foreman
daa0e96062
SWDEV-200614 - [Schneider] Crash in Agisoft when run in mGPU environment - Add a workaround for memory pinning path. It will perform 2-step copy to make sure memory pinning doesn't occur on the first unaligned page, because in Windows memory manager can have CPU access to the allocation header in another thread and a race condition is possible - change some default setting for staging and pinned paths, because PCIE gen3 performance. Affected files ... ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palsettings.cpp#96 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palvirtual.cpp#150 edit ... //depot/stg/opencl/drivers/opencl/runtime/utils/flags.hpp#317 edit
292 řádky
17 KiB
C++
292 řádky
17 KiB
C++
//
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// Copyright (c) 2009 Advanced Micro Devices, Inc. All rights reserved.
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//
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#ifndef FLAGS_HPP_
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#define FLAGS_HPP_
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#define RUNTIME_FLAGS(debug,release,release_on_stg) \
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\
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debug(int, LOG_LEVEL, 0, \
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"The default log level") \
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debug(uint, DEBUG_GPU_FLAGS, 0, \
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"The debug options for GPU device") \
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release(uint, GPU_MAX_COMMAND_QUEUES, 300, \
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"The maximum number of concurrent Virtual GPUs") \
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release(size_t, CQ_THREAD_STACK_SIZE, 256*Ki, /* @todo: that much! */ \
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"The default command queue thread stack size") \
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release(int, GPU_MAX_WORKGROUP_SIZE, 0, \
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"Maximum number of workitems in a workgroup for GPU, 0 -use default") \
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release(int, GPU_MAX_WORKGROUP_SIZE_2D_X, 0, \
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"Maximum number of workitems in a 2D workgroup for GPU, x component, 0 -use default") \
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release(int, GPU_MAX_WORKGROUP_SIZE_2D_Y, 0, \
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"Maximum number of workitems in a 2D workgroup for GPU, y component, 0 -use default") \
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release(int, GPU_MAX_WORKGROUP_SIZE_3D_X, 0, \
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"Maximum number of workitems in a 3D workgroup for GPU, x component, 0 -use default") \
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release(int, GPU_MAX_WORKGROUP_SIZE_3D_Y, 0, \
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"Maximum number of workitems in a 3D workgroup for GPU, y component, 0 -use default") \
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release(int, GPU_MAX_WORKGROUP_SIZE_3D_Z, 0, \
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"Maximum number of workitems in a 3D workgroup for GPU, z component, 0 -use default") \
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debug(bool, CPU_MEMORY_GUARD_PAGES, false, \
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"Use guard pages for CPU memory") \
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debug(size_t, CPU_MEMORY_GUARD_PAGE_SIZE, 64, \
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"Size in KB of CPU memory guard page") \
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debug(size_t, CPU_MEMORY_ALIGNMENT_SIZE, 256, \
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"Size in bytes for the default alignment for guarded memory on CPU") \
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debug(size_t, PARAMETERS_MIN_ALIGNMENT, 16, \
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"Minimum alignment required for the abstract parameters stack") \
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debug(size_t, MEMOBJ_BASE_ADDR_ALIGN, 4*Ki, \
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"Alignment of the base address of any allocate memory object") \
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release(cstring, GPU_DEVICE_ORDINAL, "", \
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"Select the device ordinal (comma seperated list of available devices)") \
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release(bool, REMOTE_ALLOC, false, \
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"Use remote memory for the global heap allocation") \
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release(uint, GPU_MAX_HEAP_SIZE, 100, \
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"Set maximum size of the GPU heap to % of board memory") \
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release(uint, GPU_STAGING_BUFFER_SIZE, 1024, \
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"Size of the GPU staging buffer in KiB") \
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release(bool, GPU_DUMP_BLIT_KERNELS, false, \
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"Dump the kernels for blit manager") \
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release(uint, GPU_BLIT_ENGINE_TYPE, 0x0, \
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"Blit engine type: 0 - Default, 1 - Host, 2 - CAL, 3 - Kernel") \
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release(bool, GPU_FLUSH_ON_EXECUTION, false, \
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"Submit commands to HW on every operation. 0 - Disable, 1 - Enable") \
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release(bool, GPU_USE_SYNC_OBJECTS, true, \
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"If enabled, use sync objects instead of polling") \
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release(bool, CL_KHR_FP64, true, \
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"Enable/Disable support for double precision") \
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release(cstring, AMD_OCL_BUILD_OPTIONS, 0, \
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"Set clBuildProgram() and clCompileProgram()'s options (override)") \
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release(cstring, AMD_OCL_BUILD_OPTIONS_APPEND, 0, \
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"Append clBuildProgram() and clCompileProgram()'s options") \
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release(cstring, AMD_OCL_LINK_OPTIONS, 0, \
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"Set clLinkProgram()'s options (override)") \
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release(cstring, AMD_OCL_LINK_OPTIONS_APPEND, 0, \
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"Append clLinkProgram()'s options") \
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release(cstring, AMD_OCL_SC_LIB, 0, \
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"Set shader compiler shared library name or path") \
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debug(bool, AMD_OCL_ENABLE_MESSAGE_BOX, false, \
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"Enable the error dialog on Windows") \
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release(size_t, GPU_PINNED_XFER_SIZE, 32, \
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"The pinned buffer size for pinning in read/write transfers") \
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release(size_t, GPU_PINNED_MIN_XFER_SIZE, 1024, \
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"The minimal buffer size for pinned read/write transfers in KBytes") \
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release(size_t, GPU_RESOURCE_CACHE_SIZE, 64, \
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"The resource cache size in MB") \
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release(size_t, GPU_MAX_SUBALLOC_SIZE, 4096, \
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"The maximum size accepted for suballocaitons in KB") \
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release(bool, GPU_FORCE_64BIT_PTR, 0, \
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"Forces 64 bit pointers on GPU") \
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release(bool, GPU_FORCE_OCL20_32BIT, 0, \
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"Forces 32 bit apps to take CLANG\HSAIL path") \
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release(bool, GPU_RAW_TIMESTAMP, 0, \
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"Reports GPU raw timestamps in GPU timeline") \
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release(size_t, GPU_NUM_MEM_DEPENDENCY, 256, \
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"Number of memory objects for dependency tracking") \
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release(size_t, GPU_XFER_BUFFER_SIZE, 0, \
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"Transfer buffer size for image copy optimization in KB") \
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release(bool, GPU_IMAGE_DMA, true, \
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"Enable DRM DMA for image transfers") \
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release(uint, GPU_SINGLE_ALLOC_PERCENT, 85, \
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"Maximum size of a single allocation as percentage of total") \
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release(uint, GPU_NUM_COMPUTE_RINGS, 2, \
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"GPU number of compute rings. 0 - disabled, 1 , 2,.. - the number of compute rings") \
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release(int, GPU_SELECT_COMPUTE_RINGS_ID, -1, \
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"GPU select the compute rings ID -1 - disabled, 0 , 1,.. - the forced compute rings ID for submission") \
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release(uint, GPU_WORKLOAD_SPLIT, 22, \
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"Workload split size") \
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release(bool, GPU_USE_SINGLE_SCRATCH, false, \
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"Use single scratch buffer per device instead of per HW ring") \
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release(bool, AMD_OCL_WAIT_COMMAND, false, \
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"1 = Enable a wait for every submitted command") \
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/* HSAIL is by default, except Linux 32bit, because of known Catalyst 32bit issue */ \
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release(bool, GPU_HSAIL_ENABLE, LP64_SWITCH(LINUX_SWITCH(false,true),true), \
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"Enable HSAIL on dGPU stack (requires CI+ HW)") \
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release(uint, GPU_PRINT_CHILD_KERNEL, 0, \
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"Prints the specified number of the child kernels") \
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release(bool, GPU_USE_DEVICE_QUEUE, false, \
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"Use a dedicated device queue for the actual submissions") \
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release(bool, GPU_ENABLE_LARGE_ALLOCATION, true, \
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"Enable >4GB single allocations") \
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release(bool, AMD_THREAD_TRACE_ENABLE, true, \
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"Enable thread trace extension") \
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release(uint, OPENCL_VERSION, (IS_BRAHMA ? 120 : 200), \
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"Force GPU opencl verison") \
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release(bool, HSA_LOCAL_MEMORY_ENABLE, true, \
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"Enable HSA device local memory usage") \
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release(uint, HSA_KERNARG_POOL_SIZE, 512 * 1024, \
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"Kernarg pool size") \
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release(bool, HSA_ENABLE_COARSE_GRAIN_SVM, true, \
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"Enable device memory for coarse grain SVM allocations") \
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release(bool, GPU_IFH_MODE, false, \
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"1 = Enable GPU IFH (infinitely fast hardware) mode. Any other value keeps setting disabled.") \
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release(bool, GPU_MIPMAP, true, \
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"Enables GPU mipmap extension") \
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release(uint, GPU_ENABLE_PAL, 2, \
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"Enables PAL backend. 0 - GSL(default), 1 - PAL, 2 - GSL and PAL") \
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release(bool, DISABLE_DEFERRED_ALLOC, false, \
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"Disables deferred memory allocation on device") \
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release(int, AMD_GPU_FORCE_SINGLE_FP_DENORM, -1, \
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"Force denorm for single precision: -1 - don't force, 0 - disable, 1 - enable") \
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release(uint, OCL_SET_SVM_SIZE, 4*16384, \
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"set SVM space size for discrete GPU") \
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debug(uint, OCL_SYSMEM_REQUIREMENT, 2, \
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"Use flag to change the minimum requirement of system memory not to downgrade") \
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debug(bool, GPU_ENABLE_HW_DEBUG, false, \
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"Enable HW DEBUG for GPU") \
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release(uint, GPU_WAVES_PER_SIMD, 0, \
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"Force the number of waves per SIMD (1-10)") \
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release(bool, GPU_WAVE_LIMIT_ENABLE, false, \
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"1 = Enable adaptive wave limiter") \
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release(bool, OCL_STUB_PROGRAMS, false, \
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"1 = Enables OCL programs stubing") \
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release(bool, GPU_ANALYZE_HANG, false, \
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"1 = Enables GPU hang analysis") \
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release(uint, GPU_MAX_REMOTE_MEM_SIZE, 2, \
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"Maximum size (in Ki) that allows device memory substitution with system") \
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release(bool, GPU_ADD_HBCC_SIZE, false, \
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"Add HBCC size to the reported device memory") \
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release_on_stg(uint, GPU_WAVE_LIMIT_CU_PER_SH, 0, \
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"Assume the number of CU per SH for wave limiter") \
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release_on_stg(uint, GPU_WAVE_LIMIT_MAX_WAVE, 10, \
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"Set maximum waves per SIMD to try for wave limiter") \
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release_on_stg(uint, GPU_WAVE_LIMIT_RUN, 20, \
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"Set running factor for wave limiter") \
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release_on_stg(cstring, GPU_WAVE_LIMIT_DUMP, "", \
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"File path prefix for dumping wave limiter output") \
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release_on_stg(cstring, GPU_WAVE_LIMIT_TRACE, "", \
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"File path prefix for tracing wave limiter") \
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release(bool, OCL_CODE_CACHE_ENABLE, false, \
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"1 = Enable compiler code cache") \
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release(bool, OCL_CODE_CACHE_RESET, false, \
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"1 = Reset the compiler code cache storage") \
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release(bool, GPU_VEGA10_ONLY, VEGA10_ONLY, \
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"1 = Report vega10 only on OCL/ROCR") \
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release_on_stg(bool, PAL_DISABLE_SDMA, false, \
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"1 = Disable SDMA for PAL") \
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release(uint, PAL_RGP_DISP_COUNT, 50, \
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"The number of dispatches for RGP capture with SQTT") \
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release(bool, GPU_ENABLE_WAVE32_MODE, true, \
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"Enables Wave32 compilation in HW if available") \
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release(bool, GPU_ENABLE_LC, true, \
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"Enables LC path") \
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release(bool, GPU_ENABLE_HW_P2P, false, \
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"Enables HW P2P path") \
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release(bool, GPU_ENABLE_COOP_GROUPS, false, \
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"Enables cooperative group launch") \
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release(uint, GPU_MAX_COMMAND_BUFFERS, 8, \
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"The maximum number of command buffers allocated per queue") \
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release(uint, GPU_MAX_HW_QUEUES, 4, \
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"The maximum number of HW queues allocated per device") \
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release(bool, GPU_IMAGE_BUFFER_WAR, true, \
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"Enables image buffer workaround") \
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release(cstring, HIP_VISIBLE_DEVICES, "", \
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"Only devices whose index is present in the sequence are visible to HIP") \
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release(cstring, CUDA_VISIBLE_DEVICES, "", \
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"Only devices whose index is present in the sequence are visible to HIP") \
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release(bool, GPU_ENABLE_WGP_MODE, true, \
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"Enables WGP Mode in HW if available") \
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release(bool, GPU_DUMP_CODE_OBJECT, false, \
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"Enable dump code object") \
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release(uint, GPU_MAX_USWC_ALLOC_SIZE, 2048, \
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"Set a limit in Mb on the maximum USWC allocation size" \
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"-1 = No limit") \
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release(uint, AMD_SERIALIZE_KERNEL, 0, \
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"Serialize kernel enqueue, 0x1 = Wait for completion before enqueue" \
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"0x2 = Wait for completion after enqueue 0x3 = both") \
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release(uint, AMD_SERIALIZE_COPY, 0, \
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"Serialize copies, 0x1 = Wait for completion before enqueue" \
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"0x2 = Wait for completion after enqueue 0x3 = both")
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namespace amd {
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extern bool IS_HIP;
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extern bool IS_LEGACY;
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//! \addtogroup Utils
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// @{
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struct Flag {
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enum Type {
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Tinvalid = 0,
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Tbool, //!< A boolean type flag (true, false).
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Tint, //!< An integer type flag (signed).
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Tuint, //!< An integer type flag (unsigned).
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Tsize_t, //!< A size_t type flag.
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Tcstring //!< A string type flag.
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};
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#define DEFINE_FLAG_NAME(type, name, value, help) k##name,
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enum Name {
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RUNTIME_FLAGS(DEFINE_FLAG_NAME, DEFINE_FLAG_NAME, DEFINE_FLAG_NAME)
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numFlags_
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};
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#undef DEFINE_FLAG_NAME
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#define CAN_SET(type, name, v, h) static const bool cannotSet##name = false;
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#define CANNOT_SET(type, name, v, h) static const bool cannotSet##name = true;
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#ifdef DEBUG
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RUNTIME_FLAGS(CAN_SET, CAN_SET, CAN_SET)
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#else // !DEBUG
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RUNTIME_FLAGS(CANNOT_SET, CAN_SET, CANNOT_SET)
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#endif // !DEBUG
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#undef CAN_SET
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#undef CANNOT_SET
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private:
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static Flag flags_[];
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public:
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static char* envstr_;
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const char* name_;
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const void* value_;
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Type type_;
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bool isDefault_;
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public:
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static bool init();
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static void tearDown();
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bool setValue(const char* value);
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static bool isDefault(Name name) { return flags_[name].isDefault_; }
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};
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#define flagIsDefault(name) \
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(amd::Flag::cannotSet##name || amd::Flag::isDefault(amd::Flag::k##name))
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#define setIfNotDefault(var, opt, other) \
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if (!flagIsDefault(opt)) \
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var = (opt);\
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else \
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var = (other);
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// @}
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} // namespace amd
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#ifdef _WIN32
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# define EXPORT_FLAG extern "C" __declspec(dllexport)
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#else // !_WIN32
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# define EXPORT_FLAG extern "C"
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#endif // !_WIN32
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#define DECLARE_RELEASE_FLAG(type, name, value, help) EXPORT_FLAG type name;
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#ifdef DEBUG
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# define DECLARE_DEBUG_FLAG(type, name, value, help) EXPORT_FLAG type name;
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#else // !DEBUG
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# define DECLARE_DEBUG_FLAG(type, name, value, help) const type name = value;
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#endif // !DEBUG
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RUNTIME_FLAGS(DECLARE_DEBUG_FLAG, DECLARE_RELEASE_FLAG, DECLARE_DEBUG_FLAG);
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#undef DECLARE_DEBUG_FLAG
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#undef DECLARE_RELEASE_FLAG
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#endif /*FLAGS_HPP_*/
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