Laurent Morichetti
97 lines
4.7 KiB
C++
97 lines
4.7 KiB
C++
/* Copyright (c) 2010-present Advanced Micro Devices, Inc.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE. */
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#ifndef GPUSCHED_HPP_
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#define GPUSCHED_HPP_
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#include "hsa.h"
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namespace gpu {
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//! AmdAqlWrap slot state
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enum AqlWrapState {
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AQL_WRAP_FREE = 0,
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AQL_WRAP_RESERVED,
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AQL_WRAP_READY,
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AQL_WRAP_MARKER,
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AQL_WRAP_BUSY,
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AQL_WRAP_DONE
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};
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struct AmdVQueueHeader {
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uint32_t aql_slot_num; //!< [LRO/SRO] The total number of the AQL slots (multiple of 64).
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uint32_t event_slot_num; //!< [LRO] The number of kernel events in the events buffer
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uint64_t event_slot_mask; //!< [LRO] A pointer to the allocation bitmask array for the events
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uint64_t event_slots; //!< [LRO] Pointer to a buffer for the events.
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// Array of event_slot_num entries of AmdEvent
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uint64_t aql_slot_mask; //!< [LRO/SRO]A pointer to the allocation bitmask for aql_warp slots
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uint32_t command_counter; //!< [LRW] The global counter for the submitted commands into the queue
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uint32_t wait_size; //!< [LRO] The wait list size (in clk_event_t)
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uint32_t arg_size; //!< [LRO] The size of argument buffer (in bytes)
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uint32_t mask_groups; //!< Processed mask groups by one thread
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uint64_t
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kernel_table; //!< [LRO] Pointer to an array with all kernel objects (ulong for each entry)
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uint32_t reserved[2]; //!< For the future usage
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};
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struct AmdAqlWrap {
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uint32_t state; //!< [LRW/SRW] The current state of the AQL wrapper: FREE, RESERVED, READY,
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// MARKER, BUSY and DONE. The block could be returned back to a free state.
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uint32_t enqueue_flags; //!< [LWO/SRO] Contains the flags for the kernel execution start
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uint32_t command_id; //!< [LWO/SRO] The unique command ID
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uint32_t child_counter; //!< [LRW/SRW] Counter that determine the launches of child kernels.
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// It’s incremented on the
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// start and decremented on the finish. The parent kernel can be considered as
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// done when the value is 0 and the state is DONE
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uint64_t completion; //!< [LWO/SRO] CL event for the current execution (clk_event_t)
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uint64_t parent_wrap; //!< [LWO/SRO] Pointer to the parent AQL wrapper (AmdAqlWrap*)
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uint64_t wait_list; //!< [LRO/SRO] Pointer to an array of clk_event_t objects (64 bytes default)
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uint32_t wait_num; //!< [LWO/SRO] The number of cl_event_wait objects
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uint32_t reserved[5]; //!< For the future usage
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hsa_kernel_dispatch_packet_t aql; //!< [LWO/SRO] AQL packet – 64 bytes AQL packet
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};
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struct AmdEvent {
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uint32_t state; //!< [LRO/SRW] Event state: START, END, COMPLETE
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uint32_t counter; //!< [LRW] Event retain/release counter. 0 means the event is free
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uint64_t timer[3]; //!< [LRO/SWO] Timer values for profiling for each state
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uint64_t captureInfo; //!< [LRW/SRO] Profiling capture info for CLK_PROFILING_COMMAND_EXEC_TIME
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};
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struct SchedulerParam {
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uint32_t signal; //!< Signal to stop the child queue(address must be 16 bytes aligned)
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uint32_t eng_clk; //!< Engine clock in Mhz
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uint64_t hw_queue; //!< Address to HW queue
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uint64_t hsa_queue; //!< Address to HSA dummy queue
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uint32_t useATC; //!< GPU access to shader program by ATC.
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uint32_t scratchSize; //!< Scratch buffer size
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uint64_t scratch; //!< GPU address to the scratch buffer
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uint32_t numMaxWaves; //!< The max number of possible waves
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uint32_t releaseHostCP; //!< Releases CP on the host queue
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uint64_t parentAQL; //!< Host parent AmdAqlWrap packet
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uint32_t dedicatedQueue; //!< Scheduler uses a dedicated queue
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uint32_t scratchOffset; //!< Scratch buffer offset
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uint32_t reserved[2]; //!< Reserved
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};
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} // namespace gpu
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#endif
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