Alex Xie
80 строки
4.2 KiB
C++
80 строки
4.2 KiB
C++
/* Copyright (c) 2008-present Advanced Micro Devices, Inc.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE. */
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#pragma once
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#ifndef WITHOUT_HSA_BACKEND
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namespace roc {
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//! Alignment restriciton for the pinned memory
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static constexpr size_t PinnedMemoryAlignment = 4 * Ki;
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//! Specific defines for images for Dynamic Parallelism
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static constexpr uint DeviceQueueMaskSize = 32;
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typedef uint HsaDeviceId;
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struct AMDDeviceInfo {
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const char* machineTarget_; //!< Machine target
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const char* machineTargetLC_;//!< Machine target for LC
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uint simdPerCU_; //!< Number of SIMDs per CU
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uint simdWidth_; //!< Number of workitems processed per SIMD
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uint simdInstructionWidth_; //!< Number of instructions processed per SIMD
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uint memChannelBankWidth_; //!< Memory channel bank width
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uint localMemSizePerCU_; //!< Local memory size per CU
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uint localMemBanks_; //!< Number of banks of local memory
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uint gfxipMajor_; //!< The core engine GFXIP Major version
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uint gfxipMinor_; //!< The core engine GFXIP Minor version
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uint gfxipStepping_; //!< The core engine GFXIP Stepping version
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uint pciDeviceId_; //!< PCIe device id
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};
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constexpr HsaDeviceId HSA_INVALID_DEVICE_ID = -1;
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static constexpr AMDDeviceInfo DeviceInfo[] = {
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/* KAVERI_SPECTRE */ {"Spectre", "", 4, 16, 1, 256, 64 * Ki, 32, 7, 0, 1, 0},
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/* KAVERI_SPOOKY */ {"Spooky", "", 4, 16, 1, 256, 64 * Ki, 32, 7, 0, 1, 0},
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/* HAWAII */ {"Hawaii", "gfx701", 4, 16, 1, 256, 64 * Ki, 32, 7, 0, 1, 0},
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/* CARRIZO */ {"Carrizo", "gfx801", 4, 16, 1, 256, 64 * Ki, 32, 8, 0, 1, 0},
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/* TONGA */ {"Tonga", "gfx802", 4, 16, 1, 256, 64 * Ki, 32, 8, 0, 2, 0},
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/* ICELAND */ {"Iceland", "gfx802", 4, 16, 1, 256, 64 * Ki, 32, 8, 0, 2, 0},
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/* FIJI */ {"Fiji", "gfx803", 4, 16, 1, 256, 64 * Ki, 32, 8, 0, 3, 0},
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/* ELLESMERE */ {"Ellesmere", "gfx803", 4, 16, 1, 256, 64 * Ki, 32, 8, 0, 3, 0},
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/* BAFFIN */ {"Baffin", "gfx803", 4, 16, 1, 256, 64 * Ki, 32, 8, 0, 3, 0},
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/* VEGA10 */ {"gfx900", "gfx900", 4, 16, 1, 256, 64 * Ki, 32, 9, 0, 0, 0},
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/* VEGA10_HBCC */ {"gfx901", "gfx901", 4, 16, 1, 256, 64 * Ki, 32, 9, 0, 1, 0},
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/* RAVEN */ {"gfx902", "gfx902", 4, 16, 1, 256, 64 * Ki, 32, 9, 0, 2, 0},
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/* VEGA12 */ {"gfx904", "gfx904", 4, 16, 1, 256, 64 * Ki, 32, 9, 0, 4, 0},
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/* VEGA20 */ {"gfx906", "gfx906", 4, 16, 1, 256, 64 * Ki, 32, 9, 0, 6, 0},
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/* ARCTURUS */ {"gfx908", "gfx908", 4, 16, 1, 256, 64 * Ki, 32, 9, 0, 8, 0},
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/* NAVI10 */ {"gfx1010", "gfx1010", 2, 32, 1, 256, 64 * Ki, 32, 10, 1, 0, 0},
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/* NAVI12 */ {"gfx1011", "gfx1011", 2, 32, 1, 256, 64 * Ki, 32, 10, 1, 1, 0},
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/* NAVI14 */ {"gfx1012", "gfx1012", 2, 32, 1, 256, 64 * Ki, 32, 10, 1, 2, 0},
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/* SIENNA_CICHILD */ {"gfx1030", "gfx1030", 2, 32, 1, 256, 64 * Ki, 32, 10, 3, 0, 0},
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/* NAVY_FLOUNDER */ {"gfx1031", "gfx1031", 2, 32, 1, 256, 64 * Ki, 32, 10, 3, 1, 0},
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/* DIMGREY CAVEFISH*/{"gfx1032", "gfx1032", 2, 32, 1, 256, 64 * Ki, 32, 10, 3, 2, 0}
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};
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}
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constexpr uint kMaxAsyncQueues = 8; // set to match the number of pipes, which is 8
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#endif
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