Danylo Lytovchenko
650 lines
425 KiB
C++
650 lines
425 KiB
C++
/* Copyright (c) 2009 - 2021 Advanced Micro Devices, Inc.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE. */
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#ifndef FLAGS_HPP_
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#define FLAGS_HPP_
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#define RUNTIME_FLAGS(debug, release, release_on_stg) \
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\
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release(int, AMD_LOG_LEVEL, 0, "The default log level") release( \
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uint, AMD_LOG_MASK, 0X7FFFFFFF, \
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"The mask to enable specific kinds of logs") release(cstring, AMD_LOG_LEVEL_FILE, "", \
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"Set output file for AMD_LOG_LEVEL, " \
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"Default is stderr") release(size_t, \
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AMD_LOG_LEVEL_SIZE, \
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2048, \
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"The max " \
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"size of " \
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"AMD_LOG " \
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"generate" \
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"d in MB " \
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"if " \
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"printed " \
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"to a " \
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"file") \
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debug(uint, DEBUG_GPU_FLAGS, 0, "The debug options for GPU device") release( \
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size_t, CQ_THREAD_STACK_SIZE, 256 * Ki, /* @todo: that much! */ \
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"The default command queue thread stack size") release(int, GPU_MAX_WORKGROUP_SIZE, 0, \
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"Maximum number of workitems in " \
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"a workgroup for GPU, 0 -use " \
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"default") \
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debug(bool, CPU_MEMORY_GUARD_PAGES, false, "Use guard pages for CPU memory") debug( \
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size_t, CPU_MEMORY_GUARD_PAGE_SIZE, \
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64, "Size in KB of CPU memory guard page") debug(size_t, CPU_MEMORY_ALIGNMENT_SIZE, \
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256, \
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"Size in bytes for the default " \
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"alignment for guarded memory on " \
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"CPU") debug(size_t, \
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PARAMETERS_MIN_ALIGNMENT, \
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NATIVE_ALIGNMENT_SIZE, \
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"Minimum alignment " \
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"required for the " \
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"abstract parameters " \
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"stack") debug(size_t, \
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MEMOBJ_BASE_ADDR_ALIGN, \
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4 * Ki, \
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"Align" \
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"ment " \
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"of " \
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"the " \
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"base " \
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"addre" \
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"ss " \
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"of " \
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"any " \
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"alloc" \
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"ate " \
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"memor" \
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"y " \
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"objec" \
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"t") \
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release( \
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uint, ROC_HMM_FLAGS, \
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0, "ROCm HMM configuration flags") release(cstring, GPU_DEVICE_ORDINAL, "", \
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"Select the device ordinal (comma " \
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"seperated list of available " \
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"devices)") release(bool, \
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REMOTE_ALLOC, \
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false, \
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"Use remote " \
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"memory for the " \
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"global heap " \
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"allocation") \
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release(uint, GPU_CP_DMA_COPY_SIZE, 1, \
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"Set maximum size of CP DMA copy in KiB") release(uint, \
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GPU_MAX_HEAP_SIZE, \
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100, \
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"Set maximum size of " \
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"the GPU heap to % " \
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"of board memory") \
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release( \
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uint, GPU_STAGING_BUFFER_SIZE, 4, \
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"Size of the GPU staging buffer in MiB") release(bool, \
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GPU_DUMP_BLIT_KERNELS, \
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false, \
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"Dump the kernels for " \
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"blit manager") \
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release(uint, GPU_BLIT_ENGINE_TYPE, 0x0, \
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"Blit engine type: 0 - Default, 1 - Host, 2 - CAL, 3 - Kernel") \
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release(bool, GPU_FLUSH_ON_EXECUTION, false, \
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"Submit commands to HW on every operation. 0 - Disable, 1 " \
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"- Enable") release(bool, CL_KHR_FP64, true, \
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"Enable/Disable support for double " \
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"precision") release(cstring, \
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AMD_OCL_BUILD_OPTIONS, \
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0, \
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"Set " \
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"clBuildProgram() " \
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"and " \
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"clCompileProgram(" \
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")'s options " \
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"(override)") \
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release(cstring, AMD_OCL_BUILD_OPTIONS_APPEND, 0, \
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"Append clBuildProgram() and clCompileProgram()'s " \
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"options") release(cstring, AMD_OCL_LINK_OPTIONS, 0, \
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"Set clLinkProgram()'s options " \
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"(override)") \
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release( \
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cstring, AMD_OCL_LINK_OPTIONS_APPEND, 0, \
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"Append clLinkProgram()'s options") debug(cstring, \
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AMD_OCL_SUBST_OBJFILE, \
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0, \
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"Specify " \
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"binary " \
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"substitution" \
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" config " \
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"file for " \
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"OpenCL") \
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release( \
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size_t, GPU_PINNED_XFER_SIZE, 32, \
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"The pinned buffer size for pinning in read/write " \
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"transfers in MiB") release(size_t, \
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GPU_PINNED_MIN_XFER_SIZE, \
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128, \
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"The minimal buffer " \
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"size for pinned " \
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"read/write transfers " \
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"in MiB") release(size_t, \
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GPU_RESOURCE_CACHE_SIZE, \
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64, \
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"The " \
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"reso" \
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"urce" \
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" cac" \
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"he " \
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"size" \
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" in " \
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"MB") \
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release( \
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size_t, GPU_MAX_SUBALLOC_SIZE, 4096, \
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"The maximum size accepted for suballocations " \
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"in KB") release(size_t, GPU_NUM_MEM_DEPENDENCY, \
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256, \
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"Number of memory objects for " \
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"dependency tracking") \
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release( \
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size_t, GPU_XFER_BUFFER_SIZE, 0, \
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"Transfer buffer size for image copy " \
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"optimization in KB") release(bool, \
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GPU_IMAGE_DMA, \
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true, \
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"Enable DRM " \
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"DMA for " \
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"image " \
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"transfers") \
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release( \
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uint, GPU_SINGLE_ALLOC_PERCENT, 100, \
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"Maximum size of a single allocation " \
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"as percentage of total") release(uint, \
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GPU_NUM_COMPUTE_RINGS, \
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2, \
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"GPU " \
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"numb" \
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"er " \
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"of " \
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"comp" \
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"ute " \
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"ring" \
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"s. " \
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"0 - " \
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"disa" \
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"bled" \
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", 1 " \
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", " \
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"2,.." \
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" - " \
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"the " \
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"numb" \
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"er " \
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"of " \
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"comp" \
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"ute " \
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"ring" \
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"s") \
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release( \
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bool, AMD_OCL_WAIT_COMMAND, false, \
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"1 = Enable a wait for every " \
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"submitted command") release(uint, \
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GPU_PRINT_CHILD_KERNEL, \
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0, \
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"Print" \
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"s " \
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"the " \
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"speci" \
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"fied " \
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"numbe" \
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"r of " \
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"the " \
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"child" \
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" kern" \
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"els") \
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release(bool, GPU_USE_DEVICE_QUEUE, \
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false, \
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"Use a dedicated device " \
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"queue for the actual " \
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"submissions") release(bool, \
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AMD_THREAD_TRACE_ENABLE, \
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true, \
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"Ena" \
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"ble" \
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" th" \
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"rea" \
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"d " \
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"tra" \
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"ce " \
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"ext" \
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"ens" \
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"io" \
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"n") \
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release( \
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uint, OPENCL_VERSION, 200, \
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"Force GPU opencl version") release(bool, \
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HSA_LOCAL_MEMORY_ENABLE, \
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true, \
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"Enable HSA device local memory usage") \
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release( \
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uint, \
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HSA_KERNARG_POOL_SIZE, \
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1024 * 1024, \
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"Kernarg pool size") release(bool, \
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GPU_MIPMAP, \
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true, \
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"Enables GPU mipmap extension") \
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release( \
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uint, \
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GPU_ENABLE_PAL, \
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2, \
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"Enables PAL " \
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"backend. 0 - ROC, " \
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"1 - PAL, 2 - ROC " \
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"or PAL") release(bool, DISABLE_DEFERRED_ALLOC, \
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false, \
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"Disables deferred memory allocation on device") \
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release( \
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int, \
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AMD_GPU_FORCE_SINGLE_FP_DENORM, \
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-1, \
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"Force denorm " \
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"for single " \
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"precision: -1 " \
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"- don't " \
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"force, 0 - " \
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"disable, 1 - " \
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"enable") \
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release( \
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uint, \
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OCL_SET_SVM_SIZE, \
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4 * 16384, \
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"set SVM " \
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"space " \
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"size for " \
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"discrete " \
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"GPU") release(uint, \
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GPU_WAVES_PER_SIMD, \
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0, \
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"Force the number of waves per SIMD (1-10)") \
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release( \
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bool, \
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OCL_STUB_PROGRAMS, \
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false, \
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"1 = " \
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"Enable" \
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"s OCL " \
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"progra" \
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"ms " \
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"stubin" \
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"g") \
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release( \
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bool, \
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GPU_ANALYZE_HANG, \
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false, \
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"1 " \
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"= " \
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"En" \
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"ab" \
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"le" \
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"s " \
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"GP" \
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"U " \
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"ha" \
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"ng" \
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" a" \
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"na" \
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"ly" \
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"si" \
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"s") \
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release( \
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uint, \
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GPU_MAX_REMOTE_MEM_SIZE, \
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2, \
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"Maximum size (in Ki) that allows device memory substitution with system") \
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release(bool, \
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GPU_ADD_HBCC_SIZE, \
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false, \
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"Add HBCC size to the reported device memory") release(bool, \
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PAL_DISABLE_SDMA, \
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false, \
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"1 = Disable SDMA for PAL") release(uint, \
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PAL_RGP_DISP_COUNT, \
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10000, \
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"The number of dispatches for RGP capture with SQTT") release(uint, \
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PAL_MALL_POLICY, \
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0, \
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"Controls the behaviour of allocations with respect to the MALL" \
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"0 = MALL policy is decided by KMD" \
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"1 = Allocations are never put through the MALL" \
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"2 = Allocations will always be put through the MALL") release(bool, \
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GPU_ENABLE_WAVE32_MODE, \
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true, \
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"Enables Wave32 compilation in HW if available") release(bool, \
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GPU_ENABLE_LC, \
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true, \
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"Enables LC path") release(bool, GPU_ENABLE_HW_P2P, \
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false, \
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"Enables HW P2P path") release(bool, \
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GPU_ENABLE_COOP_GROUPS, \
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true, \
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"Enables cooperative group launch") release(uint, \
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GPU_MAX_COMMAND_BUFFERS, \
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8, \
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"The maximum number of command buffers allocated per queue") release(uint, \
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GPU_MAX_HW_QUEUES, \
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4, \
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"The maximum number of HW queues allocated per device") release(bool, GPU_IMAGE_BUFFER_WAR, true, \
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"Enables image buffer workaround") release(cstring, \
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HIP_VISIBLE_DEVICES, \
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"", \
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"Only devices whose index is present in the sequence are visible to HIP") release(cstring, \
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CUDA_VISIBLE_DEVICES, \
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"", \
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"Only devices whose index is present in the sequence are visible to CUDA") \
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release(bool, \
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GPU_ENABLE_WGP_MODE, \
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true, \
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"Enables WGP Mode in HW if available") \
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release( \
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bool, \
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GPU_DUMP_CODE_OBJECT, \
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false, \
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"Enable dump code object") release(uint, \
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GPU_MAX_USWC_ALLOC_SIZE, 2048, \
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"Set a limit in Mb on the maximum USWC allocation size" \
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"-1 = No limit") \
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release( \
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uint, \
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AMD_SERIALIZE_KERNEL, \
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0, \
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"Serialize kernel enqueue, 0x1 = Wait for completion before enqueue" \
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"0x2 = Wait for completion after enqueue 0x3 = both") release(uint, \
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AMD_SERIALIZE_COPY, \
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0, \
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"Serialize copies, 0x1 = Wait for completion before enqueue" \
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"0x2 = Wait for completion after enqueue 0x3 = both") release(uint, \
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HIP_LAUNCH_BLOCKING, \
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0, \
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"Serialize kernel enqueue 0x1 = Wait for completion after enqueue," \
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"same as AMD_SERIALIZE_KERNEL=2") release(bool, \
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PAL_ALWAYS_RESIDENT, \
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false, \
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"Force memory resources to become resident at allocation time") release(uint, \
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HIP_HOST_COHERENT, \
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0, \
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"Coherent memory in hipHostMalloc, 0x1 = memory is coherent with host" \
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"0x0 = memory is not coherent between host and GPU") release(uint, AMD_OPT_FLUSH, 1, \
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"Kernel flush option , 0x0 = Use system-scope fence operations." \
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"0x1 = Use device-scope fence operations when possible.") \
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release( \
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bool, \
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AMD_DIRECT_DISPATCH, \
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false, \
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"Enable direct kernel dispatch.") release(uint, \
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HIP_HIDDEN_FREE_MEM, \
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0, \
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"Reserve free mem reporting in Mb" \
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"0 = Disable") release(size_t, \
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GPU_FORCE_BLIT_COPY_SIZE, \
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16, \
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"Use Blit until this size(in KB) for copies") release(uint, \
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ROC_ACTIVE_WAIT_TIMEOUT, \
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0, \
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"Forces active wait of GPU interrup for the timeout(us)") release(bool, \
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ROC_ENABLE_LARGE_BAR, \
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true, \
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"Enable Large Bar if supported by the device") release(bool, \
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ROC_CPU_WAIT_FOR_SIGNAL, \
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true, \
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"Enable CPU wait for dependent HSA signals.") release(bool, \
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ROC_SYSTEM_SCOPE_SIGNAL, \
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true, \
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"Enable system scope for signals (uses interrupts).") release(bool, \
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GPU_FORCE_QUEUE_PROFILING, \
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false, \
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"Force command queue profiling by default") \
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release( \
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bool, \
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HIP_MEM_POOL_SUPPORT, \
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true, \
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"Enables memory pool support in HIP") release(bool, \
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HIP_MEM_POOL_USE_VM, \
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true, \
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"Enables memory pool support in HIP") release(bool, \
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DEBUG_HIP_MEM_POOL_VMHEAP, \
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true, \
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"Enables virtual memory for memory pools") release(bool, \
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PAL_HIP_IPC_FLAG, true, \
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"Enable interprocess flag for device allocation in PAL HIP") \
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release( \
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uint, \
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PAL_FORCE_ASIC_REVISION, \
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0, \
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"Force a specific asic revision for all devices") \
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release( \
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bool, \
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PAL_EMBED_KERNEL_MD, \
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false, \
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"Enables writing kernel metadata into command buffers.") release(cstring, \
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ROC_GLOBAL_CU_MASK, \
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"", \
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"Sets a global CU mask (entered as hex value) for all queues," \
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"Each active bit represents using one CU (e.g., 0xf enables only 4 CUs)") release(size_t, PAL_PREPINNED_MEMORY_SIZE, 64, \
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"Size in KBytes of prepinned memory") release(bool, \
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AMD_CPU_AFFINITY, \
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false, \
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"Reset CPU affinity of any runtime threads") release(bool, \
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ROC_USE_FGS_KERNARG, \
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true, \
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"Use fine grain kernel args segment for supported asics") release(uint, \
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ROC_P2P_SDMA_SIZE, \
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1024, \
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"The minimum size in KB for P2P transfer with SDMA") release(uint, \
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ROC_AQL_QUEUE_SIZE, \
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16384, \
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"AQL queue size in AQL packets") \
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release( \
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uint, \
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ROC_SIGNAL_POOL_SIZE, \
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64, \
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"Initial size of HSA signal pool") \
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release(uint, \
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DEBUG_CLR_LIMIT_BLIT_WG, \
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16, \
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"Limit the number of workgroups in blit operations") release(bool, \
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DEBUG_CLR_BLIT_KERNARG_OPT, \
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false, \
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"Enable blit kernel arguments optimization") release(bool, \
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ROC_SKIP_KERNEL_ARG_COPY, \
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false, \
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"If true, then runtime can skip kernel arg copy") release(bool, \
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GPU_STREAMOPS_CP_WAIT, \
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false, \
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"Force the stream wait memory operation to wait on CP.") release(bool, HIPRTC_USE_RUNTIME_UNBUNDLER, \
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false, \
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"Set this to true to force runtime unbundler in hiprtc.") release(size_t, \
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HIP_INITIAL_DM_SIZE, \
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8 * Mi, \
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"Set initial heap size for device malloc.") \
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release( \
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bool, \
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HIP_FORCE_DEV_KERNARG, \
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true, \
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"Force device mem for kernel args.") release(bool, \
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DEBUG_CLR_GRAPH_PACKET_CAPTURE, \
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true, \
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"Enable/Disable graph packet capturing") release(bool, \
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GPU_DEBUG_ENABLE, false, \
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"Enables collection of extra info for debugger at some perf cost") \
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release( \
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cstring, \
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|
HIPRTC_COMPILE_OPTIONS_APPEND, \
|
|
"", \
|
|
"Set compile options needed for hiprtc compilation") \
|
|
release( \
|
|
cstring, \
|
|
HIPRTC_LINK_OPTIONS_APPEND, \
|
|
"", \
|
|
"Set link options needed for hiprtc compilation") \
|
|
release( \
|
|
bool, \
|
|
HIP_VMEM_MANAGE_SUPPORT, \
|
|
true, \
|
|
"Virtual Memory Management Support") \
|
|
release( \
|
|
bool, \
|
|
DEBUG_HIP_GRAPH_DOT_PRINT, \
|
|
false, \
|
|
"Enable/Disable graph debug dot print dump") release(bool, DEBUG_HIP_FORCE_ASYNC_QUEUE, false, \
|
|
"Forces grpahs into async queue mode. DEBUG_HIP_FORCE_GRAPH_QUEUES must be 1") \
|
|
release( \
|
|
uint, \
|
|
DEBUG_HIP_FORCE_GRAPH_QUEUES, \
|
|
4, \
|
|
"Forces the number of streams for the graph parallel execution") \
|
|
release( \
|
|
uint, \
|
|
DEBUG_HIP_BLOCK_SYNC, \
|
|
50, \
|
|
"Blocks synchronization on CPU until the callback processing is done") \
|
|
release(uint, \
|
|
DEBUG_CLR_MAX_BATCH_SIZE, \
|
|
1000, \
|
|
"Forces the callback to clean-up CPU submission queue") release(bool, DEBUG_CLR_SYSMEM_POOL, false, \
|
|
"Use sysmem pool implementation in runtime for amd commands") \
|
|
release(bool, \
|
|
DEBUG_HIP_KERNARG_COPY_OPT, \
|
|
true, \
|
|
"Enable/Disable multiple kern arg copies") release(bool, \
|
|
DEBUG_CLR_KERNARG_HDP_FLUSH_WA, \
|
|
false, \
|
|
"Toggle kernel arg copy workaround") release(bool, \
|
|
DEBUG_HIP_DYNAMIC_QUEUES, \
|
|
false, \
|
|
"Forces dynamic queue management") \
|
|
release( \
|
|
uint, \
|
|
HIP_SKIP_ABORT_ON_GPU_ERROR, \
|
|
true, \
|
|
"Set this to true, to avoid host side abort for GPU errors") \
|
|
release( \
|
|
bool, \
|
|
HIP_FORCE_SPIRV_CODEOBJECT, \
|
|
false, \
|
|
"Force use of SPIRV instead of device specific code object.") \
|
|
release( \
|
|
uint, \
|
|
DEBUG_CLR_BATCH_CPU_SYNC_SIZE, \
|
|
8, \
|
|
"Forces the minimum batch size for CPU sync")
|
|
|
|
namespace amd {
|
|
|
|
extern bool IS_HIP;
|
|
|
|
extern bool IS_LEGACY;
|
|
|
|
//! \addtogroup Utils
|
|
// @{
|
|
|
|
struct Flag {
|
|
enum Type {
|
|
Tinvalid = 0,
|
|
Tbool, //!< A boolean type flag (true, false).
|
|
Tint, //!< An integer type flag (signed).
|
|
Tuint, //!< An integer type flag (unsigned).
|
|
Tsize_t, //!< A size_t type flag.
|
|
Tcstring //!< A string type flag.
|
|
};
|
|
|
|
#define DEFINE_FLAG_NAME(type, name, value, help) k##name,
|
|
enum Name { RUNTIME_FLAGS(DEFINE_FLAG_NAME, DEFINE_FLAG_NAME, DEFINE_FLAG_NAME) numFlags_ };
|
|
#undef DEFINE_FLAG_NAME
|
|
|
|
#define CAN_SET(type, name, v, h) static const bool cannotSet##name = false;
|
|
#define CANNOT_SET(type, name, v, h) static const bool cannotSet##name = true;
|
|
|
|
#ifdef DEBUG
|
|
RUNTIME_FLAGS(CAN_SET, CAN_SET, CAN_SET)
|
|
#else // !DEBUG
|
|
RUNTIME_FLAGS(CANNOT_SET, CAN_SET, CANNOT_SET)
|
|
#endif // !DEBUG
|
|
|
|
#undef CAN_SET
|
|
#undef CANNOT_SET
|
|
|
|
private:
|
|
static Flag flags_[];
|
|
|
|
public:
|
|
static char* envstr_;
|
|
const char* name_;
|
|
const void* value_;
|
|
Type type_;
|
|
bool isDefault_;
|
|
|
|
public:
|
|
static bool init();
|
|
|
|
static void tearDown();
|
|
|
|
bool setValue(const char* value);
|
|
|
|
static bool isDefault(Name name) { return flags_[name].isDefault_; }
|
|
};
|
|
|
|
#define flagIsDefault(name) (amd::Flag::cannotSet##name || amd::Flag::isDefault(amd::Flag::k##name))
|
|
|
|
#define setIfNotDefault(var, opt, other) \
|
|
if (!flagIsDefault(opt)) \
|
|
var = (opt); \
|
|
else \
|
|
var = (other);
|
|
|
|
// @}
|
|
|
|
} // namespace amd
|
|
|
|
#ifdef _WIN32
|
|
#define EXPORT_FLAG extern "C" __declspec(dllexport)
|
|
#else // !_WIN32
|
|
#ifdef BUILD_STATIC_LIBS
|
|
#define EXPORT_FLAG extern
|
|
#else
|
|
#define EXPORT_FLAG extern "C"
|
|
#endif
|
|
namespace amd::flags {
|
|
#endif // !_WIN32
|
|
|
|
#define DECLARE_RELEASE_FLAG(type, name, value, help) EXPORT_FLAG type name;
|
|
#ifdef DEBUG
|
|
#define DECLARE_DEBUG_FLAG(type, name, value, help) EXPORT_FLAG type name;
|
|
#else // !DEBUG
|
|
#define DECLARE_DEBUG_FLAG(type, name, value, help) const type name = value;
|
|
#endif // !DEBUG
|
|
|
|
RUNTIME_FLAGS(DECLARE_DEBUG_FLAG, DECLARE_RELEASE_FLAG, DECLARE_DEBUG_FLAG);
|
|
|
|
#undef DECLARE_DEBUG_FLAG
|
|
#undef DECLARE_RELEASE_FLAG
|
|
#ifndef _WIN32
|
|
}
|
|
using namespace amd::flags;
|
|
#endif // !_WIN32
|
|
#endif /*FLAGS_HPP_*/
|