Anusha GodavarthySurya
70 строки
2.6 KiB
C++
70 строки
2.6 KiB
C++
/* Copyright (c) 2010 - 2021 Advanced Micro Devices, Inc.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE. */
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namespace roc {
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#define BLIT_KERNEL(...) #__VA_ARGS__
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const char* rocBlitLinearSourceCode = BLIT_KERNEL(
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// Extern
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extern void __amd_streamOpsWrite(__global uint*, __global ulong*, ulong, ulong);
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extern void __amd_streamOpsWait(__global uint*, __global ulong*, ulong, ulong, ulong);
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extern void __ockl_dm_init_v1(ulong, ulong, uint, uint);
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// Implementation
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__kernel void __amd_rocclr_streamOpsWrite(__global uint* ptrInt, __global ulong* ptrUlong,
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ulong value, ulong sizeBytes) {
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__amd_streamOpsWrite(ptrInt, ptrUlong, value, sizeBytes);
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}
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__kernel void __amd_rocclr_streamOpsWait(__global uint* ptrInt, __global ulong* ptrUlong,
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ulong value, ulong flags, ulong mask) {
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__amd_streamOpsWait(ptrInt, ptrUlong, value, flags, mask);
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}
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__kernel void __amd_rocclr_initHeap(ulong heap_to_initialize, ulong initial_blocks,
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uint heap_size, uint number_of_initial_blocks) {
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__ockl_dm_init_v1(heap_to_initialize, initial_blocks, heap_size, number_of_initial_blocks);
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}
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);
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const char* SchedulerSourceCode = BLIT_KERNEL(
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extern void __amd_scheduler_rocm(__global void*);
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__kernel void __amd_rocclr_scheduler(__global void* params) {
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__amd_scheduler_rocm(params);
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}
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);
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const char* GwsInitSourceCode = BLIT_KERNEL(
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extern void __ockl_gws_init(uint nwm1, uint rid);
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__kernel void __amd_rocclr_gwsInit(uint value) {
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__ockl_gws_init(value, 0);
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}
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);
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} // namespace roc
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