Jose Santos
35 KiB
35 KiB
| 1 | Dispatch_ID | Kernel_Name | GPU_ID | Grid_Size | Workgroup_Size | LDS_Per_Workgroup | Scratch_Per_Workitem | Arch_VGPR | Accum_VGPR | SGPR | wave_size | obj | SQ_CYCLES | SQ_BUSY_CYCLES | SQ_WAVES | SQ_INSTS_VALU_CVT | SQ_INSTS_VMEM_WR | SQ_INSTS_VMEM_RD | SQ_INSTS_VMEM | SQ_INSTS_SALU | GRBM_COUNT | GRBM_GUI_ACTIVE | TCP_GATE_EN1_sum | TCP_GATE_EN2_sum | TCP_TD_TCP_STALL_CYCLES_sum | TCP_TCR_TCP_STALL_CYCLES_sum | TA_TA_BUSY_sum | TA_BUFFER_WAVEFRONTS_sum | TD_TD_BUSY_sum | TD_TC_STALL_sum | SPI_CSN_WINDOW_VALID | SPI_CSN_BUSY | CPC_CPC_STAT_BUSY | CPC_CPC_STAT_IDLE | CPF_CPF_STAT_BUSY | CPF_CPF_STAT_STALL | TCC_CYCLE_sum | TCC_BUSY_sum | TCC_PROBE_sum | TCC_PROBE_ALL_sum | wave_size_1 | obj_1 | SQ_WAVE_CYCLES | SQ_WAIT_ANY | SQ_WAIT_INST_ANY | SQ_ACTIVE_INST_ANY | SQ_BUSY_CU_CYCLES | SQ_ACTIVE_INST_VMEM | SQ_ACTIVE_INST_LDS | SQ_ACTIVE_INST_VALU | TCP_UTCL1_TRANSLATION_MISS_sum | TCP_UTCL1_TRANSLATION_HIT_sum | TCP_UTCL1_PERMISSION_MISS_sum | TCP_UTCL1_REQUEST_sum | TA_ADDR_STALLED_BY_TC_CYCLES_sum | TA_TOTAL_WAVEFRONTS_sum | SPI_RA_WAVE_SIMD_FULL_CSN | SPI_RA_VGPR_SIMD_FULL_CSN | CPC_CPC_UTCL2IU_STALL | CPC_ME1_BUSY_FOR_PACKET_DECODE | TCC_EA_WRREQ_sum | TCC_EA_WRREQ_64B_sum | TCC_EA_WR_UNCACHED_32B_sum | TCC_EA_WRREQ_DRAM_sum | wave_size_2 | obj_2 | TCC_EA_RDREQ_IO_CREDIT_STALL[0] | TCC_EA_RDREQ_LEVEL[0] | TCC_EA_WRREQ[0] | TCC_EA_WRREQ_64B[0] | TCC_EA_RDREQ_IO_CREDIT_STALL[1] | TCC_EA_RDREQ_LEVEL[1] | TCC_EA_WRREQ[1] | TCC_EA_WRREQ_64B[1] | TCC_EA_RDREQ_IO_CREDIT_STALL[2] | TCC_EA_RDREQ_LEVEL[2] | TCC_EA_WRREQ[2] | TCC_EA_WRREQ_64B[2] | TCC_EA_RDREQ_IO_CREDIT_STALL[3] | TCC_EA_RDREQ_LEVEL[3] | TCC_EA_WRREQ[3] | TCC_EA_WRREQ_64B[3] | TCC_EA_RDREQ_IO_CREDIT_STALL[4] | TCC_EA_RDREQ_LEVEL[4] | TCC_EA_WRREQ[4] | TCC_EA_WRREQ_64B[4] | TCC_EA_RDREQ_IO_CREDIT_STALL[5] | TCC_EA_RDREQ_LEVEL[5] | TCC_EA_WRREQ[5] | TCC_EA_WRREQ_64B[5] | TCC_EA_RDREQ_IO_CREDIT_STALL[6] | TCC_EA_RDREQ_LEVEL[6] | TCC_EA_WRREQ[6] | TCC_EA_WRREQ_64B[6] | TCC_EA_RDREQ_IO_CREDIT_STALL[7] | TCC_EA_RDREQ_LEVEL[7] | TCC_EA_WRREQ[7] | TCC_EA_WRREQ_64B[7] | TCC_EA_RDREQ_IO_CREDIT_STALL[8] | TCC_EA_RDREQ_LEVEL[8] | TCC_EA_WRREQ[8] | TCC_EA_WRREQ_64B[8] | TCC_EA_RDREQ_IO_CREDIT_STALL[9] | TCC_EA_RDREQ_LEVEL[9] | TCC_EA_WRREQ[9] | TCC_EA_WRREQ_64B[9] | TCC_EA_RDREQ_IO_CREDIT_STALL[10] | TCC_EA_RDREQ_LEVEL[10] | TCC_EA_WRREQ[10] | TCC_EA_WRREQ_64B[10] | TCC_EA_RDREQ_IO_CREDIT_STALL[11] | TCC_EA_RDREQ_LEVEL[11] | TCC_EA_WRREQ[11] | TCC_EA_WRREQ_64B[11] | TCC_EA_RDREQ_IO_CREDIT_STALL[12] | TCC_EA_RDREQ_LEVEL[12] | TCC_EA_WRREQ[12] | TCC_EA_WRREQ_64B[12] | TCC_EA_RDREQ_IO_CREDIT_STALL[13] | TCC_EA_RDREQ_LEVEL[13] | TCC_EA_WRREQ[13] | TCC_EA_WRREQ_64B[13] | TCC_EA_RDREQ_IO_CREDIT_STALL[14] | TCC_EA_RDREQ_LEVEL[14] | TCC_EA_WRREQ[14] | TCC_EA_WRREQ_64B[14] | TCC_EA_RDREQ_IO_CREDIT_STALL[15] | TCC_EA_RDREQ_LEVEL[15] | TCC_EA_WRREQ[15] | TCC_EA_WRREQ_64B[15] | TCC_EA_RDREQ_IO_CREDIT_STALL[16] | TCC_EA_RDREQ_LEVEL[16] | TCC_EA_WRREQ[16] | TCC_EA_WRREQ_64B[16] | TCC_EA_RDREQ_IO_CREDIT_STALL[17] | TCC_EA_RDREQ_LEVEL[17] | TCC_EA_WRREQ[17] | TCC_EA_WRREQ_64B[17] | TCC_EA_RDREQ_IO_CREDIT_STALL[18] | TCC_EA_RDREQ_LEVEL[18] | TCC_EA_WRREQ[18] | TCC_EA_WRREQ_64B[18] | TCC_EA_RDREQ_IO_CREDIT_STALL[19] | TCC_EA_RDREQ_LEVEL[19] | TCC_EA_WRREQ[19] | TCC_EA_WRREQ_64B[19] | TCC_EA_RDREQ_IO_CREDIT_STALL[20] | TCC_EA_RDREQ_LEVEL[20] | TCC_EA_WRREQ[20] | TCC_EA_WRREQ_64B[20] | TCC_EA_RDREQ_IO_CREDIT_STALL[21] | TCC_EA_RDREQ_LEVEL[21] | TCC_EA_WRREQ[21] | TCC_EA_WRREQ_64B[21] | TCC_EA_RDREQ_IO_CREDIT_STALL[22] | TCC_EA_RDREQ_LEVEL[22] | TCC_EA_WRREQ[22] | TCC_EA_WRREQ_64B[22] | TCC_EA_RDREQ_IO_CREDIT_STALL[23] | TCC_EA_RDREQ_LEVEL[23] | TCC_EA_WRREQ[23] | TCC_EA_WRREQ_64B[23] | TCC_EA_RDREQ_IO_CREDIT_STALL[24] | TCC_EA_RDREQ_LEVEL[24] | TCC_EA_WRREQ[24] | TCC_EA_WRREQ_64B[24] | TCC_EA_RDREQ_IO_CREDIT_STALL[25] | TCC_EA_RDREQ_LEVEL[25] | TCC_EA_WRREQ[25] | TCC_EA_WRREQ_64B[25] | TCC_EA_RDREQ_IO_CREDIT_STALL[26] | TCC_EA_RDREQ_LEVEL[26] | TCC_EA_WRREQ[26] | TCC_EA_WRREQ_64B[26] | TCC_EA_RDREQ_IO_CREDIT_STALL[27] | TCC_EA_RDREQ_LEVEL[27] | TCC_EA_WRREQ[27] | TCC_EA_WRREQ_64B[27] | TCC_EA_RDREQ_IO_CREDIT_STALL[28] | TCC_EA_RDREQ_LEVEL[28] | TCC_EA_WRREQ[28] | TCC_EA_WRREQ_64B[28] | TCC_EA_RDREQ_IO_CREDIT_STALL[29] | TCC_EA_RDREQ_LEVEL[29] | TCC_EA_WRREQ[29] | TCC_EA_WRREQ_64B[29] | TCC_EA_RDREQ_IO_CREDIT_STALL[30] | TCC_EA_RDREQ_LEVEL[30] | TCC_EA_WRREQ[30] | TCC_EA_WRREQ_64B[30] | TCC_EA_RDREQ_IO_CREDIT_STALL[31] | TCC_EA_RDREQ_LEVEL[31] | TCC_EA_WRREQ[31] | TCC_EA_WRREQ_64B[31] | wave_size_3 | obj_3 | SQ_INSTS_VALU_MUL_F32 | SQ_INSTS_VALU_FMA_F32 | SQ_INSTS_VALU_TRANS_F32 | SQ_INSTS_VALU_ADD_F64 | SQ_INSTS_VALU_MUL_F64 | SQ_INSTS_VALU_FMA_F64 | SQ_INSTS_VALU_TRANS_F64 | SQ_INSTS_VALU_INT32 | TCP_VOLATILE_sum | TCP_TOTAL_ACCESSES_sum | TCP_TOTAL_READ_sum | TCP_TOTAL_WRITE_sum | TA_BUFFER_ATOMIC_WAVEFRONTS_sum | TA_BUFFER_TOTAL_CYCLES_sum | TD_ATOMIC_WAVEFRONT_sum | TD_STORE_WAVEFRONT_sum | SPI_RA_REQ_NO_ALLOC | SPI_RA_REQ_NO_ALLOC_CSN | CPC_CPC_STAT_STALL | CPC_UTCL1_STALL_ON_TRANSLATION | CPF_CPF_STAT_IDLE | CPF_CPF_TCIU_IDLE | TCC_REQ_sum | TCC_STREAMING_REQ_sum | TCC_HIT_sum | TCC_MISS_sum | wave_size_4 | obj_4 | SQ_INSTS_VSKIPPED | SQ_INSTS | SQ_INSTS_VALU | SQ_INSTS_VALU_ADD_F16 | SQ_INSTS_VALU_MUL_F16 | SQ_INSTS_VALU_FMA_F16 | SQ_INSTS_VALU_TRANS_F16 | SQ_INSTS_VALU_ADD_F32 | GRBM_SPI_BUSY | TCP_READ_TAGCONFLICT_STALL_CYCLES_sum | TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum | TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum | TCP_TA_TCP_STATE_READ_sum | TA_BUFFER_READ_WAVEFRONTS_sum | TA_BUFFER_WRITE_WAVEFRONTS_sum | TD_SPI_STALL_sum | TD_LOAD_WAVEFRONT_sum | SPI_CSN_NUM_THREADGROUPS | SPI_CSN_WAVE | CPC_CPC_TCIU_BUSY | CPC_CPC_TCIU_IDLE | CPF_CPF_TCIU_BUSY | CPF_CPF_TCIU_STALL | TCC_NC_REQ_sum | TCC_UC_REQ_sum | TCC_CC_REQ_sum | TCC_RW_REQ_sum | wave_size_5 | obj_5 | TCC_RW_REQ[0] | TCC_TOO_MANY_EA_WRREQS_STALL[0] | TCC_WRITE[0] | TCC_RW_REQ[1] | TCC_TOO_MANY_EA_WRREQS_STALL[1] | TCC_WRITE[1] | TCC_RW_REQ[2] | TCC_TOO_MANY_EA_WRREQS_STALL[2] | TCC_WRITE[2] | TCC_RW_REQ[3] | TCC_TOO_MANY_EA_WRREQS_STALL[3] | TCC_WRITE[3] | TCC_RW_REQ[4] | TCC_TOO_MANY_EA_WRREQS_STALL[4] | TCC_WRITE[4] | TCC_RW_REQ[5] | TCC_TOO_MANY_EA_WRREQS_STALL[5] | TCC_WRITE[5] | TCC_RW_REQ[6] | TCC_TOO_MANY_EA_WRREQS_STALL[6] | TCC_WRITE[6] | TCC_RW_REQ[7] | TCC_TOO_MANY_EA_WRREQS_STALL[7] | TCC_WRITE[7] | TCC_RW_REQ[8] | TCC_TOO_MANY_EA_WRREQS_STALL[8] | TCC_WRITE[8] | TCC_RW_REQ[9] | TCC_TOO_MANY_EA_WRREQS_STALL[9] | TCC_WRITE[9] | TCC_RW_REQ[10] | TCC_TOO_MANY_EA_WRREQS_STALL[10] | TCC_WRITE[10] | TCC_RW_REQ[11] | TCC_TOO_MANY_EA_WRREQS_STALL[11] | TCC_WRITE[11] | TCC_RW_REQ[12] | TCC_TOO_MANY_EA_WRREQS_STALL[12] | TCC_WRITE[12] | TCC_RW_REQ[13] | TCC_TOO_MANY_EA_WRREQS_STALL[13] | TCC_WRITE[13] | TCC_RW_REQ[14] | TCC_TOO_MANY_EA_WRREQS_STALL[14] | TCC_WRITE[14] | TCC_RW_REQ[15] | TCC_TOO_MANY_EA_WRREQS_STALL[15] | TCC_WRITE[15] | TCC_RW_REQ[16] | TCC_TOO_MANY_EA_WRREQS_STALL[16] | TCC_WRITE[16] | TCC_RW_REQ[17] | TCC_TOO_MANY_EA_WRREQS_STALL[17] | TCC_WRITE[17] | TCC_RW_REQ[18] | TCC_TOO_MANY_EA_WRREQS_STALL[18] | TCC_WRITE[18] | TCC_RW_REQ[19] | TCC_TOO_MANY_EA_WRREQS_STALL[19] | TCC_WRITE[19] | TCC_RW_REQ[20] | TCC_TOO_MANY_EA_WRREQS_STALL[20] | TCC_WRITE[20] | TCC_RW_REQ[21] | TCC_TOO_MANY_EA_WRREQS_STALL[21] | TCC_WRITE[21] | TCC_RW_REQ[22] | TCC_TOO_MANY_EA_WRREQS_STALL[22] | TCC_WRITE[22] | TCC_RW_REQ[23] | TCC_TOO_MANY_EA_WRREQS_STALL[23] | TCC_WRITE[23] | TCC_RW_REQ[24] | TCC_TOO_MANY_EA_WRREQS_STALL[24] | TCC_WRITE[24] | TCC_RW_REQ[25] | TCC_TOO_MANY_EA_WRREQS_STALL[25] | TCC_WRITE[25] | TCC_RW_REQ[26] | TCC_TOO_MANY_EA_WRREQS_STALL[26] | TCC_WRITE[26] | TCC_RW_REQ[27] | TCC_TOO_MANY_EA_WRREQS_STALL[27] | TCC_WRITE[27] | TCC_RW_REQ[28] | TCC_TOO_MANY_EA_WRREQS_STALL[28] | TCC_WRITE[28] | TCC_RW_REQ[29] | TCC_TOO_MANY_EA_WRREQS_STALL[29] | TCC_WRITE[29] | TCC_RW_REQ[30] | TCC_TOO_MANY_EA_WRREQS_STALL[30] | TCC_WRITE[30] | TCC_RW_REQ[31] | TCC_TOO_MANY_EA_WRREQS_STALL[31] | TCC_WRITE[31] | wave_size_6 | obj_6 | TCC_HIT[0] | TCC_MISS[0] | TCC_READ[0] | TCC_REQ[0] | TCC_HIT[1] | TCC_MISS[1] | TCC_READ[1] | TCC_REQ[1] | TCC_HIT[2] | TCC_MISS[2] | TCC_READ[2] | TCC_REQ[2] | TCC_HIT[3] | TCC_MISS[3] | TCC_READ[3] | TCC_REQ[3] | TCC_HIT[4] | TCC_MISS[4] | TCC_READ[4] | TCC_REQ[4] | TCC_HIT[5] | TCC_MISS[5] | TCC_READ[5] | TCC_REQ[5] | TCC_HIT[6] | TCC_MISS[6] | TCC_READ[6] | TCC_REQ[6] | TCC_HIT[7] | TCC_MISS[7] | TCC_READ[7] | TCC_REQ[7] | TCC_HIT[8] | TCC_MISS[8] | TCC_READ[8] | TCC_REQ[8] | TCC_HIT[9] | TCC_MISS[9] | TCC_READ[9] | TCC_REQ[9] | TCC_HIT[10] | TCC_MISS[10] | TCC_READ[10] | TCC_REQ[10] | TCC_HIT[11] | TCC_MISS[11] | TCC_READ[11] | TCC_REQ[11] | TCC_HIT[12] | TCC_MISS[12] | TCC_READ[12] | TCC_REQ[12] | TCC_HIT[13] | TCC_MISS[13] | TCC_READ[13] | TCC_REQ[13] | TCC_HIT[14] | TCC_MISS[14] | TCC_READ[14] | TCC_REQ[14] | TCC_HIT[15] | TCC_MISS[15] | TCC_READ[15] | TCC_REQ[15] | TCC_HIT[16] | TCC_MISS[16] | TCC_READ[16] | TCC_REQ[16] | TCC_HIT[17] | TCC_MISS[17] | TCC_READ[17] | TCC_REQ[17] | TCC_HIT[18] | TCC_MISS[18] | TCC_READ[18] | TCC_REQ[18] | TCC_HIT[19] | TCC_MISS[19] | TCC_READ[19] | TCC_REQ[19] | TCC_HIT[20] | TCC_MISS[20] | TCC_READ[20] | TCC_REQ[20] | TCC_HIT[21] | TCC_MISS[21] | TCC_READ[21] | TCC_REQ[21] | TCC_HIT[22] | TCC_MISS[22] | TCC_READ[22] | TCC_REQ[22] | TCC_HIT[23] | TCC_MISS[23] | TCC_READ[23] | TCC_REQ[23] | TCC_HIT[24] | TCC_MISS[24] | TCC_READ[24] | TCC_REQ[24] | TCC_HIT[25] | TCC_MISS[25] | TCC_READ[25] | TCC_REQ[25] | TCC_HIT[26] | TCC_MISS[26] | TCC_READ[26] | TCC_REQ[26] | TCC_HIT[27] | TCC_MISS[27] | TCC_READ[27] | TCC_REQ[27] | TCC_HIT[28] | TCC_MISS[28] | TCC_READ[28] | TCC_REQ[28] | TCC_HIT[29] | TCC_MISS[29] | TCC_READ[29] | TCC_REQ[29] | TCC_HIT[30] | TCC_MISS[30] | TCC_READ[30] | TCC_REQ[30] | TCC_HIT[31] | TCC_MISS[31] | TCC_READ[31] | TCC_REQ[31] | wave_size_7 | obj_7 | SQ_WAVES_LT_32 | SQ_WAVES_LT_16 | SQ_ITEMS | SQ_LDS_MEM_VIOLATIONS | SQ_LDS_ATOMIC_RETURN | SQ_LDS_IDX_ACTIVE | SQ_WAVES_RESTORED | SQ_WAVES_SAVED | TCP_TCC_NC_WRITE_REQ_sum | TCP_TCC_NC_ATOMIC_REQ_sum | TCP_TCC_UC_READ_REQ_sum | TCP_TCC_UC_WRITE_REQ_sum | TA_FLAT_WRITE_WAVEFRONTS_sum | TA_FLAT_ATOMIC_WAVEFRONTS_sum | SPI_RA_WVLIM_STALL_CSN | SPI_SWC_CSC_WR | TCC_NORMAL_EVICT_sum | TCC_ALL_TC_OP_INV_EVICT_sum | TCC_TOO_MANY_EA_WRREQS_STALL_sum | TCC_EA_ATOMIC_sum | wave_size_8 | obj_8 | TCC_EA_RDREQ[0] | TCC_EA_RDREQ_32B[0] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[0] | TCC_EA_RDREQ_GMI_CREDIT_STALL[0] | TCC_EA_RDREQ[1] | TCC_EA_RDREQ_32B[1] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[1] | TCC_EA_RDREQ_GMI_CREDIT_STALL[1] | TCC_EA_RDREQ[2] | TCC_EA_RDREQ_32B[2] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[2] | TCC_EA_RDREQ_GMI_CREDIT_STALL[2] | TCC_EA_RDREQ[3] | TCC_EA_RDREQ_32B[3] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[3] | TCC_EA_RDREQ_GMI_CREDIT_STALL[3] | TCC_EA_RDREQ[4] | TCC_EA_RDREQ_32B[4] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[4] | TCC_EA_RDREQ_GMI_CREDIT_STALL[4] | TCC_EA_RDREQ[5] | TCC_EA_RDREQ_32B[5] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[5] | TCC_EA_RDREQ_GMI_CREDIT_STALL[5] | TCC_EA_RDREQ[6] | TCC_EA_RDREQ_32B[6] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[6] | TCC_EA_RDREQ_GMI_CREDIT_STALL[6] | TCC_EA_RDREQ[7] | TCC_EA_RDREQ_32B[7] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[7] | TCC_EA_RDREQ_GMI_CREDIT_STALL[7] | TCC_EA_RDREQ[8] | TCC_EA_RDREQ_32B[8] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[8] | TCC_EA_RDREQ_GMI_CREDIT_STALL[8] | TCC_EA_RDREQ[9] | TCC_EA_RDREQ_32B[9] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[9] | TCC_EA_RDREQ_GMI_CREDIT_STALL[9] | TCC_EA_RDREQ[10] | TCC_EA_RDREQ_32B[10] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[10] | TCC_EA_RDREQ_GMI_CREDIT_STALL[10] | TCC_EA_RDREQ[11] | TCC_EA_RDREQ_32B[11] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[11] | TCC_EA_RDREQ_GMI_CREDIT_STALL[11] | TCC_EA_RDREQ[12] | TCC_EA_RDREQ_32B[12] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[12] | TCC_EA_RDREQ_GMI_CREDIT_STALL[12] | TCC_EA_RDREQ[13] | TCC_EA_RDREQ_32B[13] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[13] | TCC_EA_RDREQ_GMI_CREDIT_STALL[13] | TCC_EA_RDREQ[14] | TCC_EA_RDREQ_32B[14] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[14] | TCC_EA_RDREQ_GMI_CREDIT_STALL[14] | TCC_EA_RDREQ[15] | TCC_EA_RDREQ_32B[15] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[15] | TCC_EA_RDREQ_GMI_CREDIT_STALL[15] | TCC_EA_RDREQ[16] | TCC_EA_RDREQ_32B[16] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[16] | TCC_EA_RDREQ_GMI_CREDIT_STALL[16] | TCC_EA_RDREQ[17] | TCC_EA_RDREQ_32B[17] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[17] | TCC_EA_RDREQ_GMI_CREDIT_STALL[17] | TCC_EA_RDREQ[18] | TCC_EA_RDREQ_32B[18] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[18] | TCC_EA_RDREQ_GMI_CREDIT_STALL[18] | TCC_EA_RDREQ[19] | TCC_EA_RDREQ_32B[19] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[19] | TCC_EA_RDREQ_GMI_CREDIT_STALL[19] | TCC_EA_RDREQ[20] | TCC_EA_RDREQ_32B[20] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[20] | TCC_EA_RDREQ_GMI_CREDIT_STALL[20] | TCC_EA_RDREQ[21] | TCC_EA_RDREQ_32B[21] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[21] | TCC_EA_RDREQ_GMI_CREDIT_STALL[21] | TCC_EA_RDREQ[22] | TCC_EA_RDREQ_32B[22] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[22] | TCC_EA_RDREQ_GMI_CREDIT_STALL[22] | TCC_EA_RDREQ[23] | TCC_EA_RDREQ_32B[23] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[23] | TCC_EA_RDREQ_GMI_CREDIT_STALL[23] | TCC_EA_RDREQ[24] | TCC_EA_RDREQ_32B[24] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[24] | TCC_EA_RDREQ_GMI_CREDIT_STALL[24] | TCC_EA_RDREQ[25] | TCC_EA_RDREQ_32B[25] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[25] | TCC_EA_RDREQ_GMI_CREDIT_STALL[25] | TCC_EA_RDREQ[26] | TCC_EA_RDREQ_32B[26] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[26] | TCC_EA_RDREQ_GMI_CREDIT_STALL[26] | TCC_EA_RDREQ[27] | TCC_EA_RDREQ_32B[27] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[27] | TCC_EA_RDREQ_GMI_CREDIT_STALL[27] | TCC_EA_RDREQ[28] | TCC_EA_RDREQ_32B[28] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[28] | TCC_EA_RDREQ_GMI_CREDIT_STALL[28] | TCC_EA_RDREQ[29] | TCC_EA_RDREQ_32B[29] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[29] | TCC_EA_RDREQ_GMI_CREDIT_STALL[29] | TCC_EA_RDREQ[30] | TCC_EA_RDREQ_32B[30] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[30] | TCC_EA_RDREQ_GMI_CREDIT_STALL[30] | TCC_EA_RDREQ[31] | TCC_EA_RDREQ_32B[31] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[31] | TCC_EA_RDREQ_GMI_CREDIT_STALL[31] | wave_size_9 | obj_9 | SQ_INSTS_VALU_INT64 | SQ_INSTS_SMEM | SQ_INSTS_FLAT | SQ_INSTS_LDS | SQ_INSTS_GDS | SQ_INSTS_EXP_GDS | SQ_INSTS_BRANCH | SQ_INSTS_SENDMSG | TCP_TOTAL_ATOMIC_WITH_RET_sum | TCP_TOTAL_ATOMIC_WITHOUT_RET_sum | TCP_TOTAL_WRITEBACK_INVALIDATES_sum | TCP_TOTAL_CACHE_ACCESSES_sum | TA_BUFFER_COALESCED_READ_CYCLES_sum | TA_BUFFER_COALESCED_WRITE_CYCLES_sum | TD_COALESCABLE_WAVEFRONT_sum | SPI_RA_RES_STALL_CSN | SPI_RA_TMP_STALL_CSN | CPC_CPC_UTCL2IU_BUSY | CPC_CPC_UTCL2IU_IDLE | CPF_CMP_UTCL1_STALL_ON_TRANSLATION | TCC_READ_sum | TCC_WRITE_sum | TCC_ATOMIC_sum | TCC_WRITEBACK_sum | wave_size_10 | obj_10 | SQC_TC_DATA_WRITE_REQ | SQC_TC_DATA_ATOMIC_REQ | SQC_TC_STALL | SQC_TC_REQ | SQC_DCACHE_REQ_READ_16 | SQC_ICACHE_REQ | SQC_ICACHE_HITS | SQC_ICACHE_MISSES | wave_size_11 | obj_11 | SQ_THREAD_CYCLES_VALU | SQ_IFETCH | SQ_LDS_BANK_CONFLICT | SQ_LDS_ADDR_CONFLICT | SQ_LDS_UNALIGNED_STALL | SQ_WAVES_EQ_64 | SQ_WAVES_LT_64 | SQ_WAVES_LT_48 | TCP_TCC_WRITE_REQ_sum | TCP_TCC_ATOMIC_WITH_RET_REQ_sum | TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum | TCP_TCC_NC_READ_REQ_sum | TA_FLAT_WAVEFRONTS_sum | TA_FLAT_READ_WAVEFRONTS_sum | SPI_RA_BAR_CU_FULL_CSN | SPI_RA_TGLIM_CU_FULL_CSN | TCC_EA_RDREQ_DRAM_sum | TCC_TAG_STALL_sum | TCC_NORMAL_WRITEBACK_sum | TCC_ALL_TC_OP_WB_WRITEBACK_sum | wave_size_12 | obj_12 | TCC_EA_WRREQ_DRAM_CREDIT_STALL[0] | TCC_EA_WRREQ_GMI_CREDIT_STALL[0] | TCC_EA_WRREQ_IO_CREDIT_STALL[0] | TCC_EA_WRREQ_LEVEL[0] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[1] | TCC_EA_WRREQ_GMI_CREDIT_STALL[1] | TCC_EA_WRREQ_IO_CREDIT_STALL[1] | TCC_EA_WRREQ_LEVEL[1] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[2] | TCC_EA_WRREQ_GMI_CREDIT_STALL[2] | TCC_EA_WRREQ_IO_CREDIT_STALL[2] | TCC_EA_WRREQ_LEVEL[2] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[3] | TCC_EA_WRREQ_GMI_CREDIT_STALL[3] | TCC_EA_WRREQ_IO_CREDIT_STALL[3] | TCC_EA_WRREQ_LEVEL[3] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[4] | TCC_EA_WRREQ_GMI_CREDIT_STALL[4] | TCC_EA_WRREQ_IO_CREDIT_STALL[4] | TCC_EA_WRREQ_LEVEL[4] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[5] | TCC_EA_WRREQ_GMI_CREDIT_STALL[5] | TCC_EA_WRREQ_IO_CREDIT_STALL[5] | TCC_EA_WRREQ_LEVEL[5] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[6] | TCC_EA_WRREQ_GMI_CREDIT_STALL[6] | TCC_EA_WRREQ_IO_CREDIT_STALL[6] | TCC_EA_WRREQ_LEVEL[6] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[7] | TCC_EA_WRREQ_GMI_CREDIT_STALL[7] | TCC_EA_WRREQ_IO_CREDIT_STALL[7] | TCC_EA_WRREQ_LEVEL[7] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[8] | TCC_EA_WRREQ_GMI_CREDIT_STALL[8] | TCC_EA_WRREQ_IO_CREDIT_STALL[8] | TCC_EA_WRREQ_LEVEL[8] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[9] | TCC_EA_WRREQ_GMI_CREDIT_STALL[9] | TCC_EA_WRREQ_IO_CREDIT_STALL[9] | TCC_EA_WRREQ_LEVEL[9] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[10] | TCC_EA_WRREQ_GMI_CREDIT_STALL[10] | TCC_EA_WRREQ_IO_CREDIT_STALL[10] | TCC_EA_WRREQ_LEVEL[10] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[11] | TCC_EA_WRREQ_GMI_CREDIT_STALL[11] | TCC_EA_WRREQ_IO_CREDIT_STALL[11] | TCC_EA_WRREQ_LEVEL[11] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[12] | TCC_EA_WRREQ_GMI_CREDIT_STALL[12] | TCC_EA_WRREQ_IO_CREDIT_STALL[12] | TCC_EA_WRREQ_LEVEL[12] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[13] | TCC_EA_WRREQ_GMI_CREDIT_STALL[13] | TCC_EA_WRREQ_IO_CREDIT_STALL[13] | TCC_EA_WRREQ_LEVEL[13] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[14] | TCC_EA_WRREQ_GMI_CREDIT_STALL[14] | TCC_EA_WRREQ_IO_CREDIT_STALL[14] | TCC_EA_WRREQ_LEVEL[14] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[15] | TCC_EA_WRREQ_GMI_CREDIT_STALL[15] | TCC_EA_WRREQ_IO_CREDIT_STALL[15] | TCC_EA_WRREQ_LEVEL[15] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[16] | TCC_EA_WRREQ_GMI_CREDIT_STALL[16] | TCC_EA_WRREQ_IO_CREDIT_STALL[16] | TCC_EA_WRREQ_LEVEL[16] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[17] | TCC_EA_WRREQ_GMI_CREDIT_STALL[17] | TCC_EA_WRREQ_IO_CREDIT_STALL[17] | TCC_EA_WRREQ_LEVEL[17] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[18] | TCC_EA_WRREQ_GMI_CREDIT_STALL[18] | TCC_EA_WRREQ_IO_CREDIT_STALL[18] | TCC_EA_WRREQ_LEVEL[18] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[19] | TCC_EA_WRREQ_GMI_CREDIT_STALL[19] | TCC_EA_WRREQ_IO_CREDIT_STALL[19] | TCC_EA_WRREQ_LEVEL[19] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[20] | TCC_EA_WRREQ_GMI_CREDIT_STALL[20] | TCC_EA_WRREQ_IO_CREDIT_STALL[20] | TCC_EA_WRREQ_LEVEL[20] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[21] | TCC_EA_WRREQ_GMI_CREDIT_STALL[21] | TCC_EA_WRREQ_IO_CREDIT_STALL[21] | TCC_EA_WRREQ_LEVEL[21] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[22] | TCC_EA_WRREQ_GMI_CREDIT_STALL[22] | TCC_EA_WRREQ_IO_CREDIT_STALL[22] | TCC_EA_WRREQ_LEVEL[22] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[23] | TCC_EA_WRREQ_GMI_CREDIT_STALL[23] | TCC_EA_WRREQ_IO_CREDIT_STALL[23] | TCC_EA_WRREQ_LEVEL[23] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[24] | TCC_EA_WRREQ_GMI_CREDIT_STALL[24] | TCC_EA_WRREQ_IO_CREDIT_STALL[24] | TCC_EA_WRREQ_LEVEL[24] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[25] | TCC_EA_WRREQ_GMI_CREDIT_STALL[25] | TCC_EA_WRREQ_IO_CREDIT_STALL[25] | TCC_EA_WRREQ_LEVEL[25] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[26] | TCC_EA_WRREQ_GMI_CREDIT_STALL[26] | TCC_EA_WRREQ_IO_CREDIT_STALL[26] | TCC_EA_WRREQ_LEVEL[26] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[27] | TCC_EA_WRREQ_GMI_CREDIT_STALL[27] | TCC_EA_WRREQ_IO_CREDIT_STALL[27] | TCC_EA_WRREQ_LEVEL[27] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[28] | TCC_EA_WRREQ_GMI_CREDIT_STALL[28] | TCC_EA_WRREQ_IO_CREDIT_STALL[28] | TCC_EA_WRREQ_LEVEL[28] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[29] | TCC_EA_WRREQ_GMI_CREDIT_STALL[29] | TCC_EA_WRREQ_IO_CREDIT_STALL[29] | TCC_EA_WRREQ_LEVEL[29] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[30] | TCC_EA_WRREQ_GMI_CREDIT_STALL[30] | TCC_EA_WRREQ_IO_CREDIT_STALL[30] | TCC_EA_WRREQ_LEVEL[30] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[31] | TCC_EA_WRREQ_GMI_CREDIT_STALL[31] | TCC_EA_WRREQ_IO_CREDIT_STALL[31] | TCC_EA_WRREQ_LEVEL[31] | wave_size_13 | obj_13 | TCC_ATOMIC[0] | TCC_CYCLE[0] | TCC_EA_ATOMIC[0] | TCC_EA_ATOMIC_LEVEL[0] | TCC_ATOMIC[1] | TCC_CYCLE[1] | TCC_EA_ATOMIC[1] | TCC_EA_ATOMIC_LEVEL[1] | TCC_ATOMIC[2] | TCC_CYCLE[2] | TCC_EA_ATOMIC[2] | TCC_EA_ATOMIC_LEVEL[2] | TCC_ATOMIC[3] | TCC_CYCLE[3] | TCC_EA_ATOMIC[3] | TCC_EA_ATOMIC_LEVEL[3] | TCC_ATOMIC[4] | TCC_CYCLE[4] | TCC_EA_ATOMIC[4] | TCC_EA_ATOMIC_LEVEL[4] | TCC_ATOMIC[5] | TCC_CYCLE[5] | TCC_EA_ATOMIC[5] | TCC_EA_ATOMIC_LEVEL[5] | TCC_ATOMIC[6] | TCC_CYCLE[6] | TCC_EA_ATOMIC[6] | TCC_EA_ATOMIC_LEVEL[6] | TCC_ATOMIC[7] | TCC_CYCLE[7] | TCC_EA_ATOMIC[7] | TCC_EA_ATOMIC_LEVEL[7] | TCC_ATOMIC[8] | TCC_CYCLE[8] | TCC_EA_ATOMIC[8] | TCC_EA_ATOMIC_LEVEL[8] | TCC_ATOMIC[9] | TCC_CYCLE[9] | TCC_EA_ATOMIC[9] | TCC_EA_ATOMIC_LEVEL[9] | TCC_ATOMIC[10] | TCC_CYCLE[10] | TCC_EA_ATOMIC[10] | TCC_EA_ATOMIC_LEVEL[10] | TCC_ATOMIC[11] | TCC_CYCLE[11] | TCC_EA_ATOMIC[11] | TCC_EA_ATOMIC_LEVEL[11] | TCC_ATOMIC[12] | TCC_CYCLE[12] | TCC_EA_ATOMIC[12] | TCC_EA_ATOMIC_LEVEL[12] | TCC_ATOMIC[13] | TCC_CYCLE[13] | TCC_EA_ATOMIC[13] | TCC_EA_ATOMIC_LEVEL[13] | TCC_ATOMIC[14] | TCC_CYCLE[14] | TCC_EA_ATOMIC[14] | TCC_EA_ATOMIC_LEVEL[14] | TCC_ATOMIC[15] | TCC_CYCLE[15] | TCC_EA_ATOMIC[15] | TCC_EA_ATOMIC_LEVEL[15] | TCC_ATOMIC[16] | TCC_CYCLE[16] | TCC_EA_ATOMIC[16] | TCC_EA_ATOMIC_LEVEL[16] | TCC_ATOMIC[17] | TCC_CYCLE[17] | TCC_EA_ATOMIC[17] | TCC_EA_ATOMIC_LEVEL[17] | TCC_ATOMIC[18] | TCC_CYCLE[18] | TCC_EA_ATOMIC[18] | TCC_EA_ATOMIC_LEVEL[18] | TCC_ATOMIC[19] | TCC_CYCLE[19] | TCC_EA_ATOMIC[19] | TCC_EA_ATOMIC_LEVEL[19] | TCC_ATOMIC[20] | TCC_CYCLE[20] | TCC_EA_ATOMIC[20] | TCC_EA_ATOMIC_LEVEL[20] | TCC_ATOMIC[21] | TCC_CYCLE[21] | TCC_EA_ATOMIC[21] | TCC_EA_ATOMIC_LEVEL[21] | TCC_ATOMIC[22] | TCC_CYCLE[22] | TCC_EA_ATOMIC[22] | TCC_EA_ATOMIC_LEVEL[22] | TCC_ATOMIC[23] | TCC_CYCLE[23] | TCC_EA_ATOMIC[23] | TCC_EA_ATOMIC_LEVEL[23] | TCC_ATOMIC[24] | TCC_CYCLE[24] | TCC_EA_ATOMIC[24] | TCC_EA_ATOMIC_LEVEL[24] | TCC_ATOMIC[25] | TCC_CYCLE[25] | TCC_EA_ATOMIC[25] | TCC_EA_ATOMIC_LEVEL[25] | TCC_ATOMIC[26] | TCC_CYCLE[26] | TCC_EA_ATOMIC[26] | TCC_EA_ATOMIC_LEVEL[26] | TCC_ATOMIC[27] | TCC_CYCLE[27] | TCC_EA_ATOMIC[27] | TCC_EA_ATOMIC_LEVEL[27] | TCC_ATOMIC[28] | TCC_CYCLE[28] | TCC_EA_ATOMIC[28] | TCC_EA_ATOMIC_LEVEL[28] | TCC_ATOMIC[29] | TCC_CYCLE[29] | TCC_EA_ATOMIC[29] | TCC_EA_ATOMIC_LEVEL[29] | TCC_ATOMIC[30] | TCC_CYCLE[30] | TCC_EA_ATOMIC[30] | TCC_EA_ATOMIC_LEVEL[30] | TCC_ATOMIC[31] | TCC_CYCLE[31] | TCC_EA_ATOMIC[31] | TCC_EA_ATOMIC_LEVEL[31] | wave_size_14 | obj_14 | SQ_INSTS_FLAT_LDS_ONLY | SQ_INSTS_VALU_MFMA_MOPS_I8 | SQ_INSTS_VALU_MFMA_MOPS_F16 | SQ_INSTS_VALU_MFMA_MOPS_BF16 | SQ_INSTS_VALU_MFMA_MOPS_F32 | SQ_INSTS_VALU_MFMA_MOPS_F64 | SQC_TC_INST_REQ | SQC_TC_DATA_READ_REQ | TCP_TCC_RW_READ_REQ_sum | TCP_TCC_RW_WRITE_REQ_sum | TCP_TCC_RW_ATOMIC_REQ_sum | TCP_PENDING_STALL_CYCLES_sum | wave_size_15 | obj_15 | SQ_ACTIVE_INST_SCA | SQ_ACTIVE_INST_EXP_GDS | SQ_ACTIVE_INST_MISC | SQ_ACTIVE_INST_FLAT | SQ_INST_CYCLES_VMEM_WR | SQ_INST_CYCLES_VMEM_RD | SQ_INST_CYCLES_SMEM | SQ_INST_CYCLES_SALU | TCP_TCP_LATENCY_sum | TCP_TCC_READ_REQ_LATENCY_sum | TCP_TCC_WRITE_REQ_LATENCY_sum | TCP_TCC_READ_REQ_sum | TA_ADDR_STALLED_BY_TD_CYCLES_sum | TA_DATA_STALLED_BY_TC_CYCLES_sum | SPI_RA_SGPR_SIMD_FULL_CSN | SPI_RA_LDS_CU_FULL_CSN | CPC_ME1_DC0_SPI_BUSY | TCC_EA_WRREQ_STALL_sum | TCC_EA_RDREQ_sum | TCC_EA_RDREQ_32B_sum | TCC_EA_RD_UNCACHED_32B_sum | wave_size_16 | obj_16 | SQC_DCACHE_REQ_READ_1 | SQC_DCACHE_REQ_READ_2 | SQC_DCACHE_REQ_READ_4 | wave_size_17 | obj_17 | SQ_INSTS_SMEM_NORM | SQ_INSTS_MFMA | SQ_INSTS_VALU_MFMA_I8 | SQ_INSTS_VALU_MFMA_F16 | SQ_INSTS_VALU_MFMA_BF16 | SQ_INSTS_VALU_MFMA_F32 | SQ_INSTS_VALU_MFMA_F64 | SQ_VALU_MFMA_BUSY_CYCLES | TCP_TCC_UC_ATOMIC_REQ_sum | TCP_TCC_CC_READ_REQ_sum | TCP_TCC_CC_WRITE_REQ_sum | TCP_TCC_CC_ATOMIC_REQ_sum | SPI_VWC_CSC_WR | SPI_RA_BULKY_CU_FULL_CSN | TCC_EA_RDREQ_LEVEL_sum | TCC_EA_WRREQ_LEVEL_sum | TCC_EA_ATOMIC_LEVEL_sum | wave_size_18 | obj_18 | SQC_ICACHE_MISSES_DUPLICATE | SQC_DCACHE_INPUT_VALID_READYB | SQC_DCACHE_ATOMIC | SQC_DCACHE_REQ_READ_8 | SQC_DCACHE_REQ | SQC_DCACHE_HITS | SQC_DCACHE_MISSES | SQC_DCACHE_MISSES_DUPLICATE | Start_Timestamp | End_Timestamp |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2 | 0 | vecCopy(double*, double*, double*, int, int) [clone .kd] | 2 | 1048576 | 256 | 0 | 0 | 8 | 0 | 16 | 64 | 0x7faf0bc30ec0 | 230680 | 131907 | 16384 | 0 | 16384 | 16384 | 32768 | 49152 | 28834 | 28834 | 1992463.0 | 1416205.0 | 3424.0 | 151322.0 | 1123559.0 | 0.0 | 1408683.0 | 1111503.0 | 228969 | 140030 | 28834 | 0 | 28834 | 0 | 922688.0 | 493585.0 | 0.0 | 0.0 | 64 | 0x7f3fa0d08ec0 | 10920182 | 9928588 | 647530 | 344064 | 1635530 | 0 | 0 | 163840 | 832.0 | 515136.0 | 0.0 | 524288.0 | 263908.0 | 32768.0 | 484575 | 0 | 0 | 10847 | 131072.0 | 131072.0 | 0.0 | 131072.0 | 64 | 0x7fee1fd78ec0 | 0 | 1294043 | 4096 | 4096 | 0 | 1179623 | 4096 | 4096 | 0 | 1343759 | 4096 | 4096 | 0 | 1307993 | 4096 | 4096 | 0 | 1140025 | 4096 | 4096 | 0 | 1612067 | 4096 | 4096 | 0 | 1186362 | 4096 | 4096 | 0 | 1315869 | 4096 | 4096 | 0 | 1131318 | 4096 | 4096 | 0 | 1133330 | 4096 | 4096 | 0 | 1108961 | 4096 | 4096 | 0 | 1305492 | 4096 | 4096 | 0 | 1187943 | 4096 | 4096 | 0 | 1145887 | 4096 | 4096 | 0 | 1313106 | 4096 | 4096 | 0 | 1324761 | 4096 | 4096 | 0 | 1198429 | 4096 | 4096 | 0 | 1207007 | 4096 | 4096 | 0 | 1131412 | 4096 | 4096 | 0 | 1383544 | 4096 | 4096 | 0 | 1029790 | 4096 | 4096 | 0 | 1819610 | 4096 | 4096 | 0 | 1462597 | 4096 | 4096 | 0 | 1176151 | 4096 | 4096 | 0 | 1129491 | 4096 | 4096 | 0 | 1106642 | 4096 | 4096 | 0 | 1224066 | 4096 | 4096 | 0 | 1140871 | 4096 | 4096 | 0 | 1248507 | 4096 | 4096 | 0 | 1062605 | 4096 | 4096 | 0 | 1166831 | 4096 | 4096 | 0 | 1345424 | 4096 | 4096 | 64 | 0x7fcdf8740ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 114688 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 12268 | 18688 | 7820 | 545 | 0 | 26156 | 204286.0 | 0.0 | 73206.0 | 131080.0 | 64 | 0x7fe6bad74ec0 | 0 | 393216 | 163840 | 0 | 0 | 0 | 0 | 0 | 18307 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 381.0 | 32768.0 | 4096 | 16384 | 352 | 28734 | 1982 | 0 | 56.0 | 7.0 | 0.0 | 204399.0 | 64 | 0x7f0732708ec0 | 6336 | 0 | 4096 | 6376 | 0 | 4096 | 6376 | 0 | 4096 | 6449 | 0 | 4096 | 6360 | 0 | 4096 | 6390 | 0 | 4096 | 6364 | 0 | 4096 | 6395 | 0 | 4096 | 6398 | 0 | 4096 | 6340 | 0 | 4096 | 6376 | 0 | 4096 | 6376 | 0 | 4096 | 6453 | 0 | 4096 | 6364 | 0 | 4096 | 6394 | 0 | 4096 | 6364 | 0 | 4096 | 6339 | 0 | 4096 | 6390 | 0 | 4096 | 6376 | 0 | 4096 | 6349 | 0 | 4096 | 6422 | 0 | 4096 | 6412 | 0 | 4096 | 6374 | 0 | 4096 | 6582 | 0 | 4096 | 6415 | 0 | 4096 | 6340 | 0 | 4096 | 6393 | 0 | 4096 | 6378 | 0 | 4096 | 6347 | 0 | 4096 | 6425 | 0 | 4096 | 6415 | 0 | 4096 | 6375 | 0 | 4096 | 64 | 0x7f779dc18ec0 | 2218 | 4099 | 2221 | 6317 | 2301 | 4096 | 2301 | 6397 | 2289 | 4096 | 2289 | 6385 | 2323 | 4096 | 2323 | 6419 | 2287 | 4096 | 2287 | 6383 | 2291 | 4096 | 2291 | 6387 | 2247 | 4096 | 2247 | 6343 | 2297 | 4096 | 2297 | 6393 | 2295 | 4096 | 2295 | 6391 | 2220 | 4096 | 2220 | 6316 | 2307 | 4096 | 2307 | 6403 | 2290 | 4096 | 2290 | 6386 | 2325 | 4096 | 2325 | 6421 | 2291 | 4096 | 2291 | 6387 | 2290 | 4096 | 2290 | 6386 | 2251 | 4096 | 2251 | 6347 | 2274 | 4096 | 2274 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0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4099 | 0 | 0 | 0 | 4096 | 0 | 77 | 0 | 4100 | 0 | 0 | 0 | 4096 | 0 | 82 | 0 | 4096 | 0 | 215 | 0 | 4096 | 0 | 26 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 64 | 0x7f0da5fd0ec0 | 0 | 65536 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 0.0 | 0.0 | 0.0 | 524288.0 | 0.0 | 0.0 | 0.0 | 10375 | 0 | 814 | 26950 | 0 | 73182.0 | 131072.0 | 0.0 | 65568.0 | 64 | 0x7fafe65c4ec0 | 0 | 0 | 0 | 224 | 0 | 65536 | 64215 | 56 | 64 | 0x7fb469ab8ec0 | 10485760 | 65536 | 0 | 0 | 0 | 16384 | 0 | 0 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131080.0 | 34503.0 | 46188.0 | 19348.0 | 64 | 0x7f01a6500ec0 | 0 | 0 | 0 | 1092005 | 0 | 0 | 0 | 1089074 | 0 | 0 | 0 | 1035974 | 0 | 0 | 0 | 1162858 | 21 | 0 | 0 | 1221153 | 97 | 0 | 0 | 1207141 | 0 | 0 | 0 | 1054401 | 0 | 0 | 0 | 1132993 | 0 | 0 | 0 | 1000441 | 0 | 0 | 0 | 1083011 | 0 | 0 | 0 | 1022785 | 0 | 0 | 0 | 1026577 | 0 | 0 | 0 | 958099 | 0 | 0 | 0 | 1079211 | 191 | 0 | 0 | 1244224 | 9 | 0 | 0 | 1233237 | 0 | 0 | 0 | 1043911 | 0 | 0 | 0 | 1074089 | 4 | 0 | 0 | 1073967 | 264 | 0 | 0 | 1390233 | 0 | 0 | 0 | 993520 | 0 | 0 | 0 | 1068643 | 0 | 0 | 0 | 1059660 | 0 | 0 | 0 | 1134638 | 0 | 0 | 0 | 1168395 | 0 | 0 | 0 | 988146 | 0 | 0 | 0 | 1043386 | 0 | 0 | 0 | 1223013 | 0 | 0 | 0 | 1170092 | 0 | 0 | 0 | 995145 | 0 | 0 | 0 | 1070150 | 0 | 0 | 0 | 1165258 | 64 | 0x7f14d1ef4ec0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 | 0 | 27878 | 0 | 0 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| 3 | 1 | vecCopy(double*, double*, double*, int, int) [clone .kd] | 2 | 1048576 | 256 | 0 | 0 | 8 | 0 | 16 | 64 | 0x7faf0bc30ec0 | 303864 | 210822 | 16384 | 0 | 16384 | 16384 | 32768 | 49152 | 37982 | 37982 | 3017252.0 | 2430599.0 | 5004.0 | 392631.0 | 1603801.0 | 0.0 | 2418147.0 | 2109628.0 | 303856 | 219933 | 37982 | 0 | 37982 | 0 | 1215424.0 | 782486.0 | 0.0 | 0.0 | 64 | 0x7f3fa0d08ec0 | 17457179 | 16858737 | 254378 | 344064 | 2526932 | 0 | 0 | 163840 | 0.0 | 524288.0 | 0.0 | 524288.0 | 534338.0 | 32768.0 | 737631 | 0 | 0 | 11538 | 90762.0 | 90762.0 | 0.0 | 90762.0 | 64 | 0x7fee1fd78ec0 | 0 | 3118224 | 2832 | 2832 | 0 | 3261055 | 2876 | 2876 | 0 | 3655187 | 2876 | 2876 | 0 | 3725380 | 2876 | 2876 | 0 | 3655126 | 2890 | 2890 | 0 | 4218172 | 2852 | 2852 | 0 | 3800127 | 2892 | 2892 | 0 | 3247809 | 2828 | 2828 | 0 | 3713563 | 2828 | 2828 | 0 | 2704879 | 2832 | 2832 | 0 | 3180484 | 2876 | 2876 | 0 | 3445378 | 2876 | 2876 | 0 | 3438040 | 2872 | 2872 | 0 | 3949512 | 2884 | 2884 | 0 | 3914862 | 2848 | 2848 | 0 | 3064322 | 2892 | 2892 | 0 | 3261739 | 2824 | 2824 | 0 | 4429124 | 2874 | 2874 | 0 | 3383179 | 2844 | 2844 | 0 | 3517378 | 2844 | 2844 | 0 | 3357375 | 2828 | 2828 | 0 | 3737385 | 2900 | 2900 | 0 | 4115302 | 2846 | 2846 | 0 | 3843878 | 2824 | 2824 | 0 | 3894509 | 2824 | 2824 | 0 | 3078837 | 2824 | 2824 | 0 | 3642306 | 2876 | 2876 | 0 | 3805127 | 2844 | 2844 | 0 | 3120755 | 2844 | 2844 | 0 | 3299928 | 2828 | 2828 | 0 | 3075429 | 2900 | 2900 | 0 | 3865800 | 2848 | 2848 | 64 | 0x7fcdf8740ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 114688 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 31503 | 27653 | 9598 | 2884 | 0 | 39454 | 200900.0 | 0.0 | 69815.0 | 131085.0 | 64 | 0x7fe6bad74ec0 | 0 | 393216 | 163840 | 0 | 0 | 0 | 0 | 0 | 29913 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 241.0 | 32768.0 | 4096 | 16384 | 302 | 41069 | 2026 | 0 | 56.0 | 10.0 | 0.0 | 201195.0 | 64 | 0x7f0732708ec0 | 6275 | 0 | 4096 | 6266 | 0 | 4096 | 6246 | 0 | 4096 | 6263 | 0 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2169 | 6265 | 2203 | 4096 | 2203 | 6299 | 2235 | 4098 | 2237 | 6333 | 2212 | 4096 | 2212 | 6308 | 2189 | 4096 | 2189 | 6285 | 2193 | 4096 | 2193 | 6289 | 2134 | 4096 | 2134 | 6230 | 2178 | 4096 | 2178 | 6274 | 2182 | 4096 | 2182 | 6278 | 2166 | 4096 | 2166 | 6262 | 2200 | 4096 | 2200 | 6296 | 2244 | 4097 | 2245 | 6341 | 2209 | 4096 | 2209 | 6305 | 2187 | 4096 | 2187 | 6283 | 2194 | 4096 | 2194 | 6290 | 2198 | 4097 | 2199 | 6295 | 64 | 0x7f2de1778ec0 | 0 | 0 | 1048576 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 32768 | 65550.0 | 0.0 | 0.0 | 0.0 | 64 | 0x7f6e6cc84ec0 | 4096 | 0 | 298 | 0 | 4096 | 0 | 57 | 0 | 4098 | 0 | 121 | 0 | 4096 | 0 | 871 | 0 | 4097 | 0 | 927 | 0 | 4096 | 0 | 538 | 0 | 4096 | 0 | 1030 | 0 | 4096 | 0 | 1340 | 0 | 4096 | 0 | 557 | 0 | 4096 | 0 | 313 | 0 | 4096 | 0 | 554 | 0 | 4096 | 0 | 611 | 0 | 4097 | 0 | 292 | 0 | 4096 | 0 | 2357 | 0 | 4096 | 0 | 1070 | 0 | 4097 | 0 | 1090 | 0 | 4096 | 0 | 898 | 0 | 4097 | 0 | 1084 | 0 | 4097 | 0 | 752 | 0 | 4096 | 0 | 447 | 0 | 4096 | 0 | 1710 | 0 | 4096 | 0 | 610 | 0 | 4096 | 0 | 625 | 0 | 4096 | 0 | 1619 | 0 | 4096 | 0 | 1520 | 0 | 4100 | 0 | 125 | 0 | 4096 | 0 | 426 | 0 | 4096 | 0 | 683 | 0 | 4097 | 0 | 1464 | 0 | 4096 | 0 | 530 | 0 | 4096 | 0 | 1195 | 0 | 4096 | 0 | 738 | 0 | 64 | 0x7f0da5fd0ec0 | 0 | 65536 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 0.0 | 0.0 | 0.0 | 524288.0 | 0.0 | 0.0 | 0.0 | 21337 | 0 | 2714 | 38454 | 0 | 69733.0 | 131072.0 | 0.0 | 45609.0 | 64 | 0x7fafe65c4ec0 | 0 | 0 | 0 | 56 | 0 | 65536 | 65536 | 0 | 64 | 0x7fb469ab8ec0 | 10485760 | 65536 | 0 | 0 | 0 | 16384 | 0 | 0 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131082.0 | 105091.0 | 45612.0 | 0.0 | 64 | 0x7f01a6500ec0 | 0 | 0 | 0 | 1547715 | 0 | 0 | 0 | 1895436 | 0 | 0 | 0 | 1639521 | 0 | 0 | 0 | 1912827 | 64 | 0 | 0 | 1748731 | 1139 | 0 | 0 | 2134241 | 0 | 0 | 0 | 1581029 | 266 | 0 | 0 | 2089147 | 0 | 0 | 0 | 1839559 | 0 | 0 | 0 | 1511723 | 0 | 0 | 0 | 1853730 | 0 | 0 | 0 | 1998002 | 0 | 0 | 0 | 1471157 | 26 | 0 | 0 | 1845058 | 0 | 0 | 0 | 2011350 | 0 | 0 | 0 | 1667585 | 0 | 0 | 0 | 1849370 | 0 | 0 | 0 | 1901748 | 81 | 0 | 0 | 1879494 | 171 | 0 | 0 | 2133104 | 0 | 0 | 0 | 1516145 | 280 | 0 | 0 | 1881994 | 32 | 0 | 0 | 1987480 | 0 | 0 | 0 | 2122447 | 0 | 0 | 0 | 1580493 | 0 | 0 | 0 | 1972374 | 0 | 0 | 0 | 1673834 | 0 | 0 | 0 | 1760131 | 0 | 0 | 0 | 1667013 | 0 | 0 | 0 | 1445299 | 26 | 0 | 0 | 1763949 | 138 | 0 | 0 | 2052419 | 64 | 0x7f14d1ef4ec0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 0 | 41274 | 0 | 0 | 64 | 0x7fa9abb20ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 56 | 131072.0 | 131072.0 | 0.0 | 2003653.0 | 64 | 0x7f45db7a0ec0 | 114688 | 0 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 57785445.0 | 195794080.0 | 46777541.0 | 131072.0 | 0.0 | 506614.0 | 0 | 0 | 23278 | 3912.0 | 131073.0 | 0.0 | 0.0 | 64 | 0x7f4ab1148ec0 | 32768 | 32768 | 0 | 64 | 0x7f919f270ec0 | 131072 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 118741265.0 | 58141396.0 | 0.0 | 64 | 0x7f2c30ad0ec0 | 0 | 204845 | 0 | 0 | 65536 | 63800 | 56 | 1680 | 199855576464819 | 199855576481459 |
| 4 | 2 | vecCopy(double*, double*, double*, int, int) [clone .kd] | 2 | 1048576 | 256 | 0 | 0 | 8 | 0 | 16 | 64 | 0x7faf0bc30ec0 | 328312 | 221517 | 16384 | 0 | 16384 | 16384 | 32768 | 49152 | 41038 | 41038 | 3156901.0 | 2474907.0 | 4814.0 | 365446.0 | 1623645.0 | 0.0 | 2461722.0 | 2154515.0 | 328304 | 231043 | 41038 | 0 | 41038 | 0 | 1313216.0 | 767227.0 | 0.0 | 0.0 | 64 | 0x7f3fa0d08ec0 | 19141904 | 18041249 | 756591 | 344064 | 2767961 | 0 | 0 | 163840 | 832.0 | 515146.0 | 0.0 | 524288.0 | 579320.0 | 32768.0 | 961827 | 0 | 0 | 13250 | 91256.0 | 91256.0 | 0.0 | 91256.0 | 64 | 0x7fee1fd78ec0 | 0 | 3317020 | 2824 | 2824 | 0 | 3917642 | 2872 | 2872 | 0 | 3669871 | 2860 | 2860 | 0 | 4815879 | 2868 | 2868 | 0 | 3724570 | 2870 | 2870 | 0 | 4117769 | 2848 | 2848 | 0 | 3483454 | 2868 | 2868 | 0 | 4210386 | 2828 | 2828 | 0 | 3168618 | 2828 | 2828 | 0 | 3609674 | 2826 | 2826 | 0 | 3412411 | 2872 | 2872 | 0 | 2953535 | 2860 | 2860 | 0 | 3780585 | 2868 | 2868 | 0 | 3806005 | 2874 | 2874 | 0 | 3795130 | 2848 | 2848 | 0 | 3911999 | 2856 | 2856 | 0 | 4582343 | 2832 | 2832 | 0 | 4440612 | 2836 | 2836 | 0 | 3488933 | 2854 | 2854 | 0 | 3351485 | 2836 | 2836 | 0 | 4894774 | 2832 | 2832 | 0 | 4223851 | 2876 | 2876 | 0 | 4446861 | 2820 | 2820 | 0 | 4601305 | 2832 | 2832 | 0 | 3916128 | 2832 | 2832 | 0 | 3862893 | 2826 | 2826 | 0 | 4301803 | 2828 | 2828 | 0 | 4111966 | 2858 | 2858 | 0 | 3511557 | 2836 | 2836 | 0 | 3643517 | 2840 | 2840 | 0 | 3233508 | 2876 | 2876 | 0 | 3690737 | 2820 | 2820 | 64 | 0x7fcdf8740ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 114688 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 29653 | 27002 | 9610 | 3157 | 0 | 38993 | 200335.0 | 0.0 | 69252.0 | 131083.0 | 64 | 0x7fe6bad74ec0 | 0 | 393216 | 163840 | 0 | 0 | 0 | 0 | 0 | 29946 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 232.0 | 32768.0 | 4096 | 16384 | 302 | 40895 | 2005 | 0 | 56.0 | 10.0 | 0.0 | 200454.0 | 64 | 0x7f0732708ec0 | 6269 | 0 | 4096 | 6274 | 0 | 4096 | 6245 | 0 | 4096 | 6259 | 0 | 4096 | 6262 | 0 | 4096 | 6271 | 0 | 4096 | 6272 | 0 | 4096 | 6254 | 0 | 4096 | 6253 | 0 | 4096 | 6266 | 0 | 4096 | 6274 | 0 | 4096 | 6245 | 0 | 4096 | 6265 | 0 | 4096 | 6268 | 0 | 4096 | 6276 | 0 | 4096 | 6270 | 0 | 4096 | 6272 | 0 | 4096 | 6271 | 0 | 4096 | 6262 | 0 | 4096 | 6254 | 0 | 4096 | 6251 | 0 | 4096 | 6250 | 0 | 4096 | 6239 | 0 | 4096 | 6282 | 0 | 4096 | 6284 | 0 | 4096 | 6270 | 0 | 4096 | 6276 | 0 | 4096 | 6267 | 0 | 4096 | 6257 | 0 | 4096 | 6250 | 0 | 4096 | 6252 | 0 | 4096 | 6243 | 0 | 4096 | 64 | 0x7f779dc18ec0 | 2188 | 4100 | 2192 | 6288 | 2185 | 4098 | 2187 | 6283 | 2167 | 4097 | 2168 | 6264 | 2178 | 4096 | 2178 | 6274 | 2151 | 4096 | 2151 | 6247 | 2173 | 4096 | 2173 | 6269 | 2187 | 4096 | 2187 | 6283 | 2168 | 4096 | 2168 | 6264 | 2165 | 4096 | 2165 | 6261 | 2192 | 4096 | 2192 | 6288 | 2183 | 4096 | 2183 | 6279 | 2173 | 4096 | 2173 | 6269 | 2179 | 4096 | 2179 | 6275 | 2151 | 4096 | 2151 | 6247 | 2177 | 4096 | 2177 | 6273 | 2190 | 4096 | 2190 | 6286 | 2141 | 4096 | 2141 | 6237 | 2139 | 4096 | 2139 | 6235 | 2193 | 4098 | 2195 | 6291 | 2179 | 4096 | 2179 | 6275 | 2146 | 4096 | 2146 | 6242 | 2178 | 4096 | 2178 | 6274 | 2174 | 4096 | 2174 | 6270 | 2178 | 4096 | 2178 | 6274 | 2185 | 4096 | 2185 | 6281 | 2141 | 4096 | 2141 | 6237 | 2141 | 4096 | 2141 | 6237 | 2192 | 4097 | 2193 | 6289 | 2180 | 4096 | 2180 | 6276 | 2143 | 4096 | 2143 | 6239 | 2182 | 4096 | 2182 | 6278 | 2231 | 4097 | 2232 | 6328 | 64 | 0x7f2de1778ec0 | 0 | 0 | 1048576 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 32768 | 65551.0 | 0.0 | 0.0 | 0.0 | 64 | 0x7f6e6cc84ec0 | 4096 | 0 | 726 | 0 | 4096 | 0 | 1142 | 0 | 4098 | 0 | 686 | 0 | 4096 | 0 | 863 | 0 | 4097 | 0 | 963 | 0 | 4096 | 0 | 5 | 0 | 4096 | 0 | 398 | 0 | 4096 | 0 | 830 | 0 | 4096 | 0 | 644 | 0 | 4096 | 0 | 1569 | 0 | 4096 | 0 | 735 | 0 | 4096 | 0 | 0 | 0 | 4097 | 0 | 0 | 0 | 4096 | 0 | 778 | 0 | 4096 | 0 | 110 | 0 | 4097 | 0 | 490 | 0 | 4096 | 0 | 617 | 0 | 4097 | 0 | 312 | 0 | 4097 | 0 | 986 | 0 | 4096 | 0 | 400 | 0 | 4096 | 0 | 688 | 0 | 4096 | 0 | 697 | 0 | 4096 | 0 | 1169 | 0 | 4096 | 0 | 1587 | 0 | 4096 | 0 | 335 | 0 | 4100 | 0 | 364 | 0 | 4096 | 0 | 115 | 0 | 4096 | 0 | 962 | 0 | 4097 | 0 | 192 | 0 | 4096 | 0 | 419 | 0 | 4096 | 0 | 262 | 0 | 4096 | 0 | 936 | 0 | 64 | 0x7f0da5fd0ec0 | 0 | 65536 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 0.0 | 0.0 | 0.0 | 524288.0 | 0.0 | 0.0 | 0.0 | 22740 | 0 | 2720 | 39449 | 0 | 69871.0 | 131072.0 | 0.0 | 45668.0 | 64 | 0x7fafe65c4ec0 | 0 | 0 | 0 | 56 | 0 | 65536 | 65536 | 0 | 64 | 0x7fb469ab8ec0 | 10485760 | 65536 | 0 | 0 | 0 | 16384 | 0 | 0 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131085.0 | 86862.0 | 45515.0 | 0.0 | 64 | 0x7f01a6500ec0 | 7 | 0 | 0 | 1718556 | 601 | 0 | 0 | 2173730 | 9 | 0 | 0 | 2184674 | 0 | 0 | 0 | 1566960 | 186 | 0 | 0 | 1769966 | 0 | 0 | 0 | 1335502 | 115 | 0 | 0 | 1566006 | 69 | 0 | 0 | 2027798 | 148 | 0 | 0 | 2088893 | 245 | 0 | 0 | 1747696 | 0 | 0 | 0 | 1601415 | 0 | 0 | 0 | 1539228 | 0 | 0 | 0 | 1741793 | 57 | 0 | 0 | 1604001 | 0 | 0 | 0 | 1361187 | 167 | 0 | 0 | 1811428 | 178 | 0 | 0 | 2212179 | 0 | 0 | 0 | 1716561 | 0 | 0 | 0 | 1415555 | 110 | 0 | 0 | 1827595 | 0 | 0 | 0 | 1559563 | 45 | 0 | 0 | 2042839 | 0 | 0 | 0 | 1596467 | 0 | 0 | 0 | 1817249 | 0 | 0 | 0 | 1879937 | 0 | 0 | 0 | 1754566 | 0 | 0 | 0 | 1932763 | 0 | 0 | 0 | 1541753 | 186 | 0 | 0 | 1946934 | 0 | 0 | 0 | 1451277 | 0 | 0 | 0 | 1397953 | 0 | 0 | 0 | 1691843 | 64 | 0x7f14d1ef4ec0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 0 | 41934 | 0 | 0 | 64 | 0x7fa9abb20ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 56 | 131072.0 | 131072.0 | 0.0 | 2095169.0 | 64 | 0x7f45db7a0ec0 | 114688 | 0 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 59553355.0 | 201014624.0 | 50577064.0 | 131072.0 | 0.0 | 536773.0 | 0 | 0 | 25345 | 4083.0 | 131082.0 | 0.0 | 18.0 | 64 | 0x7f4ab1148ec0 | 32768 | 32768 | 0 | 64 | 0x7f919f270ec0 | 131072 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 122091435.0 | 60575096.0 | 0.0 | 64 | 0x7f2c30ad0ec0 | 0 | 195561 | 0 | 0 | 65536 | 63800 | 56 | 1680 | 199855576502899 | 199855576518579 |