Update queue structure to support async reclaim

Update queue structure to add members required for asynchronous reclaim
mechanism and dual-scratch. CP will set the AMD_QUEUE_CAPS_ASYNC_RECLAIM
bit on queue-connect to indicate whether the new features are supported.

The new members are ignored by previous versions of CP FW

Change-Id: Ic8e9ef41c5b1d04f09b43bc9b44b31527863d10f


[ROCm/ROCR-Runtime commit: 0344c8c0b6]

projects/rocr-runtime/runtime/hsa-runtime/inc/amd_hsa_queue.h

@@ -60,9 +60,22 @@ enum amd_queue_properties_t {
 // AMD Queue.
 #define AMD_QUEUE_ALIGN_BYTES 64
 #define AMD_QUEUE_ALIGN __ALIGNED__(AMD_QUEUE_ALIGN_BYTES)
+
+// AMD Queue Capabilities.
+typedef uint32_t amd_queue_capabilities32_t;
+enum amd_queue_capabilities_t {
+  /* Whether this CP queue supports dual-scratch and async-reclaim */
+  AMD_HSA_BITS_CREATE_ENUM_ENTRIES(AMD_QUEUE_CAPS_ASYNC_RECLAIM, 0, 1),
+};
+
+// Members tagged with "async-reclaim" are ignored by CP FW's that do not support
+// AMD_QUEUE_CAPS_ASYNC_RECLAIM. CP FW's that support async-reclaim also support
+// dual-scratch (alternate scratch).
+
 typedef struct AMD_QUEUE_ALIGN amd_queue_s {
   hsa_queue_t hsa_queue;
-  uint32_t reserved1[4];
+  uint32_t caps;
+  uint32_t reserved1[3];
   volatile uint64_t write_dispatch_id;
   uint32_t group_segment_aperture_base_hi;
   uint32_t private_segment_aperture_base_hi;
@@ -79,9 +92,18 @@ typedef struct AMD_QUEUE_ALIGN amd_queue_s {
   uint64_t scratch_backing_memory_byte_size;
   uint32_t scratch_wave64_lane_byte_size;
   amd_queue_properties32_t queue_properties;
-  uint32_t reserved3[2];
+  volatile uint64_t scratch_last_used_index;     /* async-reclaim */
   hsa_signal_t queue_inactive_signal;
-  uint32_t reserved4[14];
+  uint32_t reserved4[2];
+  volatile uint64_t alt_scratch_last_used_index; /* async-reclaim */
+  uint64_t alt_scratch_backing_memory_location;  /* async-reclaim */
+  uint64_t alt_scratch_backing_memory_byte_size; /* async-reclaim */
+  uint32_t alt_scratch_dispatch_limit_x;         /* async-reclaim */
+  uint32_t alt_scratch_dispatch_limit_y;         /* async-reclaim */
+  uint32_t alt_scratch_dispatch_limit_z;         /* async-reclaim */
+  uint32_t alt_scratch_wave64_lane_byte_size;    /* async-reclaim */
+  uint32_t alt_compute_tmpring_size;             /* async-reclaim */
+  uint32_t reserved5;
 } amd_queue_t;
 
 #endif // AMD_HSA_QUEUE_H