P4 to Git Change 1055292 by yaxunl@yaxunl_stg_win50 on 2014/07/15 10:23:56

EPR #389586 - Add workaround for VI SPI SGPR initialization hardware bug for HSAIL path.

	There is a hardware bug in VI (UBTS502672) which requires a workaround. Compute shaders need to tell shader compiler the available sGPR is 78 and set sGPUR usage in the compiled ISA to be 94. It has been done in AMDIL path but not done in HSAIL path. This change will apply the workaround to HSAIL path.

Affected files ...

... //depot/stg/opencl/drivers/opencl/compiler/lib/backends/gpu/scwrapper/SI/devStateSI.cpp#16 edit
... //depot/stg/opencl/drivers/opencl/compiler/lib/backends/gpu/scwrapper/SI/devStateSI.h#11 edit
... //depot/stg/opencl/drivers/opencl/compiler/lib/backends/gpu/scwrapper/SI/scCompileSI.cpp#41 edit
... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/OPTIONS.def#109 edit


[ROCm/clr commit: 1abfb8b305]

projects/clr/rocclr/compiler/lib/utils/OPTIONS.def

@@ -1072,10 +1072,6 @@ FLAG(OT_UINT32, OVIS_SUPPORT|OVIS_INTERNAL|OVA_REQUIRED, \
     "limit-scalar-registers", OptLimitScalarRegisters, 0, \
     "Maximum number of scalar registers that are available to the compiler.")
 
-// -workaround-UBTS502672=0|1 (default is 1)
-FLAG(OT_BOOL, OVIS_SUPPORT, "workaround-UBTS502672", WorkaroundUBTS502672, 1,\
-    "Enable/disable workaround for Iceland/Tonga SGPR issue UBTS 502672")
-
 // -lower-atomics=0|1 (default is 1)
 FLAG(OT_BOOL, OVIS_SUPPORT, "lower-atomics", LowerAtomics, 1,\
     "Enable/disable pass lowering OCL atomics to LLVM intrinsics (only for x86/x64)")