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P4 to Git Change 1288095 by jsjodin@jsjodin-git2p4-llvm on 2016/07/06 18:08:24

Bläddra i källkod 
SWDEV-3 - IR: Set TargetPrefix for some X86 and AArch64 intrinsics where it was missing

	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274390 91177308-0d34-0410-b5e6-96231b3b80d8

	GitHash: f0a4c116041f7c2aef7796c8b067f0947b69602d

Affected files ...

... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/include/llvm/IR/IntrinsicsAArch64.td#2 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/include/llvm/IR/IntrinsicsX86.td#2 edit
This commit is contained in:
foreman
2016-07-07 02:37:58 -04:00
förälder f9a2bb53b6
incheckning 162c07fcb4
7 ändrade filer med 82 tillägg och 90 borttagningar
Download Patch File Download Diff File Expand all files Collapse all files
rocclr/runtime/device/pal/palblit.cpp
+1 -1
Visa fil
@@ -2678,7 +2678,7 @@ KernelBlitManager::writeRawData(
const void* data const void* data
) const ) const
{ {
static_cast<pal::Memory&>(memory).writeRawData(gpu(), 0, size, data, false); static_cast<pal::Memory&>(memory).writeRawData(gpu(), size, data, false);
synchronize(); synchronize();
} }
rocclr/runtime/device/pal/paldevice.cpp
-1
Visa fil
@@ -706,7 +706,6 @@ Device::create(Pal::IDevice* device)
// palSettings ... // palSettings ...
palSettings->textureOptLevel = Pal::TextureFilterOptimizationsDisabled; palSettings->textureOptLevel = Pal::TextureFilterOptimizationsDisabled;
palSettings->forceHighClocks = appProfile_.enableHighPerformanceState(); palSettings->forceHighClocks = appProfile_.enableHighPerformanceState();
palSettings->cmdBufBatchedSubmitChainLimit = 0;
// Commit the new settings for the device // Commit the new settings for the device
result = iDev()->CommitSettingsAndInit(); result = iDev()->CommitSettingsAndInit();
rocclr/runtime/device/pal/palprintf.cpp
+1 -1
Visa fil
@@ -619,7 +619,7 @@ PrintfDbgHSA::init(
// Copy offset and number of bytes available for printf data // Copy offset and number of bytes available for printf data
// into the corresponding location in the debug buffer // into the corresponding location in the debug buffer
dbgBuffer_->writeRawData(gpu, 0, initSize, sysMem, true); dbgBuffer_->writeRawData(gpu, initSize, sysMem, true);
} }
return true; return true;
} }
rocclr/runtime/device/pal/palresource.cpp
+7 -5
Visa fil
@@ -1072,10 +1072,9 @@ Resource::free()
void void
Resource::writeRawData( Resource::writeRawData(
VirtualGPU& gpu, VirtualGPU& gpu,
size_t offset, size_t size,
size_t size,
const void* data, const void* data,
bool waitForEvent) const bool waitForEvent) const
{ {
GpuEvent event; GpuEvent event;
@@ -1083,8 +1082,11 @@ Resource::writeRawData(
// size needs to be DWORD aligned // size needs to be DWORD aligned
assert((size & 3) == 0); assert((size & 3) == 0);
gpu.eventBegin(MainEngine); gpu.eventBegin(MainEngine);
//! @todo Remove cache flush
//! It's a workaround for a PAL crash with embedded data, allocated before any command
gpu.flushCUCaches();
gpu.queue(MainEngine).addCmdMemRef(iMem()); gpu.queue(MainEngine).addCmdMemRef(iMem());
gpu.iCmd()->CmdUpdateMemory(*iMem(), offset, size, reinterpret_cast<const uint32_t*>(data)); gpu.iCmd()->CmdUpdateMemory(*iMem(), 0, size, reinterpret_cast<const uint32_t*>(data));
gpu.eventEnd(MainEngine, event); gpu.eventEnd(MainEngine, event);
setBusy(gpu, event); setBusy(gpu, event);
@@ -1936,7 +1938,7 @@ Resource::warmUpRenames(VirtualGPU& gpu)
uint dummy = 0; uint dummy = 0;
const bool NoWait = false; const bool NoWait = false;
// Write 0 for the buffer paging by VidMM // Write 0 for the buffer paging by VidMM
writeRawData(gpu, 0, sizeof(dummy), &dummy, NoWait); writeRawData(gpu, sizeof(dummy), &dummy, NoWait);
const bool Force = true; const bool Force = true;
rename(gpu, Force); rename(gpu, Force);
} }
rocclr/runtime/device/pal/palresource.hpp
+4 -5
Visa fil
@@ -240,11 +240,10 @@ public:
* *
*/ */
void writeRawData( void writeRawData(
VirtualGPU& gpu, //!< Virtual GPU device object VirtualGPU& gpu, //!< Virtual GPU device object
size_t offset, //!< Offset for in the buffer for data size_t size, //!< Size in bytes of data to be copied(multiple of DWORDS)
size_t size, //!< Size in bytes of data to be copied(multiple of DWORDS) const void* data, //!< Data to be copied
const void* data, //!< Data to be copied bool waitForEvent //!< Wait for event complete
bool waitForEvent //!< Wait for event complete
) const; ) const;
//! Returns the offset in GPU memory for aliases //! Returns the offset in GPU memory for aliases
rocclr/runtime/device/pal/palvirtual.cpp
+61 -60
Visa fil
@@ -155,11 +155,11 @@ VirtualGPU::Queue::removeCmdMemRef(Pal::IGpuMemory* iMem)
} }
uint uint
VirtualGPU::Queue::submit(bool forceFlush) VirtualGPU::Queue::submit()
{ {
cmdCnt_++; cmdCnt_++;
uint id = cmdBufIdCurrent_; uint id = cmdBufIdCurrent_;
if ((cmdCnt_ > MaxCommands) || forceFlush) { if ((cmdCnt_ > MaxCommands) || GPU_FLUSH_ON_EXECUTION) {
if (!flush()) { if (!flush()) {
return GpuEvent::InvalidID; return GpuEvent::InvalidID;
} }
@@ -238,11 +238,6 @@ VirtualGPU::Queue::flush()
return false; return false;
} }
// Reset command buffer, so CB chunks could be reused
if (Pal::Result::Success != iCmdBuffs_[cmdBufIdSlot_]->Reset(nullptr, false)) {
LogError("PAL failed CB reset!");
return false;
}
// Start command buffer building // Start command buffer building
Pal::CmdBufferBuildInfo cmdBuildInfo = {}; Pal::CmdBufferBuildInfo cmdBuildInfo = {};
if (Pal::Result::Success != iCmdBuffs_[cmdBufIdSlot_]->Begin(cmdBuildInfo)) { if (Pal::Result::Success != iCmdBuffs_[cmdBufIdSlot_]->Begin(cmdBuildInfo)) {
@@ -596,44 +591,41 @@ VirtualGPU::createVirtualQueue(uint deviceQueueSize)
if ((virtualQueue_ == nullptr) || !virtualQueue_->create(type)) { if ((virtualQueue_ == nullptr) || !virtualQueue_->create(type)) {
return false; return false;
} }
address ptr = reinterpret_cast<address>(
if (GPU_PRINT_CHILD_KERNEL != 0) { virtualQueue_->map(this, Resource::WriteOnly));
address ptr = reinterpret_cast<address>( if (nullptr == ptr) {
virtualQueue_->map(this, Resource::WriteOnly)); return false;
if (nullptr == ptr) {
return false;
}
} }
// Clear memory
memset(ptr, 0, allocSize);
uint64_t vaBase = virtualQueue_->vmAddress();
AmdVQueueHeader* header = reinterpret_cast<AmdVQueueHeader*>(ptr);
uint64_t vaBase = virtualQueue_->vmAddress();
AmdVQueueHeader header = {};
// Initialize the virtual queue header // Initialize the virtual queue header
header.aql_slot_num = numSlots; header->aql_slot_num = numSlots;
header.event_slot_num = dev().settings().numDeviceEvents_; header->event_slot_num = dev().settings().numDeviceEvents_;
header.event_slot_mask = vaBase + eventMaskOffs; header->event_slot_mask = vaBase + eventMaskOffs;
header.event_slots = vaBase + eventsOffs; header->event_slots = vaBase + eventsOffs;
header.aql_slot_mask = vaBase + slotMaskOffs; header->aql_slot_mask = vaBase + slotMaskOffs;
header.wait_size = dev().settings().numWaitEvents_; header->wait_size = dev().settings().numWaitEvents_;
header.arg_size = dev().info().maxParameterSize_ + 64; header->arg_size = dev().info().maxParameterSize_ + 64;
header.mask_groups = maskGroups_; header->mask_groups = maskGroups_;
vqHeader_ = new AmdVQueueHeader; vqHeader_ = new AmdVQueueHeader;
if (nullptr == vqHeader_) { if (nullptr == vqHeader_) {
return false; return false;
} }
*vqHeader_ = header; *vqHeader_ = *header;
virtualQueue_->writeRawData(*this, 0, sizeof(AmdVQueueHeader), &header, false);
// Go over all slots and perform initialization // Go over all slots and perform initialization
AmdAqlWrap slot = {}; AmdAqlWrap* slots = reinterpret_cast<AmdAqlWrap*>(&header[1]);
size_t offset = sizeof(AmdVQueueHeader);
for (uint i = 0; i < numSlots; ++i) { for (uint i = 0; i < numSlots; ++i) {
uint64_t argStart = vaBase + argOffs + i * singleArgSize; uint64_t argStart = vaBase + argOffs + i * singleArgSize;
slot.aql.kernarg_address = reinterpret_cast<void*>(argStart); slots[i].aql.kernarg_address = reinterpret_cast<void*>(argStart);
slot.wait_list = argStart + dev().info().maxParameterSize_ + 64; slots[i].wait_list = argStart + dev().info().maxParameterSize_ + 64;
virtualQueue_->writeRawData(*this, offset, sizeof(AmdAqlWrap), &slot, false); }
offset += sizeof(AmdAqlWrap); // Upload data back to local memory
if (GPU_PRINT_CHILD_KERNEL == 0) {
virtualQueue_->unmap(this);
} }
schedParams_ = new Memory(dev(), 64 * Ki); schedParams_ = new Memory(dev(), 64 * Ki);
@@ -641,7 +633,7 @@ VirtualGPU::createVirtualQueue(uint deviceQueueSize)
return false; return false;
} }
address ptr = reinterpret_cast<address>(schedParams_->map(this)); ptr = reinterpret_cast<address>(schedParams_->map(this));
deviceQueueSize_ = deviceQueueSize; deviceQueueSize_ = deviceQueueSize;
@@ -697,9 +689,9 @@ VirtualGPU::create(bool profiling, uint deviceQueueSize)
state_.profiling_ = profiling; state_.profiling_ = profiling;
Pal::CmdAllocatorCreateInfo createInfo = {}; Pal::CmdAllocatorCreateInfo createInfo = {};
createInfo.flags.threadSafe = true;
// \todo forces PAL to reuse CBs, but requires postamble // \todo forces PAL to reuse CBs, but requires postamble
createInfo.flags.autoMemoryReuse = false; createInfo.flags.autoMemoryReuse = true;
createInfo.flags.threadSafe = false;
createInfo.allocInfo[Pal::CommandDataAlloc].allocHeap = createInfo.allocInfo[Pal::CommandDataAlloc].allocHeap =
Pal::GpuHeapGartCacheable; Pal::GpuHeapGartCacheable;
createInfo.allocInfo[Pal::CommandDataAlloc].allocSize = 128 * Ki; createInfo.allocInfo[Pal::CommandDataAlloc].allocSize = 128 * Ki;
@@ -2108,28 +2100,34 @@ VirtualGPU::submitKernelInternal(
} }
if (!dev().settings().useDeviceQueue_) { if (!dev().settings().useDeviceQueue_) {
Unimplemented();
/*
// Add the termination handshake to the host queue // Add the termination handshake to the host queue
eventBegin(MainEngine); eventBegin(MainEngine);
//iCmd()->CmdVirtualQueueHandshake(*gpuDefQueue->schedParams_->iMem(), cs()->VirtualQueueHandshake(gpuDefQueue->schedParams_->iMem(),
// vmParentWrap + offsetof(AmdAqlWrap, state), AQL_WRAP_DONE, vmParentWrap + offsetof(AmdAqlWrap, state), AQL_WRAP_DONE,
// vmParentWrap + offsetof(AmdAqlWrap, child_counter), vmParentWrap + offsetof(AmdAqlWrap, child_counter),
// 0, dev().settings().useDeviceQueue_); 0, dev().settings().useDeviceQueue_);
eventEnd(MainEngine, gpuEvent); eventEnd(MainEngine, gpuEvent);
*/
} }
// Get the global loop start before the scheduler // Get the global loop start before the scheduler
//Pal::gpusize loopStart = gpuDefQueue->iCmd()->CmdVirtualQueueDispatcherStart(); Unimplemented();
//static_cast<KernelBlitManager&>(gpuDefQueue->blitMgr()).runScheduler( /*
// *gpuDefQueue->virtualQueue_, mcaddr loopStart = gpuDefQueue->cs()->VirtualQueueDispatcherStart();
// *gpuDefQueue->schedParams_, gpuDefQueue->schedParamIdx_, static_cast<KernelBlitManager&>(gpuDefQueue->blitMgr()).runScheduler(
// gpuDefQueue->vqHeader_->aql_slot_num / (DeviceQueueMaskSize * maskGroups_)); *gpuDefQueue->virtualQueue_,
*gpuDefQueue->schedParams_, gpuDefQueue->schedParamIdx_,
gpuDefQueue->vqHeader_->aql_slot_num / (DeviceQueueMaskSize * maskGroups_));
const static bool FlushL2 = true; const static bool FlushL2 = true;
gpuDefQueue->flushCUCaches(FlushL2); gpuDefQueue->flushCUCaches(FlushL2);
// Get the address of PM4 template and add write it to params // Get the address of PM4 template and add write it to params
//! @note DMA flush must not occur between patch and the scheduler //! @note DMA flush must not occur between patch and the scheduler
mcaddr patchStart = gpuDefQueue->cs()->VirtualQueueDispatcherStart();
*/
Pal::gpusize patchStart = 0; Pal::gpusize patchStart = 0;
//Pal::gpusize patchStart = gpuDefQueue->iCmd()->CmdVirtualQueueDispatcherStart();
// Program parameters for the scheduler // Program parameters for the scheduler
SchedulerParam* param = &reinterpret_cast<SchedulerParam*> SchedulerParam* param = &reinterpret_cast<SchedulerParam*>
(gpuDefQueue->schedParams_->data())[gpuDefQueue->schedParamIdx_]; (gpuDefQueue->schedParams_->data())[gpuDefQueue->schedParamIdx_];
@@ -2170,28 +2168,31 @@ VirtualGPU::submitKernelInternal(
Pal::gpusize signalAddr = gpuDefQueue->schedParams_->vmAddress() + Pal::gpusize signalAddr = gpuDefQueue->schedParams_->vmAddress() +
gpuDefQueue->schedParamIdx_ * sizeof(SchedulerParam); gpuDefQueue->schedParamIdx_ * sizeof(SchedulerParam);
Unimplemented();
/*
gpuDefQueue->eventBegin(MainEngine); gpuDefQueue->eventBegin(MainEngine);
//gpuDefQueue->iCmd()->CmdVirtualQueueDispatcherEnd( gpuDefQueue->cs()->VirtualQueueDispatcherEnd(
// signalAddr, loopStart, gpuDefQueue->vqHeader_->aql_slot_num / gpuDefQueue->vmMems(), gpuDefQueue->cal_.memCount_,
// (DeviceQueueMaskSize * maskGroups_)); signalAddr, loopStart, gpuDefQueue->vqHeader_->aql_slot_num /
// Note: Device enqueue can't have extra commands after INDIRECT_BUFFER call. (DeviceQueueMaskSize * maskGroups_));
// Thus TS command for profiling has to follow in the next CB. gpuDefQueue->eventEnd(MainEngine, gpuEvent);
constexpr bool ForceSubmitFirst = true; */
gpuDefQueue->eventEnd(MainEngine, gpuEvent, ForceSubmitFirst);
// Set GPU event for the used resources // Set GPU event for the used resources
for (uint i = 0; i < memList.size(); ++i) { for (uint i = 0; i < memList.size(); ++i) {
memList[i]->setBusy(*gpuDefQueue, gpuEvent); memList[i]->setBusy(*gpuDefQueue, gpuEvent);
} }
if (dev().settings().useDeviceQueue_) { if (dev().settings().useDeviceQueue_) {
Unimplemented();
/*
// Add the termination handshake to the host queue // Add the termination handshake to the host queue
eventBegin(MainEngine); eventBegin(MainEngine);
//iCmd()->CmdVirtualQueueHandshake(*gpuDefQueue->schedParams_->iMem(), cs()->VirtualQueueHandshake(gpuDefQueue->schedParams_->iMem(),
// vmParentWrap + offsetof(AmdAqlWrap, state), AQL_WRAP_DONE, vmParentWrap + offsetof(AmdAqlWrap, state), AQL_WRAP_DONE,
// vmParentWrap + offsetof(AmdAqlWrap, child_counter), vmParentWrap + offsetof(AmdAqlWrap, child_counter),
// signalAddr, dev().settings().useDeviceQueue_); signalAddr, dev().settings().useDeviceQueue_);
eventEnd(MainEngine, gpuEvent); eventEnd(MainEngine, gpuEvent);
*/
} }
++gpuDefQueue->schedParamIdx_ %= ++gpuDefQueue->schedParamIdx_ %=
@@ -3249,7 +3250,7 @@ VirtualGPU::writeVQueueHeader(VirtualGPU& hostQ, uint64_t kernelTable)
{ {
const static bool Wait = true; const static bool Wait = true;
vqHeader_->kernel_table = kernelTable; vqHeader_->kernel_table = kernelTable;
virtualQueue_->writeRawData(hostQ, 0, sizeof(AmdVQueueHeader), vqHeader_, Wait); virtualQueue_->writeRawData(hostQ, sizeof(AmdVQueueHeader), vqHeader_, !Wait);
} }
void void
rocclr/runtime/device/pal/palvirtual.hpp
+8 -17
Visa fil
@@ -79,7 +79,7 @@ public:
//! Flushes the current command buffer to HW //! Flushes the current command buffer to HW
//! Returns ID associated with the submission //! Returns ID associated with the submission
uint submit(bool forceFlush); uint submit();
bool flush(); bool flush();
@@ -401,17 +401,15 @@ public:
//! Returns queue, associated with VirtualGPU //! Returns queue, associated with VirtualGPU
Queue& queue(EngineType id) const { return *queues_[id]; } Queue& queue(EngineType id) const { return *queues_[id]; }
void flushCUCaches(bool flushL2 = false) const void flushCUCaches() const
{ {
Pal::BarrierInfo barrier = {}; Pal::BarrierInfo barrier = {};
barrier.pipePointWaitCount = 1; barrier.pipePointWaitCount = 1;
Pal::HwPipePoint point = Pal::HwPipePostCs; Pal::HwPipePoint point = Pal::HwPipePostCs;
barrier.pPipePoints = &point; barrier.pPipePoints = &point;
barrier.transitionCount = 1; barrier.transitionCount = 1;
uint32_t cacheMask = (flushL2) ? Pal::CoherCopy : Pal::CoherShader; Pal::BarrierTransition trans = {Pal::CoherShader, Pal::CoherShader,
Pal::BarrierTransition trans = { cacheMask, cacheMask, {nullptr, { {Pal::ImageAspect::Color, 0, 0}, 0, 0 }, Pal::LayoutShaderRead, Pal::LayoutShaderRead}};
{ nullptr, { { Pal::ImageAspect::Color, 0, 0 }, 0, 0 },
Pal::LayoutShaderRead, Pal::LayoutShaderRead}};
barrier.pTransitions = &trans; barrier.pTransitions = &trans;
barrier.waitPoint = Pal::HwPipePreCs; barrier.waitPoint = Pal::HwPipePreCs;
iCmd()->CmdBarrier(barrier); iCmd()->CmdBarrier(barrier);
@@ -422,17 +420,10 @@ public:
profileEvent(engId, Begin); profileEvent(engId, Begin);
} }
void eventEnd(EngineType engId, GpuEvent& event, bool forceExec = false) const { void eventEnd(EngineType engId, GpuEvent& event) const {
constexpr bool End = false; const static bool End = false;
if (forceExec) { profileEvent(engId, End);
constexpr bool ForceFlush = true; event.id = queues_[engId]->submit();
event.id = queues_[engId]->submit(ForceFlush);
profileEvent(engId, End);
}
else {
profileEvent(engId, End);
event.id = queues_[engId]->submit(GPU_FLUSH_ON_EXECUTION);
}
event.engineId_ = engId; event.engineId_ = engId;
} }