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P4 to Git Change 1701409 by gandryey@gera-w8 on 2018/11/01 17:43:16

Просмотр исходного кода 
SWDEV-79445 - OCL generic changes and code clean-up
	- Remove obsolete settings
	- Simplify some logic when runtime checks dimension override in the dispatch critical path

Affected files ...

... //depot/stg/opencl/drivers/opencl/api/opencl/amdocl/cl_execute.cpp#29 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/device.cpp#233 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/device.hpp#323 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/devkernel.cpp#9 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpudevice.cpp#599 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpukernel.cpp#333 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuprogram.cpp#246 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuresource.cpp#246 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpusettings.cpp#361 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpusettings.hpp#103 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuvirtual.cpp#425 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gslbe/src/rt/GSLDevice.cpp#184 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palsettings.cpp#60 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palsettings.hpp#20 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/rocsettings.cpp#39 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/rocsettings.hpp#18 edit
... //depot/stg/opencl/drivers/opencl/runtime/utils/flags.hpp#300 edit
Этот коммит содержится в:
foreman
2018-11-01 17:49:35 -04:00
родитель 320c9a6375
Коммит 21f6e4337a
16 изменённых файлов: 62 добавлений и 172 удалений
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rocclr/runtime/device/device.cpp
+7 -1
Просмотреть файл
@@ -573,7 +573,6 @@ namespace device {
Settings::Settings() : value_(0) {
assert((ClExtTotal < (8 * sizeof(extensions_))) && "Too many extensions!");
extensions_ = 0;
partialDispatch_ = false;
supportRA_ = true;
customHostAllocator_ = false;
waitCommand_ = AMD_OCL_WAIT_COMMAND;
@@ -581,6 +580,13 @@ Settings::Settings() : value_(0) {
enableHwDebug_ = false;
commandQueues_ = 200; //!< Field value set to maximum number
//!< concurrent Virtual GPUs for default
overrideLclSet = (!flagIsDefault(GPU_MAX_WORKGROUP_SIZE)) ? 1 : 0;
overrideLclSet |= (!flagIsDefault(GPU_MAX_WORKGROUP_SIZE_2D_X) ||
!flagIsDefault(GPU_MAX_WORKGROUP_SIZE_2D_Y)) ? 2 : 0;
overrideLclSet |= (!flagIsDefault(GPU_MAX_WORKGROUP_SIZE_3D_X) ||
!flagIsDefault(GPU_MAX_WORKGROUP_SIZE_3D_Y) ||
!flagIsDefault(GPU_MAX_WORKGROUP_SIZE_3D_Z)) ? 4 : 0;
}
void Memory::saveMapInfo(const void* mapAddress, const amd::Coord3D origin,
rocclr/runtime/device/device.hpp
+2 -2
Просмотреть файл
@@ -507,8 +507,8 @@ class Settings : public amd::HeapObject {
uint64_t extensions_; //!< Supported OCL extensions
union {
struct {
uint overrideLclSet : 3; //!< Bit mask to override the local size
uint apuSystem_ : 1; //!< Device is APU system with shared memory
uint partialDispatch_ : 1; //!< Enables partial dispatch
uint supportRA_ : 1; //!< Support RA channel order format
uint waitCommand_ : 1; //!< Enables a wait for every submitted command
uint customHostAllocator_ : 1; //!< True if device has custom host allocator
@@ -520,7 +520,7 @@ class Settings : public amd::HeapObject {
uint singleFpDenorm_ : 1; //!< Support Single FP Denorm
uint gfx10Hsail_ : 1 ; //!< GFX10 HSAIL path
uint useLightning_ : 1; //!< Enable LC path for this device
uint reserved_ : 20;
uint reserved_ : 18;
};
uint value_;
};
rocclr/runtime/device/devkernel.cpp
+5 -17
Просмотреть файл
@@ -119,16 +119,7 @@ void Kernel::FindLocalWorkSize(size_t workDim, const amd::NDRange& gblWorkSize,
if (workGroupInfo()->compileSize_[0] == 0) {
// Find the default local workgroup size, if it wasn't specified
if (lclWorkSize[0] == 0) {
bool b1DOverrideSet = !flagIsDefault(GPU_MAX_WORKGROUP_SIZE);
bool b2DOverrideSet = !flagIsDefault(GPU_MAX_WORKGROUP_SIZE_2D_X) ||
!flagIsDefault(GPU_MAX_WORKGROUP_SIZE_2D_Y);
bool b3DOverrideSet = !flagIsDefault(GPU_MAX_WORKGROUP_SIZE_3D_X) ||
!flagIsDefault(GPU_MAX_WORKGROUP_SIZE_3D_Y) ||
!flagIsDefault(GPU_MAX_WORKGROUP_SIZE_3D_Z);
bool overrideSet = ((workDim == 1) && b1DOverrideSet) || ((workDim == 2) && b2DOverrideSet) ||
((workDim == 3) && b3DOverrideSet);
if (!overrideSet) {
if ((dev().settings().overrideLclSet & (1 << (workDim - 1))) == 0) {
// Find threads per group
size_t thrPerGrp = workGroupInfo()->size_;
@@ -137,8 +128,7 @@ void Kernel::FindLocalWorkSize(size_t workDim, const amd::NDRange& gblWorkSize,
// and thread group is a multiple value of wavefronts
((thrPerGrp % workGroupInfo()->wavefrontSize_) == 0) &&
// and it's 2 or 3-dimensional workload
(workDim > 1) && ((dev().settings().partialDispatch_) ||
(((gblWorkSize[0] % 16) == 0) && ((gblWorkSize[1] % 16) == 0)))) {
(workDim > 1) && (((gblWorkSize[0] % 16) == 0) && ((gblWorkSize[1] % 16) == 0))) {
// Use 8x8 workgroup size if kernel has image writes
if (flags_.imageWriteEna_ || (thrPerGrp != dev().info().preferredWorkGroupSize_)) {
lclWorkSize[0] = 8;
@@ -166,12 +156,10 @@ void Kernel::FindLocalWorkSize(size_t workDim, const amd::NDRange& gblWorkSize,
// Assuming DWORD access
const uint cacheLineMatch = dev().info().globalMemCacheLineSize_ >> 2;
// Check if partial dispatch is enabled and
if (dev().settings().partialDispatch_ &&
// we couldn't find optimal workload
(((lclWorkSize.product() % workGroupInfo()->wavefrontSize_) != 0) ||
// Check if we couldn't find optimal workload
if (((lclWorkSize.product() % workGroupInfo()->wavefrontSize_) != 0) ||
// or size is too small for the cache line
(lclWorkSize[0] < cacheLineMatch))) {
(lclWorkSize[0] < cacheLineMatch)) {
size_t maxSize = 0;
size_t maxDim = 0;
for (uint d = 0; d < workDim; ++d) {
rocclr/runtime/device/gpu/gpudevice.cpp
+1 -6
Просмотреть файл
@@ -1058,12 +1058,7 @@ bool Device::initializeHeapResources() {
if (settings().stagedXferSize_ != 0) {
// Initialize staged write buffers
if (settings().stagedXferWrite_) {
Resource::MemoryType type;
if (settings().stagingWritePersistent_ && !settings().disablePersistent_) {
type = Resource::Persistent;
} else {
type = Resource::RemoteUSWC;
}
Resource::MemoryType type = Resource::RemoteUSWC;
xferWrite_ = new XferBuffers(*this, type, amd::alignUp(settings().stagedXferSize_, 4 * Ki));
if ((xferWrite_ == NULL) || !xferWrite_->create()) {
LogError("Couldn't allocate transfer buffer objects for read");
rocclr/runtime/device/gpu/gpukernel.cpp
+33 -51
Просмотреть файл
@@ -628,7 +628,7 @@ bool NullKernel::create(const std::string& code, const std::string& metadata,
if ((binaryCode == NULL) && (binarySize == 0) && !code.empty()) {
acl_error err;
std::string arch = GPU_TARGET_INFO_ARCH;
std::string arch = "amdil";
if (nullDev().settings().use64BitPtr_) {
arch += "64";
}
@@ -1028,16 +1028,7 @@ void Kernel::findLocalWorkSize(size_t workDim, const amd::NDRange& gblWorkSize,
if (workGroupInfo()->compileSize_[0] == 0) {
// Find the default local workgroup size, if it wasn't specified
if (lclWorkSize[0] == 0) {
bool b1DOverrideSet = !flagIsDefault(GPU_MAX_WORKGROUP_SIZE);
bool b2DOverrideSet = !flagIsDefault(GPU_MAX_WORKGROUP_SIZE_2D_X) ||
!flagIsDefault(GPU_MAX_WORKGROUP_SIZE_2D_Y);
bool b3DOverrideSet = !flagIsDefault(GPU_MAX_WORKGROUP_SIZE_3D_X) ||
!flagIsDefault(GPU_MAX_WORKGROUP_SIZE_3D_Y) ||
!flagIsDefault(GPU_MAX_WORKGROUP_SIZE_3D_Z);
bool overrideSet = ((workDim == 1) && b1DOverrideSet) || ((workDim == 2) && b2DOverrideSet) ||
((workDim == 3) && b3DOverrideSet);
if (!overrideSet) {
if ((dev().settings().overrideLclSet & (1 << (workDim - 1))) == 0) {
// Find threads per group
size_t thrPerGrp = workGroupInfo()->size_;
@@ -1046,8 +1037,7 @@ void Kernel::findLocalWorkSize(size_t workDim, const amd::NDRange& gblWorkSize,
// and thread group is a multiple value of wavefronts
((thrPerGrp % workGroupInfo()->wavefrontSize_) == 0) &&
// and it's 2 or 3-dimensional workload
(workDim > 1) && ((dev().settings().partialDispatch_) ||
(((gblWorkSize[0] % 16) == 0) && ((gblWorkSize[1] % 16) == 0)))) {
(workDim > 1) && ((gblWorkSize[0] % 16) == 0) && ((gblWorkSize[1] % 16) == 0)) {
// Use 8x8 workgroup size if kernel has image writes
if ((flags() & ImageWrite) || (thrPerGrp != nullDev().info().preferredWorkGroupSize_)) {
lclWorkSize[0] = 8;
@@ -1072,12 +1062,10 @@ void Kernel::findLocalWorkSize(size_t workDim, const amd::NDRange& gblWorkSize,
// Assuming DWORD access
const uint cacheLineMatch = dev().settings().cacheLineSize_ >> 2;
// Check if partial dispatch is enabled and
if (dev().settings().partialDispatch_ &&
// we couldn't find optimal workload
(((lclWorkSize.product() % workGroupInfo()->wavefrontSize_) != 0) ||
// Check if we couldn't find optimal workload
if (((lclWorkSize.product() % workGroupInfo()->wavefrontSize_) != 0) ||
// or size is too small for the cache line
(lclWorkSize[0] < cacheLineMatch))) {
(lclWorkSize[0] < cacheLineMatch)) {
size_t maxSize = 0;
size_t maxDim = 0;
for (uint d = 0; d < workDim; ++d) {
@@ -1196,17 +1184,15 @@ void Kernel::setupProgramGrid(VirtualGPU& gpu, size_t workDim, const amd::NDRang
pGroupOffset[2] = groupOffset[2];
pNDRangeGlobalOffset[2 + glbABIShift] = glbWorkOffsetOrg[2];
if (dev().settings().partialDispatch_) {
// Check if partial workgroup dispatch is required
progGrid->partialGridBlock.depth = gblWorkSize[2] % lclWorkSize[2];
if (progGrid->partialGridBlock.depth != 0) {
partialGrid = true;
// Increment the number of groups
progGrid->gridSize.depth++;
pNumGroups[2]++;
} else {
progGrid->partialGridBlock.depth = lclWorkSize[2];
}
// Check if partial workgroup dispatch is required
progGrid->partialGridBlock.depth = gblWorkSize[2] % lclWorkSize[2];
if (progGrid->partialGridBlock.depth != 0) {
partialGrid = true;
// Increment the number of groups
progGrid->gridSize.depth++;
pNumGroups[2]++;
} else {
progGrid->partialGridBlock.depth = lclWorkSize[2];
}
// Fall through to fill 2D and 1D dimensions...
case 2:
@@ -1221,17 +1207,15 @@ void Kernel::setupProgramGrid(VirtualGPU& gpu, size_t workDim, const amd::NDRang
pGroupOffset[1] = groupOffset[1];
pNDRangeGlobalOffset[1 + glbABIShift] = glbWorkOffsetOrg[1];
if (dev().settings().partialDispatch_) {
// Check if partial workgroup dispatch is required
progGrid->partialGridBlock.height = gblWorkSize[1] % lclWorkSize[1];
if (progGrid->partialGridBlock.height != 0) {
partialGrid = true;
// Increment the number of groups
progGrid->gridSize.height++;
pNumGroups[1]++;
} else {
progGrid->partialGridBlock.height = lclWorkSize[1];
}
// Check if partial workgroup dispatch is required
progGrid->partialGridBlock.height = gblWorkSize[1] % lclWorkSize[1];
if (progGrid->partialGridBlock.height != 0) {
partialGrid = true;
// Increment the number of groups
progGrid->gridSize.height++;
pNumGroups[1]++;
} else {
progGrid->partialGridBlock.height = lclWorkSize[1];
}
// Fall through to fill 1D dimension...
case 1:
@@ -1246,17 +1230,15 @@ void Kernel::setupProgramGrid(VirtualGPU& gpu, size_t workDim, const amd::NDRang
pGroupOffset[0] = groupOffset[0];
pNDRangeGlobalOffset[0 + glbABIShift] = glbWorkOffsetOrg[0];
if (dev().settings().partialDispatch_) {
// Check if partial workgroup dispatch is required
progGrid->partialGridBlock.width = gblWorkSize[0] % lclWorkSize[0];
if (progGrid->partialGridBlock.width != 0) {
partialGrid = true;
// Increment the number of groups
progGrid->gridSize.width++;
pNumGroups[0]++;
} else {
progGrid->partialGridBlock.width = lclWorkSize[0];
}
// Check if partial workgroup dispatch is required
progGrid->partialGridBlock.width = gblWorkSize[0] % lclWorkSize[0];
if (progGrid->partialGridBlock.width != 0) {
partialGrid = true;
// Increment the number of groups
progGrid->gridSize.width++;
pNumGroups[0]++;
} else {
progGrid->partialGridBlock.width = lclWorkSize[0];
}
break;
default:
rocclr/runtime/device/gpu/gpuprogram.cpp
+1 -1
Просмотреть файл
@@ -25,7 +25,7 @@ namespace gpu {
const aclTargetInfo& NullProgram::info(const char* str) {
acl_error err;
std::string arch = GPU_TARGET_INFO_ARCH;
std::string arch = "amdil";
if (dev().settings().use64BitPtr_) {
arch += "64";
}
rocclr/runtime/device/gpu/gpuresource.cpp
+2 -3
Просмотреть файл
@@ -1079,9 +1079,8 @@ bool Resource::partialMemCopyTo(VirtualGPU& gpu, const amd::Coord3D& srcOrigin,
// Check if runtime can use async memory copy,
// even if a caller didn't request async
if (dev().settings().asyncMemCopy_ &&
// Keep ASYNC if profiling is disabled or sdma profiling is possible
(!gpu.profiling() || dev().settings().sdmaProfiling_) &&
// Keep ASYNC if profiling is disabled or sdma profiling is possible
if ((!gpu.profiling() || dev().settings().sdmaProfiling_) &&
(!cal()->cardMemory_ || !dstResource.cal()->cardMemory_)) {
// Switch to SDMA engine
gpu.engineID_ = SdmaEngine;
rocclr/runtime/device/gpu/gpusettings.cpp
-18
Просмотреть файл
@@ -44,9 +44,6 @@ Settings::Settings() {
// We will enable staged read/write if we use local memory
disablePersistent_ = false;
// By Default persistent writes will be disabled.
stagingWritePersistent_ = GPU_STAGING_WRITE_PERSISTENT;
maxRenames_ = 16;
maxRenameSize_ = 4 * Mi;
@@ -77,9 +74,6 @@ Settings::Settings() {
reportFMAF_ = false;
reportFMA_ = false;
// Disable async memory transfers by default
asyncMemCopy_ = false;
// GPU device by default
apuSystem_ = false;
@@ -294,7 +288,6 @@ bool Settings::create(const CALdeviceattribs& calAttr, bool reportAsOCL12Device,
}
supportRA_ = false;
partialDispatch_ = GPU_PARTIAL_DISPATCH;
numMemDependencies_ = GPU_NUM_MEM_DEPENDENCY;
enableExtension(ClKhrInt64BaseAtomics);
@@ -352,8 +345,6 @@ bool Settings::create(const CALdeviceattribs& calAttr, bool reportAsOCL12Device,
// HW doesn't support untiled image writes
// hostMemDirectAccess_ |= HostMemImage;
asyncMemCopy_ = true;
// Make sure device actually supports double precision
doublePrecision_ = (calAttr.doublePrecision) ? doublePrecision_ : false;
if (doublePrecision_) {
@@ -447,15 +438,6 @@ void Settings::override() {
debugFlags_ = DEBUG_GPU_FLAGS;
}
// Check async memory transfer
if (!flagIsDefault(GPU_ASYNC_MEM_COPY)) {
asyncMemCopy_ = GPU_ASYNC_MEM_COPY;
}
if (!flagIsDefault(DEBUG_GPU_FLAGS)) {
debugFlags_ = DEBUG_GPU_FLAGS;
}
if (!flagIsDefault(GPU_XFER_BUFFER_SIZE)) {
xferBufSize_ = GPU_XFER_BUFFER_SIZE * Ki;
}
rocclr/runtime/device/gpu/gpusettings.hpp
+1 -3
Просмотреть файл
@@ -57,12 +57,10 @@ class Settings : public device::Settings {
uint useSingleScratch_ : 1; //!< Allocates single scratch per device
uint sdmaProfiling_ : 1; //!< Enables SDMA profiling
uint hsail_ : 1; //!< Enables HSAIL compilation
uint stagingWritePersistent_ : 1; //!< Enables persistent writes
uint svmAtomics_ : 1; //!< SVM device atomics
uint svmFineGrainSystem_ : 1; //!< SVM fine grain system support
uint asyncMemCopy_ : 1; //!< Use async memory transfers
uint useDeviceQueue_ : 1; //!< Submit to separate device queue
uint reserved_ : 9;
uint reserved_ : 11;
};
uint value_;
};
rocclr/runtime/device/gpu/gpuvirtual.cpp
+7 -11
Просмотреть файл
@@ -1429,11 +1429,9 @@ void VirtualGPU::findIterations(const amd::NDRangeContainer& sizes, const amd::N
// Find the total amount of all groups
groups = sizes.global() / local;
if (dev().settings().partialDispatch_) {
for (uint j = 0; j < dimensions; ++j) {
if ((sizes.global()[j] % local[j]) != 0) {
groups[j]++;
}
for (uint j = 0; j < dimensions; ++j) {
if ((sizes.global()[j] % local[j]) != 0) {
groups[j]++;
}
}
@@ -1481,12 +1479,10 @@ void VirtualGPU::setupIteration(uint iteration, const amd::NDRangeContainer& siz
}
global = groups * local;
if (dev().settings().partialDispatch_) {
for (uint j = 0; j < dimensions; ++j) {
size_t offset = groupOffset[j] * local[j];
if ((offset + global[j]) > sizes.global()[j]) {
global[j] = sizes.global()[j] - offset;
}
for (uint j = 0; j < dimensions; ++j) {
size_t offset = groupOffset[j] * local[j];
if ((offset + global[j]) > sizes.global()[j]) {
global[j] = sizes.global()[j] - offset;
}
}
rocclr/runtime/device/gpu/gslbe/src/rt/GSLDevice.cpp
+1 -1
Просмотреть файл
@@ -502,7 +502,7 @@ CALGSLDevice::SetupAdapter(int32 &asic_id)
//Disable DRMDMA on CFX mode for linux on all GPUs.
#ifdef ATI_OS_LINUX
if ((m_adp->getNumLinkedVPUs() > 1) && !DRMDMA_FOR_LNX_CF)
if (m_adp->getNumLinkedVPUs() > 1)
{
m_canDMA = ATIGL_FALSE;
}
rocclr/runtime/device/pal/palsettings.cpp
-13
Просмотреть файл
@@ -34,7 +34,6 @@ Settings::Settings() {
// Initialize the GPU device default settings
oclVersion_ = OpenCL12;
debugFlags_ = 0;
syncObject_ = GPU_USE_SYNC_OBJECTS;
remoteAlloc_ = REMOTE_ALLOC;
stagedXferRead_ = true;
@@ -44,9 +43,6 @@ Settings::Settings() {
// We will enable staged read/write if we use local memory
disablePersistent_ = false;
// By Default persistent writes will be disabled.
stagingWritePersistent_ = GPU_STAGING_WRITE_PERSISTENT;
imageSupport_ = false;
hwLDSSize_ = 0;
@@ -302,7 +298,6 @@ bool Settings::create(const Pal::DeviceProperties& palProp,
}
supportRA_ = false;
partialDispatch_ = GPU_PARTIAL_DISPATCH;
numMemDependencies_ = GPU_NUM_MEM_DEPENDENCY;
break;
default:
@@ -479,18 +474,10 @@ void Settings::override() {
debugFlags_ = DEBUG_GPU_FLAGS;
}
if (!flagIsDefault(DEBUG_GPU_FLAGS)) {
debugFlags_ = DEBUG_GPU_FLAGS;
}
if (!flagIsDefault(GPU_XFER_BUFFER_SIZE)) {
xferBufSize_ = GPU_XFER_BUFFER_SIZE * Ki;
}
if (!flagIsDefault(GPU_USE_SYNC_OBJECTS)) {
syncObject_ = GPU_USE_SYNC_OBJECTS;
}
if (!flagIsDefault(GPU_NUM_COMPUTE_RINGS)) {
numComputeRings_ = GPU_NUM_COMPUTE_RINGS;
}
rocclr/runtime/device/pal/palsettings.hpp
+1 -3
Просмотреть файл
@@ -48,21 +48,19 @@ class Settings : public device::Settings {
uint use64BitPtr_ : 1; //!< Use 64bit pointers on GPU
uint force32BitOcl20_ : 1; //!< Force 32bit apps to take CLANG/HSAIL path on GPU
uint imageDMA_ : 1; //!< Enable direct image DMA transfers
uint syncObject_ : 1; //!< Enable syncobject
uint viPlus_ : 1; //!< VI and post VI features
uint aiPlus_ : 1; //!< AI and post AI features
uint gfx10Plus_ : 1; //!< gfx10 and post gfx10 features
uint threadTraceEnable_ : 1; //!< Thread trace enable
uint linearPersistentImage_ : 1; //!< Allocates linear images in persistent
uint useSingleScratch_ : 1; //!< Allocates single scratch per device
uint stagingWritePersistent_ : 1; //!< Enables persistent writes
uint svmAtomics_ : 1; //!< SVM device atomics
uint svmFineGrainSystem_ : 1; //!< SVM fine grain system support
uint useDeviceQueue_ : 1; //!< Submit to separate device queue
uint sdamPageFaultWar_ : 1; //!< SDMA page fault workaround
uint rgpSqttWaitIdle_: 1; //!< Wait for idle after SQTT trace
uint rgpSqttForceDisable_: 1; //!< Disables SQTT
uint reserved_ : 10;
uint reserved_ : 12;
};
uint value_;
};
rocclr/runtime/device/rocm/rocsettings.cpp
-7
Просмотреть файл
@@ -17,7 +17,6 @@ Settings::Settings() {
// Set this to true when we drop the flag
doublePrecision_ = ::CL_KHR_FP64;
pollCompletion_ = ENVVAR_HSA_POLL_KERNEL_COMPLETION;
enableLocalMemory_ = HSA_LOCAL_MEMORY_ENABLE;
enableCoarseGrainSVM_ = HSA_ENABLE_COARSE_GRAIN_SVM;
@@ -32,7 +31,6 @@ Settings::Settings() {
maxWorkGroupSize3DZ_ = 4;
kernargPoolSize_ = HSA_KERNARG_POOL_SIZE;
signalPoolSize_ = HSA_SIGNAL_POOL_SIZE;
// Determine if user is requesting Non-Coherent mode
// for system memory. By default system memory is
@@ -43,7 +41,6 @@ Settings::Settings() {
nonCoherentMode = getenv("OPENCL_USE_NC_MEMORY_POLICY");
enableNCMode_ = (nonCoherentMode) ? true : false;
partialDispatch_ = GPU_PARTIAL_DISPATCH;
commandQueues_ = 100; //!< Field value set to maximum number
//!< concurrent Virtual GPUs for ROCm backend
@@ -158,10 +155,6 @@ void Settings::override() {
commandQueues_ = GPU_MAX_COMMAND_QUEUES;
}
if (!flagIsDefault(GPU_IMAGE_DMA)) {
commandQueues_ = GPU_IMAGE_DMA;
}
if (!flagIsDefault(GPU_XFER_BUFFER_SIZE)) {
xferBufSize_ = GPU_XFER_BUFFER_SIZE * Ki;
}
rocclr/runtime/device/rocm/rocsettings.hpp
+1 -3
Просмотреть файл
@@ -20,14 +20,13 @@ class Settings : public device::Settings {
union {
struct {
uint doublePrecision_ : 1; //!< Enables double precision support
uint pollCompletion_ : 1; //!< Enables polling in HSA
uint enableLocalMemory_ : 1; //!< Enable GPUVM memory
uint enableCoarseGrainSVM_ : 1; //!< Enable device memory for coarse grain SVM allocations
uint enableNCMode_ : 1; //!< Enable Non Coherent mode for system memory
uint imageDMA_ : 1; //!< Enable direct image DMA transfers
uint stagedXferRead_ : 1; //!< Uses a staged buffer read
uint stagedXferWrite_ : 1; //!< Uses a staged buffer write
uint reserved_ : 24;
uint reserved_ : 25;
};
uint value_;
};
@@ -48,7 +47,6 @@ class Settings : public device::Settings {
int maxWorkGroupSize3DZ_;
uint kernargPoolSize_;
uint signalPoolSize_;
uint numDeviceEvents_; //!< The number of device events
uint numWaitEvents_; //!< The number of wait events for device enqueue
rocclr/runtime/utils/flags.hpp
-32
Просмотреть файл
@@ -70,8 +70,6 @@ release(cstring, AMD_OCL_SC_LIB, 0, \
"Set shader compiler shared library name or path") \
debug(bool, AMD_OCL_ENABLE_MESSAGE_BOX, false, \
"Enable the error dialog on Windows") \
release(cstring, GPU_PRE_RA_SCHED, "default", \
"Allows setting of alternate pre-RA-sched") \
release(size_t, GPU_PINNED_XFER_SIZE, 16, \
"The pinned buffer size for pinning in read/write transfers") \
release(size_t, GPU_PINNED_MIN_XFER_SIZE, 512, \
@@ -80,16 +78,12 @@ release(size_t, GPU_RESOURCE_CACHE_SIZE, 64, \
"The resource cache size in MB") \
release(size_t, GPU_MAX_SUBALLOC_SIZE, 4096, \
"The maximum size accepted for suballocaitons in KB") \
release(uint, GPU_ASYNC_MEM_COPY, 0, \
"Enables async memory transfers with DRM engine") \
release(bool, GPU_FORCE_64BIT_PTR, 0, \
"Forces 64 bit pointers on GPU") \
release(bool, GPU_FORCE_OCL20_32BIT, 0, \
"Forces 32 bit apps to take CLANG\HSAIL path") \
release(bool, GPU_RAW_TIMESTAMP, 0, \
"Reports GPU raw timestamps in GPU timeline") \
release(bool, GPU_PARTIAL_DISPATCH, true, \
"Enables partial dispatch on GPU") \
release(size_t, GPU_NUM_MEM_DEPENDENCY, 256, \
"Number of memory objects for dependency tracking") \
release(size_t, GPU_XFER_BUFFER_SIZE, 0, \
@@ -102,26 +96,12 @@ release(uint, GPU_NUM_COMPUTE_RINGS, 2, \
"GPU number of compute rings. 0 - disabled, 1 , 2,.. - the number of compute rings") \
release(int, GPU_SELECT_COMPUTE_RINGS_ID, -1, \
"GPU select the compute rings ID -1 - disabled, 0 , 1,.. - the forced compute rings ID for submission") \
release_on_stg(bool, C1X_ATOMICS, !IS_MAINLINE, \
"Runtime will report c1x atomics support") \
release(uint, GPU_WORKLOAD_SPLIT, 22, \
"Workload split size") \
release(bool, GPU_USE_SINGLE_SCRATCH, false, \
"Use single scratch buffer per device instead of per HW ring") \
release_on_stg(cstring, GPU_TARGET_INFO_ARCH, "amdil", \
"Select the GPU TargetInfo arch (amdil|hsail)") \
release(bool, HSA_RUNTIME, 0, \
"1 = Enable HSA Runtime, any other value or absence disables it.") \
release(bool, AMD_OCL_WAIT_COMMAND, false, \
"1 = Enable a wait for every submitted command") \
debug(bool, AMD_OCL_DEBUG_LINKER, false, \
"Enable debug output in linker") \
debug(bool, GPU_SPLIT_LIB, true, \
"Enable splitting GPU 32/64 bit library") \
release(bool, GPU_STAGING_WRITE_PERSISTENT, false, \
"Enable Persistent writes") \
release(bool, DRMDMA_FOR_LNX_CF, false, \
"Enable DRMDMA for Linux CrossFire") \
/* HSAIL is by default, except Linux 32bit, because of known Catalyst 32bit issue */ \
release(bool, GPU_HSAIL_ENABLE, LP64_SWITCH(LINUX_SWITCH(false,true),true), \
"Enable HSAIL on dGPU stack (requires CI+ HW)") \
@@ -135,16 +115,10 @@ release(bool, AMD_THREAD_TRACE_ENABLE, true, \
"Enable thread trace extension") \
release(uint, OPENCL_VERSION, (IS_BRAHMA ? 120 : 200), \
"Force GPU opencl verison") \
release(bool, ENVVAR_HSA_POLL_KERNEL_COMPLETION, false, \
"Determines if Hsa runtime should use polling scheme") \
release(bool, HSA_LOCAL_MEMORY_ENABLE, true, \
"Enable HSA device local memory usage") \
release(uint, HSA_KERNARG_POOL_SIZE, 2 * 1024 * 1024, \
"Kernarg pool size") \
release(uint, HSA_SIGNAL_POOL_SIZE, 16, \
"Signal object pool size") \
release(bool, HSA_ENABLE_ATOMICS_32B, false, \
"1 = Enable SVM atomics in 32 bits (HSA backend-only). Any other value keeps then disabled.") \
release(bool, HSA_ENABLE_COARSE_GRAIN_SVM, true, \
"Enable device memory for coarse grain SVM allocations") \
release(bool, GPU_IFH_MODE, false, \
@@ -179,14 +153,8 @@ release_on_stg(uint, GPU_WAVE_LIMIT_CU_PER_SH, 0, \
"Assume the number of CU per SH for wave limiter") \
release_on_stg(uint, GPU_WAVE_LIMIT_MAX_WAVE, 10, \
"Set maximum waves per SIMD to try for wave limiter") \
release_on_stg(uint, GPU_WAVE_LIMIT_WARMUP, 100, \
"Set warming up kernel execution count for wave limiter") \
release_on_stg(uint, GPU_WAVE_LIMIT_RUN, 20, \
"Set running factor for wave limiter") \
release_on_stg(uint, GPU_WAVE_LIMIT_ABANDON, 105, \
"Set abandon threshold for wave limiter") \
release_on_stg(uint, GPU_WAVE_LIMIT_DSC_THRESH, 10, \
"Set threshold for rejecting discontinuous data") \
release_on_stg(cstring, GPU_WAVE_LIMIT_DUMP, "", \
"File path prefix for dumping wave limiter output") \
release_on_stg(cstring, GPU_WAVE_LIMIT_TRACE, "", \