P4 to Git Change 1701409 by gandryey@gera-w8 on 2018/11/01 17:43:16
SWDEV-79445 - OCL generic changes and code clean-up - Remove obsolete settings - Simplify some logic when runtime checks dimension override in the dispatch critical path Affected files ... ... //depot/stg/opencl/drivers/opencl/api/opencl/amdocl/cl_execute.cpp#29 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/device.cpp#233 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/device.hpp#323 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/devkernel.cpp#9 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpudevice.cpp#599 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpukernel.cpp#333 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuprogram.cpp#246 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuresource.cpp#246 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpusettings.cpp#361 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpusettings.hpp#103 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuvirtual.cpp#425 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gslbe/src/rt/GSLDevice.cpp#184 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palsettings.cpp#60 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palsettings.hpp#20 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/rocsettings.cpp#39 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/rocsettings.hpp#18 edit ... //depot/stg/opencl/drivers/opencl/runtime/utils/flags.hpp#300 edit
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@@ -70,8 +70,6 @@ release(cstring, AMD_OCL_SC_LIB, 0, \
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"Set shader compiler shared library name or path") \
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debug(bool, AMD_OCL_ENABLE_MESSAGE_BOX, false, \
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"Enable the error dialog on Windows") \
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release(cstring, GPU_PRE_RA_SCHED, "default", \
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"Allows setting of alternate pre-RA-sched") \
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release(size_t, GPU_PINNED_XFER_SIZE, 16, \
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"The pinned buffer size for pinning in read/write transfers") \
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release(size_t, GPU_PINNED_MIN_XFER_SIZE, 512, \
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@@ -80,16 +78,12 @@ release(size_t, GPU_RESOURCE_CACHE_SIZE, 64, \
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"The resource cache size in MB") \
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release(size_t, GPU_MAX_SUBALLOC_SIZE, 4096, \
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"The maximum size accepted for suballocaitons in KB") \
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release(uint, GPU_ASYNC_MEM_COPY, 0, \
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"Enables async memory transfers with DRM engine") \
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release(bool, GPU_FORCE_64BIT_PTR, 0, \
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"Forces 64 bit pointers on GPU") \
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release(bool, GPU_FORCE_OCL20_32BIT, 0, \
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"Forces 32 bit apps to take CLANG\HSAIL path") \
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release(bool, GPU_RAW_TIMESTAMP, 0, \
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"Reports GPU raw timestamps in GPU timeline") \
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release(bool, GPU_PARTIAL_DISPATCH, true, \
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"Enables partial dispatch on GPU") \
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release(size_t, GPU_NUM_MEM_DEPENDENCY, 256, \
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"Number of memory objects for dependency tracking") \
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release(size_t, GPU_XFER_BUFFER_SIZE, 0, \
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@@ -102,26 +96,12 @@ release(uint, GPU_NUM_COMPUTE_RINGS, 2, \
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"GPU number of compute rings. 0 - disabled, 1 , 2,.. - the number of compute rings") \
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release(int, GPU_SELECT_COMPUTE_RINGS_ID, -1, \
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"GPU select the compute rings ID -1 - disabled, 0 , 1,.. - the forced compute rings ID for submission") \
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release_on_stg(bool, C1X_ATOMICS, !IS_MAINLINE, \
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"Runtime will report c1x atomics support") \
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release(uint, GPU_WORKLOAD_SPLIT, 22, \
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"Workload split size") \
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release(bool, GPU_USE_SINGLE_SCRATCH, false, \
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"Use single scratch buffer per device instead of per HW ring") \
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release_on_stg(cstring, GPU_TARGET_INFO_ARCH, "amdil", \
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"Select the GPU TargetInfo arch (amdil|hsail)") \
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release(bool, HSA_RUNTIME, 0, \
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"1 = Enable HSA Runtime, any other value or absence disables it.") \
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release(bool, AMD_OCL_WAIT_COMMAND, false, \
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"1 = Enable a wait for every submitted command") \
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debug(bool, AMD_OCL_DEBUG_LINKER, false, \
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"Enable debug output in linker") \
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debug(bool, GPU_SPLIT_LIB, true, \
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"Enable splitting GPU 32/64 bit library") \
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release(bool, GPU_STAGING_WRITE_PERSISTENT, false, \
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"Enable Persistent writes") \
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release(bool, DRMDMA_FOR_LNX_CF, false, \
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"Enable DRMDMA for Linux CrossFire") \
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/* HSAIL is by default, except Linux 32bit, because of known Catalyst 32bit issue */ \
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release(bool, GPU_HSAIL_ENABLE, LP64_SWITCH(LINUX_SWITCH(false,true),true), \
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"Enable HSAIL on dGPU stack (requires CI+ HW)") \
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@@ -135,16 +115,10 @@ release(bool, AMD_THREAD_TRACE_ENABLE, true, \
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"Enable thread trace extension") \
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release(uint, OPENCL_VERSION, (IS_BRAHMA ? 120 : 200), \
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"Force GPU opencl verison") \
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release(bool, ENVVAR_HSA_POLL_KERNEL_COMPLETION, false, \
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"Determines if Hsa runtime should use polling scheme") \
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release(bool, HSA_LOCAL_MEMORY_ENABLE, true, \
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"Enable HSA device local memory usage") \
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release(uint, HSA_KERNARG_POOL_SIZE, 2 * 1024 * 1024, \
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"Kernarg pool size") \
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release(uint, HSA_SIGNAL_POOL_SIZE, 16, \
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"Signal object pool size") \
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release(bool, HSA_ENABLE_ATOMICS_32B, false, \
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"1 = Enable SVM atomics in 32 bits (HSA backend-only). Any other value keeps then disabled.") \
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release(bool, HSA_ENABLE_COARSE_GRAIN_SVM, true, \
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"Enable device memory for coarse grain SVM allocations") \
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release(bool, GPU_IFH_MODE, false, \
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@@ -179,14 +153,8 @@ release_on_stg(uint, GPU_WAVE_LIMIT_CU_PER_SH, 0, \
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"Assume the number of CU per SH for wave limiter") \
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release_on_stg(uint, GPU_WAVE_LIMIT_MAX_WAVE, 10, \
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"Set maximum waves per SIMD to try for wave limiter") \
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release_on_stg(uint, GPU_WAVE_LIMIT_WARMUP, 100, \
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"Set warming up kernel execution count for wave limiter") \
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release_on_stg(uint, GPU_WAVE_LIMIT_RUN, 20, \
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"Set running factor for wave limiter") \
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release_on_stg(uint, GPU_WAVE_LIMIT_ABANDON, 105, \
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"Set abandon threshold for wave limiter") \
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release_on_stg(uint, GPU_WAVE_LIMIT_DSC_THRESH, 10, \
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"Set threshold for rejecting discontinuous data") \
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release_on_stg(cstring, GPU_WAVE_LIMIT_DUMP, "", \
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"File path prefix for dumping wave limiter output") \
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release_on_stg(cstring, GPU_WAVE_LIMIT_TRACE, "", \
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