SWDEV-417091 - Disable GWS Init for PAL/Windows side.

Change-Id: Ib6295f063daa835c1f33f21f50c083241a9026ff


[ROCm/clr commit: 931431fc38]

projects/clr/rocclr/device/device.cpp

@@ -1055,8 +1055,9 @@ Settings::Settings() : value_(0) {
     if (flagIsDefault(GPU_SINGLE_ALLOC_PERCENT)) {
       GPU_SINGLE_ALLOC_PERCENT = 100;
     }
-
   }
+
+  gwsInitSupported_ = true;
 }
 
 void Memory::saveMapInfo(const void* mapAddress, const amd::Coord3D origin,

projects/clr/rocclr/device/pal/palblit.cpp

@@ -2601,26 +2601,31 @@ void KernelBlitManager::writeRawData(device::Memory& memory, size_t size, const
 }
 
 bool KernelBlitManager::RunGwsInit(
-    uint32_t value) const {
-    amd::ScopedLock k(lockXferOps_);
+  uint32_t value) const {
+  amd::ScopedLock k(lockXferOps_);
 
-    size_t globalWorkOffset[1] = { 0 };
-    size_t globalWorkSize[1] = { 1 };
-    size_t localWorkSize[1] = { 1 };
+  if (dev().settings().gwsInitSupported_ == false) {
+    LogError("GWS Init is not supported on this target");
+    return false;
+  }
 
-    // Program kernels arguments
-    setArgument(kernels_[GwsInit], 0, sizeof(uint32_t), &value);
+  size_t globalWorkOffset[1] = { 0 };
+  size_t globalWorkSize[1] = { 1 };
+  size_t localWorkSize[1] = { 1 };
 
-    // Create ND range object for the kernel's execution
-    amd::NDRangeContainer ndrange(1, globalWorkOffset, globalWorkSize, localWorkSize);
+  // Program kernels arguments
+  setArgument(kernels_[GwsInit], 0, sizeof(uint32_t), &value);
 
-    // Execute the blit
-    address parameters = kernels_[GwsInit]->parameters().values();
-    bool result = gpu().submitKernelInternal(ndrange, *kernels_[GwsInit], parameters);
+  // Create ND range object for the kernel's execution
+  amd::NDRangeContainer ndrange(1, globalWorkOffset, globalWorkSize, localWorkSize);
 
-    synchronize();
+  // Execute the blit
+  address parameters = kernels_[GwsInit]->parameters().values();
+  bool result = gpu().submitKernelInternal(ndrange, *kernels_[GwsInit], parameters);
 
-    return result;
+  synchronize();
+
+  return result;
 }
 
 amd::Memory* DmaBlitManager::pinHostMemory(const void* hostMem, size_t pinSize,

projects/clr/rocclr/device/pal/paldevice.cpp

@@ -151,6 +151,7 @@ static std::tuple<Pal::GfxIpLevel, Pal::AsicRevision, const char*> findPal(uint3
 
 namespace device {
 extern const char* HipExtraSourceCode;
+extern const char* HipExtraSourceCodeNoGWS;
 }
 
 bool PalDeviceLoad() {
@@ -2663,7 +2664,11 @@ bool Device::createBlitProgram() {
   std::string extraBlits;
   std::string ocl20;
   if (amd::IS_HIP) {
-    extraBlits = device::HipExtraSourceCode;
+    if (settings().gwsInitSupported_) {
+      extraBlits = device::HipExtraSourceCode;
+    } else {
+      extraBlits = device::HipExtraSourceCodeNoGWS;
+    }
   } else {
     if (settings().oclVersion_ >= OpenCL20) {
       extraBlits = iDev()->GetDispatchKernelSource();

projects/clr/rocclr/device/pal/palsettings.cpp

@@ -177,6 +177,7 @@ bool Settings::create(const Pal::DeviceProperties& palProp,
     case Pal::AsicRevision::Navi33:
     case Pal::AsicRevision::Navi32:
     case Pal::AsicRevision::Navi31:
+      gwsInitSupported_ = false;
     // Fall through for Navi2x ...
     case Pal::AsicRevision::Phoenix1:
     case Pal::AsicRevision::Phoenix2:

projects/clr/rocclr/device/rocm/rocsettings.cpp

@@ -94,7 +94,6 @@ Settings::Settings() {
   // Use coarse grain system memory for kernel arguments by default (to keep GPU cache)
   fgs_kernel_arg_ = false;
   barrier_value_packet_ = false;
-
   kernel_arg_impl_ = KernelArgImpl::HostKernelArgs;
   gwsInitSupported_ = true;
   limit_blit_wg_ = 16;