Initial GFX12 changes.

Add target gfx1200 to several files.
Add cases for GFX12 in a few switch statements.

Signed-off-by: David Belanger <david.belanger@amd.com>
Change-Id: Ib90032f5b9d5a3306060f13a43d970108a1399df
Signed-off-by: Chris Freehill <cfreehil@amd.com>
This commit is contained in:
David Belanger
2023-06-15 16:28:41 -04:00
committed by Chris Freehill
parent 696d8fae9e
commit 2f14acd9c1
7 changed files with 10 additions and 3 deletions
+1 -1
View File
@@ -85,7 +85,7 @@ set (CPACK_RPM_PACKAGE_REQUIRES "rocm-core,hsa-rocr")
set(DEFAULT_TARGETS "gfx700;gfx701;gfx702;gfx801;gfx802;gfx803;gfx805;gfx810"
"gfx900;gfx902;gfx904;gfx906;gfx908;gfx909;gfx90a;gfx90c;gfx940;gfx941;gfx942"
"gfx1010;gfx1011;gfx1012;gfx1013;gfx1030;gfx1031;gfx1032;gfx1033;gfx1034;gfx1035;gfx1036"
"gfx1100;gfx1101;gfx1102;gfx1103;gfx1150;gfx1151")
"gfx1100;gfx1101;gfx1102;gfx1103;gfx1150;gfx1151;gfx1200")
#
# Currently support for Windows platform is not present
@@ -1773,6 +1773,7 @@ void AqlQueue::FillComputeTmpRingSize_Gfx11() {
// that enable kernel access scratch memory
void AqlQueue::InitScratchSRD() {
switch (agent_->isa()->GetMajorVersion()) {
case 12:
case 11:
FillBufRsrcWord0();
FillBufRsrcWord1_Gfx11();
@@ -709,6 +709,7 @@ core::Blit* GpuAgent::CreateBlitSdma(bool use_xgmi) {
copy_size_overrides[1];
break;
case 11:
case 12:
sdma = new BlitSdmaV5();
copy_size_override = copy_size_overrides[1];
break;
@@ -2165,7 +2166,7 @@ void GpuAgent::InvalidateCodeCaches() {
// Microcode is handling code cache invalidation.
return;
}
} else if (isa_->GetMajorVersion() > 11) {
} else if (isa_->GetMajorVersion() > 12) {
assert(false && "Code cache invalidation not implemented for this agent");
}
+1
View File
@@ -349,6 +349,7 @@ constexpr size_t hsa_name_size = 63;
ISAREG_ENTRY_GEN("gfx1103", 11, 0, 3, unsupported, unsupported, 32)
ISAREG_ENTRY_GEN("gfx1150", 11, 5, 0, unsupported, unsupported, 32)
ISAREG_ENTRY_GEN("gfx1151", 11, 5, 1, unsupported, unsupported, 32)
ISAREG_ENTRY_GEN("gfx1200", 12, 0, 0, unsupported, unsupported, 32)
#undef ISAREG_ENTRY_GEN
return supported_isas;
}
@@ -105,6 +105,7 @@ extern uint8_t ocl_blit_object_gfx1102[];
extern uint8_t ocl_blit_object_gfx1103[];
extern uint8_t ocl_blit_object_gfx1150[];
extern uint8_t ocl_blit_object_gfx1151[];
extern uint8_t ocl_blit_object_gfx1200[];
// Arguments inserted by OCL compiler, all zero here.
struct OCLHiddenArgs {
@@ -1052,6 +1053,8 @@ hsa_status_t BlitKernel::GetPatchedBlitObject(const char* agent_name,
*blit_code_object = ocl_blit_object_gfx1150;
} else if (sname == "gfx1151") {
*blit_code_object = ocl_blit_object_gfx1151;
} else if (sname == "gfx1200") {
*blit_code_object = ocl_blit_object_gfx1200;
} else {
return HSA_STATUS_ERROR_INVALID_ISA_NAME;
}
@@ -50,7 +50,7 @@ if (NOT DEFINED TARGET_DEVICES)
set (TARGET_DEVICES "gfx700;gfx701;gfx702;gfx801;gfx802;gfx803;gfx805;gfx810"
"gfx900;gfx902;gfx904;gfx906;gfx908;gfx909;gfx90a;gfx90c;gfx940;gfx941;gfx942"
"gfx1010;gfx1011;gfx1012;gfx1013;gfx1030;gfx1031;gfx1032;gfx1033;gfx1034;gfx1035;gfx1036"
"gfx1100;gfx1101;gfx1102;gfx1103;gfx1150;gfx1151")
"gfx1100;gfx1101;gfx1102;gfx1103;gfx1150;gfx1151;gfx1200")
endif()
set( TARGET_DEVICES ${TARGET_DEVICES} CACHE STRING "Build targets" FORCE )
@@ -608,6 +608,7 @@ namespace code {
case ELF::EF_AMDGPU_MACH_AMDGCN_GFX10_1_GENERIC: MI.Name = "gfx10-1-generic"; MI.XnackSupported = true; MI.SrameccSupported = false; break;
case ELF::EF_AMDGPU_MACH_AMDGCN_GFX10_3_GENERIC: MI.Name = "gfx10-3-generic"; MI.XnackSupported = false; MI.SrameccSupported = false; break;
case ELF::EF_AMDGPU_MACH_AMDGCN_GFX11_GENERIC: MI.Name = "gfx11-generic"; MI.XnackSupported = false; MI.SrameccSupported = false; break;
case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1200: MI.Name = "gfx1200"; MI.XnackSupported = false; MI.SrameccSupported = false; break;
default: return false;
}
return true;