Add RISC-V support

Patch provided by user Xeonacid via github:
https://github.com/RadeonOpenCompute/ROCR-Runtime/pull/172/

Change-Id: I5f9086b536383093e7995b9cfdc19dab213f0265


[ROCm/ROCR-Runtime commit: 251601b20b]

projects/rocr-runtime/runtime/hsa-runtime/inc/hsa.h

@@ -80,7 +80,7 @@
 // Try to detect CPU endianness
 #if !defined(LITTLEENDIAN_CPU) && !defined(BIGENDIAN_CPU)
 #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || \
-    defined(_M_X64) || defined(__loongarch64)
+    defined(_M_X64) || defined(__loongarch64) || defined(__riscv)
 #define LITTLEENDIAN_CPU
 #endif
 #endif