SWDEV-436533 - Cache Info Struct Update

Signed-off-by: Maisam Arif <maisarif@amd.com>
Change-Id: Ic640fa657cdcc32d7b00ff78fc9452ec7e05dd07


[ROCm/amdsmi commit: 88192d8b6b]

projects/amdsmi/amdsmi_cli/README.md

@@ -656,25 +656,25 @@ VRAM:
     VRAM_VENDOR: HYNIX
     VRAM_SIZE_MB: 96432 MB
 CACHE:
-    CACHE 0:
+    CACHE_0:
         CACHE_PROPERTIES: DATA_CACHE, SIMD_CACHE
         CACHE_SIZE: 32 KB
         CACHE_LEVEL: 1
         MAX_NUM_CU_SHARED: 2
         NUM_CACHE_INSTANCE: 464
-    CACHE 1:
+    CACHE_1:
         CACHE_PROPERTIES: INST_CACHE, SIMD_CACHE
         CACHE_SIZE: 64 KB
         CACHE_LEVEL: 1
         MAX_NUM_CU_SHARED: 2
         NUM_CACHE_INSTANCE: 160
-    CACHE 2:
+    CACHE_2:
         CACHE_PROPERTIES: DATA_CACHE, SIMD_CACHE
         CACHE_SIZE: 32768 KB
         CACHE_LEVEL: 2
         MAX_NUM_CU_SHARED: 304
         NUM_CACHE_INSTANCE: 1
-    CACHE 3:
+    CACHE_3:
         CACHE_PROPERTIES: DATA_CACHE, SIMD_CACHE
         CACHE_SIZE: 262144 KB
         CACHE_LEVEL: 3
@@ -768,25 +768,25 @@ VRAM:
     VRAM_SIZE_MB: 96432 MB
 CACHE:
  CACHE:
-    CACHE 0:
+    CACHE_0:
         CACHE_PROPERTIES: DATA_CACHE, SIMD_CACHE
         CACHE_SIZE: 32 KB
         CACHE_LEVEL: 1
         MAX_NUM_CU_SHARED: 2
         NUM_CACHE_INSTANCE: 464
-    CACHE 1:
+    CACHE_1:
         CACHE_PROPERTIES: INST_CACHE, SIMD_CACHE
         CACHE_SIZE: 64 KB
         CACHE_LEVEL: 1
         MAX_NUM_CU_SHARED: 2
         NUM_CACHE_INSTANCE: 160
-    CACHE 2:
+    CACHE_2:
         CACHE_PROPERTIES: DATA_CACHE, SIMD_CACHE
         CACHE_SIZE: 32768 KB
         CACHE_LEVEL: 2
         MAX_NUM_CU_SHARED: 304
         NUM_CACHE_INSTANCE: 1
-    CACHE 3:
+    CACHE_3:
         CACHE_PROPERTIES: DATA_CACHE, SIMD_CACHE
         CACHE_SIZE: 262144 KB
         CACHE_LEVEL: 3
@@ -879,25 +879,25 @@ VRAM:
     VRAM_SIZE_MB: 96432 MB
 CACHE:
  CACHE:
-    CACHE 0:
+    CACHE_0:
         CACHE_PROPERTIES: DATA_CACHE, SIMD_CACHE
         CACHE_SIZE: 32 KB
         CACHE_LEVEL: 1
         MAX_NUM_CU_SHARED: 2
         NUM_CACHE_INSTANCE: 464
-    CACHE 1:
+    CACHE_1:
         CACHE_PROPERTIES: INST_CACHE, SIMD_CACHE
         CACHE_SIZE: 64 KB
         CACHE_LEVEL: 1
         MAX_NUM_CU_SHARED: 2
         NUM_CACHE_INSTANCE: 160
-    CACHE 2:
+    CACHE_2:
         CACHE_PROPERTIES: DATA_CACHE, SIMD_CACHE
         CACHE_SIZE: 32768 KB
         CACHE_LEVEL: 2
         MAX_NUM_CU_SHARED: 304
         NUM_CACHE_INSTANCE: 1
-    CACHE 3:
+    CACHE_3:
         CACHE_PROPERTIES: INST_CACHE, SIMD_CACHE
         CACHE_SIZE: 262144 KB
         CACHE_LEVEL: 3
@@ -989,27 +989,27 @@ VRAM:
     VRAM_VENDOR: HYNIX
     VRAM_SIZE_MB: 96432 MB
 CACHE:
-    CACHE 0:
+    CACHE_0:
 CACHE:
-    CACHE 0:
+    CACHE_0:
         CACHE_PROPERTIES: INST_CACHE, SIMD_CACHE
         CACHE_SIZE: 32 KB
         CACHE_LEVEL: 1
         MAX_NUM_CU_SHARED: 2
         NUM_CACHE_INSTANCE: 464
-    CACHE 1:
+    CACHE_1:
         CACHE_PROPERTIES: INST_CACHE, SIMD_CACHE
         CACHE_SIZE: 64 KB
         CACHE_LEVEL: 1
         MAX_NUM_CU_SHARED: 2
         NUM_CACHE_INSTANCE: 160
-    CACHE 2:
+    CACHE_2:
         CACHE_PROPERTIES: DATA_CACHE, SIMD_CACHE
         CACHE_SIZE: 32768 KB
         CACHE_LEVEL: 2
         MAX_NUM_CU_SHARED: 304
         NUM_CACHE_INSTANCE: 1
-    CACHE 3:
+    CACHE_3:
         CACHE_PROPERTIES: DATA_CACHE, SIMD_CACHE
         CACHE_SIZE: 262144 KB
         CACHE_LEVEL: 3

projects/amdsmi/example/amd_smi_drm_example.cc

@@ -314,8 +314,8 @@ int main() {
             for (unsigned int i = 0 ; i < cache_info.num_cache_types; i++) {
                 printf("\tCache Level: %d, Cache Size: %d KB, Cache type: 0x%x\n",
                     cache_info.cache[i].cache_level,
-                    cache_info.cache[i].cache_size_kb,
-                    cache_info.cache[i].flags);
+                    cache_info.cache[i].cache_size,
+                    cache_info.cache[i].properties);
                 printf("\tMax number CU shared: %d, Number of instances: %d\n",
                     cache_info.cache[i].max_num_cu_shared,
                     cache_info.cache[i].num_cache_instance);

projects/amdsmi/include/amd_smi/amdsmi.h

@@ -538,22 +538,22 @@ typedef struct {
 } amdsmi_vbios_info_t;
 
 /**
- * @brief cache flags
+ * @brief cache properties
  */
 typedef enum {
-  CACHE_FLAGS_ENABLED = 0x00000001,
-  CACHE_FLAGS_DATA_CACHE = 0x00000002,
-  CACHE_FLAGS_INST_CACHE = 0x00000004,
-  CACHE_FLAGS_CPU_CACHE = 0x00000008,
-  CACHE_FLAGS_SIMD_CACHE = 0x00000010,
-} amdsmi_cache_flags_type_t;
+  CACHE_PROPERTIES_ENABLED = 0x00000001,
+  CACHE_PROPERTIES_DATA_CACHE = 0x00000002,
+  CACHE_PROPERTIES_INST_CACHE = 0x00000004,
+  CACHE_PROPERTIES_CPU_CACHE = 0x00000008,
+  CACHE_PROPERTIES_SIMD_CACHE = 0x00000010,
+} amdsmi_cache_properties_type_t;
 
 typedef struct {
   uint32_t num_cache_types;
   struct cache_ {
-    uint32_t cache_size_kb; /* In KB */
+    uint32_t cache_size; /* In KB */
     uint32_t cache_level;
-    uint32_t flags;  // amdsmi_cache_flags_type_t which is a bitmask
+    uint32_t properties;  // amdsmi_cache_properties_type_t which is a bitmask
     uint32_t max_num_cu_shared;  /* Indicates how many Compute Units share this cache instance */
     uint32_t num_cache_instance;  /* total number of instance of this cache type */
     uint32_t reserved[3];

projects/amdsmi/py-interface/README.md

@@ -472,11 +472,26 @@ Input parameters:
 * `processor_handle` device which to query
 
 Output: Dictionary of Dictionaries containing cache information
+Schema: { cache_index:
+            {
+            cache_properties:
+                {
+                    "type": "array",
+                    "items": {
+                         "type": "string"
+                    }
+                },
+            cache_size: {"type" : "number"},
+            cache_level: {"type" : "number"},
+            max_num_cu_shared: {"type" : "number"},
+            num_cache_instance: {"type" : "number"}
+            }
+        }
 
 Field | Description
 ---|---
-`cache_index` | cache index - up to 10 caches will be available
-`cache_flags` | list of up to 4 cache property type strings. Ex. data ("DATA_CACHE"), instruction ("INST_CACHE"), CPU ("CPU_CACHE"), or SIMD ("SIMD_CACHE").
+`cache_index` | cache index is a string of format "cache_#" up to 10 caches will be available
+`cache_properties` | list of up to 4 cache property type strings. Ex. data ("DATA_CACHE"), instruction ("INST_CACHE"), CPU ("CPU_CACHE"), or SIMD ("SIMD_CACHE").
 `cache_size` | size of cache in KB
 `cache_level` | level of cache
 `max_num_cu_shared` |  max number of compute units shared
@@ -2091,7 +2106,7 @@ Output: Dictionary with fields
 `average_umc_activity` | Average umc (Universal Memory Controller) activity | %
 `average_mm_activity` | Average mm (multimedia) engine activity | %
 `average_socket_power` | Average socket power | W
-`energy_accumulator` | Energy accumulated with a 15.3 uJ resolution over 1ns | uJ 
+`energy_accumulator` | Energy accumulated with a 15.3 uJ resolution over 1ns | uJ
 `system_clock_counter` | System clock counter | ns
 `average_gfxclk_frequency` | Average gfx clock frequency | MHz
 `average_socclk_frequency` | Average soc clock frequency | MHz
@@ -2119,7 +2134,7 @@ Output: Dictionary with fields
 `voltage_soc` | soc voltage | mV
 `voltage_gfx` | gfx voltage | mV
 `voltage_mem` | mem voltage | mV
-`indep_throttle_status` | ASIC independent throttle status (see drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h for bit flags) | 
+`indep_throttle_status` | ASIC independent throttle status (see drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h for bit flags) |
 `current_socket_power` | Current socket power (also known as instant socket power) | W
 `vcn_activity` | List of VCN encode/decode engine utilization per AID | %
 `gfxclk_lock_status` | Clock lock status. Each bit corresponds to clock instance. |

projects/amdsmi/py-interface/amdsmi_interface.py

@@ -1619,30 +1619,32 @@ def amdsmi_get_gpu_cache_info(
 
     cache_info_dict = {}
     for cache_index in range(cache_info.num_cache_types):
+        # Put cache_properties at the start of the dictionary for readability
         cache_dict = {
             "cache_properties": [],
-            "cache_size": cache_info.cache[cache_index].cache_size_kb,
+            "cache_size": cache_info.cache[cache_index].cache_size,
             "cache_level": cache_info.cache[cache_index].cache_level,
             "max_num_cu_shared": cache_info.cache[cache_index].max_num_cu_shared,
             "num_cache_instance": cache_info.cache[cache_index].num_cache_instance
         }
 
-        cache_flags = cache_info.cache[cache_index].flags
-        data_cache = cache_flags & amdsmi_wrapper.CACHE_FLAGS_DATA_CACHE
-        inst_cache = cache_flags & amdsmi_wrapper.CACHE_FLAGS_INST_CACHE
-        cpu_cache = cache_flags & amdsmi_wrapper.CACHE_FLAGS_CPU_CACHE
-        simd_cache = cache_flags & amdsmi_wrapper.CACHE_FLAGS_SIMD_CACHE
+        # Check against cache properties bitmask
+        cache_properties = cache_info.cache[cache_index].properties
+        data_cache = cache_properties & amdsmi_wrapper.CACHE_PROPERTIES_DATA_CACHE
+        inst_cache = cache_properties & amdsmi_wrapper.CACHE_PROPERTIES_INST_CACHE
+        cpu_cache = cache_properties & amdsmi_wrapper.CACHE_PROPERTIES_CPU_CACHE
+        simd_cache = cache_properties & amdsmi_wrapper.CACHE_PROPERTIES_SIMD_CACHE
 
-        cache_flags_status = [data_cache, inst_cache, cpu_cache, simd_cache]
-        cache_flag_list = []
-        for cache_flag in cache_flags_status:
-            if cache_flag:
-                flag_name = amdsmi_wrapper.amdsmi_cache_flags_type_t__enumvalues[cache_flag]
-                flag_name = flag_name.replace("CACHE_FLAGS_", "")
-                cache_flag_list.append(flag_name)
+        cache_properties_status = [data_cache, inst_cache, cpu_cache, simd_cache]
+        cache_property_list = []
+        for cache_property in cache_properties_status:
+            if cache_property:
+                property_name = amdsmi_wrapper.amdsmi_cache_properties_type_t__enumvalues[cache_property]
+                property_name = property_name.replace("CACHE_PROPERTIES_", "")
+                cache_property_list.append(property_name)
 
-        cache_dict["cache_properties"] = cache_flag_list
-        cache_info_dict[f"cache {cache_index}"] = cache_dict
+        cache_dict["cache_properties"] = cache_property_list
+        cache_info_dict[f"cache_{cache_index}"] = cache_dict
 
     if not cache_info_dict:
         raise AmdSmiLibraryException(amdsmi_wrapper.AMDSMI_STATUS_NO_DATA)

projects/amdsmi/py-interface/amdsmi_wrapper.py

@@ -813,20 +813,20 @@ struct_amdsmi_vbios_info_t._fields_ = [
 
 amdsmi_vbios_info_t = struct_amdsmi_vbios_info_t
 
-# values for enumeration 'amdsmi_cache_flags_type_t'
-amdsmi_cache_flags_type_t__enumvalues = {
-    1: 'CACHE_FLAGS_ENABLED',
-    2: 'CACHE_FLAGS_DATA_CACHE',
-    4: 'CACHE_FLAGS_INST_CACHE',
-    8: 'CACHE_FLAGS_CPU_CACHE',
-    16: 'CACHE_FLAGS_SIMD_CACHE',
+# values for enumeration 'amdsmi_cache_properties_type_t'
+amdsmi_cache_properties_type_t__enumvalues = {
+    1: 'CACHE_PROPERTIES_ENABLED',
+    2: 'CACHE_PROPERTIES_DATA_CACHE',
+    4: 'CACHE_PROPERTIES_INST_CACHE',
+    8: 'CACHE_PROPERTIES_CPU_CACHE',
+    16: 'CACHE_PROPERTIES_SIMD_CACHE',
 }
-CACHE_FLAGS_ENABLED = 1
-CACHE_FLAGS_DATA_CACHE = 2
-CACHE_FLAGS_INST_CACHE = 4
-CACHE_FLAGS_CPU_CACHE = 8
-CACHE_FLAGS_SIMD_CACHE = 16
-amdsmi_cache_flags_type_t = ctypes.c_uint32 # enum
+CACHE_PROPERTIES_ENABLED = 1
+CACHE_PROPERTIES_DATA_CACHE = 2
+CACHE_PROPERTIES_INST_CACHE = 4
+CACHE_PROPERTIES_CPU_CACHE = 8
+CACHE_PROPERTIES_SIMD_CACHE = 16
+amdsmi_cache_properties_type_t = ctypes.c_uint32 # enum
 class struct_amdsmi_gpu_cache_info_t(Structure):
     pass
 
@@ -835,9 +835,9 @@ class struct_cache_(Structure):
 
 struct_cache_._pack_ = 1 # source:False
 struct_cache_._fields_ = [
-    ('cache_size_kb', ctypes.c_uint32),
+    ('cache_size', ctypes.c_uint32),
     ('cache_level', ctypes.c_uint32),
-    ('flags', ctypes.c_uint32),
+    ('properties', ctypes.c_uint32),
     ('max_num_cu_shared', ctypes.c_uint32),
     ('num_cache_instance', ctypes.c_uint32),
     ('reserved', ctypes.c_uint32 * 3),
@@ -2415,9 +2415,9 @@ __all__ = \
     'AMDSMI_VRAM_VENDOR__WINBOND', 'AMDSMI_XGMI_STATUS_ERROR',
     'AMDSMI_XGMI_STATUS_MULTIPLE_ERRORS',
     'AMDSMI_XGMI_STATUS_NO_ERRORS', 'AMD_APU', 'AMD_CPU',
-    'AMD_CPU_CORE', 'AMD_GPU', 'CACHE_FLAGS_CPU_CACHE',
-    'CACHE_FLAGS_DATA_CACHE', 'CACHE_FLAGS_ENABLED',
-    'CACHE_FLAGS_INST_CACHE', 'CACHE_FLAGS_SIMD_CACHE',
+    'AMD_CPU_CORE', 'AMD_GPU', 'CACHE_PROPERTIES_CPU_CACHE',
+    'CACHE_PROPERTIES_DATA_CACHE', 'CACHE_PROPERTIES_ENABLED',
+    'CACHE_PROPERTIES_INST_CACHE', 'CACHE_PROPERTIES_SIMD_CACHE',
     'CLK_TYPE_DCEF', 'CLK_TYPE_DCLK0', 'CLK_TYPE_DCLK1',
     'CLK_TYPE_DF', 'CLK_TYPE_FIRST', 'CLK_TYPE_GFX', 'CLK_TYPE_MEM',
     'CLK_TYPE_PCIE', 'CLK_TYPE_SOC', 'CLK_TYPE_SYS', 'CLK_TYPE_VCLK0',
@@ -2465,7 +2465,7 @@ __all__ = \
     'VRAM_TYPE_GDDR6', 'VRAM_TYPE_HBM', 'VRAM_TYPE_UNKNOWN',
     'VRAM_TYPE__MAX', 'WR_BW0', 'amd_metrics_table_header_t',
     'amdsmi_asic_info_t', 'amdsmi_bdf_t', 'amdsmi_bit_field_t',
-    'amdsmi_board_info_t', 'amdsmi_cache_flags_type_t',
+    'amdsmi_board_info_t', 'amdsmi_cache_properties_type_t',
     'amdsmi_card_form_factor_t', 'amdsmi_clk_info_t',
     'amdsmi_clk_type_t', 'amdsmi_compute_partition_type_t',
     'amdsmi_container_types_t', 'amdsmi_counter_command_t',

projects/amdsmi/src/amd_smi/amd_smi.cc

@@ -445,23 +445,22 @@ amdsmi_status_t amdsmi_get_gpu_cache_info(
 
     info->num_cache_types = rsmi_info.num_cache_types;
     for (unsigned int i =0; i < rsmi_info.num_cache_types; i++) {
-        info->cache[i].cache_size_kb = rsmi_info.cache[i].cache_size_kb;
+        info->cache[i].cache_size = rsmi_info.cache[i].cache_size_kb;
         info->cache[i].cache_level = rsmi_info.cache[i].cache_level;
         info->cache[i].max_num_cu_shared = rsmi_info.cache[i].max_num_cu_shared;
         info->cache[i].num_cache_instance = rsmi_info.cache[i].num_cache_instance;
         // convert from sysfs type to CRAT type(HSA Cache Affinity type)
-        info->cache[i].flags = 0;
+        info->cache[i].properties = 0;
         if (rsmi_info.cache[i].flags & HSA_CACHE_TYPE_DATA)
-            info->cache[i].flags |= CACHE_FLAGS_DATA_CACHE;
+            info->cache[i].properties |= CACHE_PROPERTIES_DATA_CACHE;
         if (rsmi_info.cache[i].flags & HSA_CACHE_TYPE_INSTRUCTION)
-            info->cache[i].flags |= CACHE_FLAGS_INST_CACHE;
+            info->cache[i].properties |= CACHE_PROPERTIES_INST_CACHE;
         if (rsmi_info.cache[i].flags & HSA_CACHE_TYPE_CPU)
-            info->cache[i].flags |= CACHE_FLAGS_CPU_CACHE;
+            info->cache[i].properties |= CACHE_PROPERTIES_CPU_CACHE;
         if (rsmi_info.cache[i].flags & HSA_CACHE_TYPE_HSACU)
-            info->cache[i].flags |= CACHE_FLAGS_SIMD_CACHE;
+            info->cache[i].properties |= CACHE_PROPERTIES_SIMD_CACHE;
     }
 
-
     return AMDSMI_STATUS_SUCCESS;
 }