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rocr: Remove scratch_backing_memory_byte_size

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scratch_backing_memory_byte_size was originally removed, and then put
back in 02b38d0614. This was because it
was used by rocgdb. rocgdb code has been updated to not use this field.
Bumped _amdgpu_r_debug for the ABI change.
This commit is contained in:
David Yat Sin
2025-05-21 17:42:48 +00:00
committed by Yat Sin, David
parent 17b8f9b24d
commit 3c0af843e3
3 changed files with 4 additions and 13 deletions
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runtime/hsa-runtime/core/runtime/amd_aql_queue.cpp
-9
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@@ -1841,15 +1841,6 @@ void AqlQueue::InitScratchSRD() {
amd_queue_.alt_scratch_backing_memory_location = queue_scratch_.alt_queue_process_offset;
const auto& agent_props = agent_->properties();
const uint32_t num_xcc = agent_props.NumXcc;
// FIXME: amd_queue_.scratch_backing_memory_byte_size is not used by CP, but it
// is used by the debugger. Putting back the scratch_backing_memory_byte_size
// field. But we need to find a location for alt_scratch_backing_memory_byte_size
// report size per XCC
amd_queue_.scratch_backing_memory_byte_size = queue_scratch_.main_size / num_xcc;
//amd_queue_.alt_scratch_backing_memory_byte_size = queue_scratch_.alt_size / num_xcc;
// For backwards compatibility this field records the per-lane scratch
// for a 64 lane wavefront. If scratch was allocated for 32 lane waves
runtime/hsa-runtime/core/runtime/runtime.cpp
+1 -1
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@@ -2012,7 +2012,7 @@ Runtime::Runtime()
asyncExceptions_.monitor_exceptions = true;
g_use_interrupt_wait = true;
g_use_mwaitx = true;
::_amdgpu_r_debug = {10,
::_amdgpu_r_debug = {11,
nullptr,
reinterpret_cast<uintptr_t>(
&_loader_debug_state),
runtime/hsa-runtime/inc/amd_hsa_queue.h
+3 -3
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@@ -93,12 +93,12 @@ typedef struct AMD_QUEUE_ALIGN amd_queue_s {
uint32_t compute_tmpring_size;
uint32_t scratch_resource_descriptor[4];
uint64_t scratch_backing_memory_location;
uint64_t scratch_backing_memory_byte_size;
uint32_t reserved3[2];
uint32_t scratch_wave64_lane_byte_size;
amd_queue_properties32_t queue_properties;
uint32_t reserved3[2];
uint32_t reserved4[2];
hsa_signal_t queue_inactive_signal;
uint32_t reserved4[14];
uint32_t reserved5[14];
} amd_queue_t;
/*