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P4 to Git Change 1273450 by smekhano@stas-rampitec-hsa on 2016/05/26 14:04:49

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SWDEV-93545 - HSA HLC: target option interface between complib and BE and denorm control refactoring

	Global variables and associated options to control target GPU for optimizations and fp32 denorm support are removed.
	Instead standard llvm -mcpu=<cpu> is used to pass chip family name and fp32 denorm is turned into a subtarget feature.
	Subtarget feature can be set for llc as standard -mattr=+fp32-denormals and corresponding code to pass feature string
	to the BE is added to the compiler lib, mimicing what we used to have for AMDIL.

	Device name HSAIL metadata will now reflect an actual GPU family passed to the HSAIL BE instead of "generic".

	Denorm support can be switched on as a feature bit in the target mapping. It is on starting from VI. However, just
	switching this bit for a family will not produce denorm supporting code. The option -cl-denorms-are-zero can be used
	to override this and runtime passes it for configs where CL_FP_DENORM is not reported.

	Currently CL_FP_DENORM is not reported for any device, however it can be changed with AMD_GPU_FORCE_SINGLE_FP_DENORM
	environment variable. If set it will be honored only starting from VI as set in the target mapping.

	Implemented isFMAFasterThanFMulAndFAdd to handle use of v_fma_f32 on GFX9 instead of a direct chip family check.

	Testing: smoke, precheckin
	Reviewed by Evgeny Mankov

Affected files ...

... //depot/stg/opencl/drivers/opencl/compiler/lib/backends/common/codegen.cpp#70 edit
... //depot/stg/opencl/drivers/opencl/compiler/lib/backends/common/linker.cpp#146 edit
... //depot/stg/opencl/drivers/opencl/compiler/lib/backends/common/opt_level.cpp#30 edit
... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/libUtils.cpp#18 edit
... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/libUtils.h#27 edit
... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings.h#42 edit
... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings_hsail.h#32 edit
... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings_hsail64.h#27 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm/lib/Target/HSAIL/BRIGAsmPrinter.cpp#155 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm/lib/Target/HSAIL/BRIGAsmPrinter.h#69 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm/lib/Target/HSAIL/HSAIL.td#11 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm/lib/Target/HSAIL/HSAILISelDAGToDAG.cpp#71 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm/lib/Target/HSAIL/HSAILISelLowering.cpp#116 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm/lib/Target/HSAIL/HSAILISelLowering.h#29 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm/lib/Target/HSAIL/HSAILInstrInfo.cpp#42 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm/lib/Target/HSAIL/HSAILInstrInfo.h#18 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm/lib/Target/HSAIL/HSAILInstructions.td#22 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm/lib/Target/HSAIL/HSAILKernelManager.cpp#55 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm/lib/Target/HSAIL/HSAILSubtarget.cpp#14 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm/lib/Target/HSAIL/HSAILSubtarget.h#15 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm/lib/Target/HSAIL/HSAILTargetMachine.cpp#57 edit
... //depot/stg/opencl/drivers/opencl/tests/hsa/bin/test_driver.pl#29 edit
... //depot/stg/opencl/drivers/opencl/tests/hsa/tlst/llc_opt.tlst#97 edit
... //depot/stg/opencl/drivers/opencl/tests/hsa/tlst/ocl_features.tlst#58 edit


[ROCm/clr commit: 712c0c4009]
This commit is contained in:
foreman
2016-05-26 14:22:33 -04:00
parent 07f7765e13
commit 4335f720c0
8 changed files with 91 additions and 97 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/clr/rocclr/compiler/lib/backends/common/codegen.cpp
+22 -66
View File
@@ -42,10 +42,6 @@
using namespace amdcl;
using namespace llvm;
namespace llvm {
extern int HsailOptimizeFor;
}
//!--------------------------------------------------------------------------!//
// JIT Memory manager
//!--------------------------------------------------------------------------!//
@@ -499,72 +495,33 @@ llvmCodeGen(
TheTriple.setArch(Type);
// Package up features to be passed to target/subtarget
std::string FeatureStr;
if ((Type == Triple::amdil || Type == Triple::amdil64) &&
targetMap[famID].chip_options) {
uint64_t y = targetMap[famID].chip_options;
for (uint64_t x = 0; y != 0; y >>= 1, ++x) {
if (!(y & 0x1) && (x >= 11 && x < 16)) {
continue;
}
std::string FeatureStr = getFeatureString(binary->target, OptionsObj);
if ((1 << x) == F_NO_ALIAS) {
FeatureStr += (!OptionsObj->oVariables->AssumeAlias ? '+' : '-');
} else if ((1 << x) == F_STACK_UAV) {
FeatureStr += (OptionsObj->oVariables->UseStackUAV ? '+' : '-');
} else if ((1 << x) == F_MACRO_CALL) {
FeatureStr += (OptionsObj->oVariables->UseMacroForCall ? '+' : '-');
} else if ((1 << x) == F_64BIT_PTR) {
FeatureStr += (binary->target.arch_id == aclAMDIL64) ? '+' : '-';
} else {
FeatureStr += ((y & 0x1) ? '+' : '-');
}
llvm::TargetOptions targetOptions;
targetOptions.NoFramePointerElim = false;
targetOptions.StackAlignmentOverride =
OptionsObj->oVariables->CPUStackAlignment;
// jgolds
//targetOptions.EnableEBB = (optimize && OptionsObj->oVariables->CGEBB);
//targetOptions.EnableBFO = OptionsObj->oVariables->CGBFO;
//targetOptions.NoExcessFPPrecision = !OptionsObj->oVariables->EnableFMA;
FeatureStr += GPUCodeGenFlagTable[x];
if (y != 0x1) {
FeatureStr += ',';
}
}
}
// Don't allow unsafe optimizations for CPU because the library
// contains code that is not safe. See bug 9567.
if (isGPU)
targetOptions.UnsafeFPMath = OptionsObj->oVariables->UnsafeMathOpt;
targetOptions.LessPreciseFPMADOption = OptionsObj->oVariables->MadEnable ||
OptionsObj->oVariables->EnableMAD;
targetOptions.NoInfsFPMath = OptionsObj->oVariables->FiniteMathOnly;
// Need to add a support for OptionsObj->oVariables->NoSignedZeros,
targetOptions.NoNaNsFPMath = OptionsObj->oVariables->FiniteMathOnly;
if (Type == Triple::amdil64) {
if (OptionsObj->oVariables->SmallGlobalObjects)
FeatureStr += ",+small-global-objects";
}
#if 1 || LLVM_TRUNK_INTEGRATION_CL >= 1463
llvm::TargetOptions targetOptions;
targetOptions.NoFramePointerElim = false;
targetOptions.StackAlignmentOverride =
OptionsObj->oVariables->CPUStackAlignment;
// jgolds
//targetOptions.EnableEBB = (optimize && OptionsObj->oVariables->CGEBB);
//targetOptions.EnableBFO = OptionsObj->oVariables->CGBFO;
//targetOptions.NoExcessFPPrecision = !OptionsObj->oVariables->EnableFMA;
// Don't allow unsafe optimizations for CPU because the library
// contains code that is not safe. See bug 9567.
if (isGPU)
targetOptions.UnsafeFPMath = OptionsObj->oVariables->UnsafeMathOpt;
targetOptions.LessPreciseFPMADOption = OptionsObj->oVariables->MadEnable ||
OptionsObj->oVariables->EnableMAD;
targetOptions.NoInfsFPMath = OptionsObj->oVariables->FiniteMathOnly;
// Need to add a support for OptionsObj->oVariables->NoSignedZeros,
targetOptions.NoNaNsFPMath = OptionsObj->oVariables->FiniteMathOnly;
std::auto_ptr<TargetMachine>
target(TheTarget->createTargetMachine(TheTriple.getTriple(),
aclutGetCodegenName(binary->target), FeatureStr, targetOptions,
WINDOWS_SWITCH(Reloc::DynamicNoPIC, Reloc::PIC_),
CodeModel::Default, OLvl));
#else
std::auto_ptr<TargetMachine>
target(TheTarget->createTargetMachine(TheTriple.getTriple(),
aclutGetCodegenName(binary->target), FeatureStr,
WINDOWS_SWITCH(Reloc::DynamicNoPIC, Reloc::PIC_),
CodeModel::Default));
target(TheTarget->createTargetMachine(TheTriple.getTriple(),
aclutGetCodegenName(binary->target), FeatureStr, targetOptions,
WINDOWS_SWITCH(Reloc::DynamicNoPIC, Reloc::PIC_),
CodeModel::Default, OLvl));
assert(target.get() && "Could not allocate target machine!");
#endif
// MCJIT(Jan)
if(!isGPU && OptionsObj->oVariables->UseJIT) {
@@ -618,7 +575,6 @@ llvmCodeGen(
#ifdef WITH_TARGET_HSAIL
if (isHSAILTarget(binary->target)) {
llvm::HsailOptimizeFor = getIsaType(aclutGetTargetInfo(binary));
if (Target.addPassesToEmitFile(Passes, *Out, TargetMachine::CGFT_ObjectFile, true)) {
delete Out;
return 1;
projects/clr/rocclr/compiler/lib/backends/common/linker.cpp
-2
View File
@@ -124,7 +124,6 @@
#if !defined(LEGACY_COMPLIB)
namespace llvm {
extern bool HLC_FlushF32Denorms;
extern unsigned HLC_Max_WG_Size;
}
#endif
@@ -600,7 +599,6 @@ amdcl::OCLLinker::link(llvm::Module* input, std::vector<llvm::Module*> &libs)
setFP32RoundDivideSqrt(Options()->oVariables->FP32RoundDivideSqrt);
setUseNative(Options()->oVariables->OptUseNative);
setDenormsAreZero(Options()->oVariables->DenormsAreZero);
llvm::HLC_FlushF32Denorms = Options()->oVariables->DenormsAreZero;
llvm::HLC_Max_WG_Size = 2048; // Maximum HW supported workgroup size
setUniformWorkGroupSize(Options()->oVariables->UniformWorkGroupSize);
setHaveFastFMA32(chip == "Cypress"
projects/clr/rocclr/compiler/lib/backends/common/opt_level.cpp
+2 -1
View File
@@ -143,7 +143,8 @@ OptLevel::run(aclBinary *elf)
Machine = TheTarget->createTargetMachine(TheTriple.getTriple(),
aclutGetCodegenName(elf->target),
"", targetOptions,
getFeatureString(elf->target, Options()),
targetOptions,
WINDOWS_SWITCH(Reloc::DynamicNoPIC, Reloc::PIC_),
CodeModel::Default, OLvl);
}
projects/clr/rocclr/compiler/lib/utils/v0_8/libUtils.cpp
+22
View File
@@ -573,6 +573,28 @@ int getIsaType(const aclTargetInfo *target)
}
}
std::string getFeatureString(const aclTargetInfo& target, amd::option::Options *OptionsObj)
{
std::string FeatureStr;
if (isHSAILTarget(target)) {
uint64_t y = aclGetChipOptions(target);
FeatureStr += ((y & F_FP32_DENORMS) && !OptionsObj->oVariables->DenormsAreZero) ? '+' : '-';
FeatureStr += "fp32-denormals";
for (uint64_t x = 0; y != 0; y >>= 1, ++x) {
if ((1 << x) == F_FP32_DENORMS) {
continue;
}
if (!FeatureStr.empty()) {
FeatureStr += ',';
}
FeatureStr += ((y & 0x1) ? '+' : '-');
FeatureStr += HSAILCodeGenFlagTable[x];
}
}
return FeatureStr;
}
void
appendLogToCL(aclCompiler *cl, const std::string &logStr)
{
projects/clr/rocclr/compiler/lib/utils/v0_8/libUtils.h
+4
View File
@@ -11,6 +11,7 @@
#include <cassert>
#include "library.hpp"
#include "utils/bif_section_labels.hpp"
#include "utils/options.hpp"
using namespace bif;
// Utility function to set a flag in option structure
@@ -58,6 +59,9 @@ const std::string &getIsaTypeName(const aclTargetInfo *target);
// get isa type (compute capability) from the target information.
int getIsaType(const aclTargetInfo *target);
// get Feature String for target.
std::string getFeatureString(const aclTargetInfo& target, amd::option::Options *OptionsObj);
// Create a copy of an ELF and duplicate all sections/symbols
aclBinary*
createELFCopy(aclBinary *src);
projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings.h
+13
View File
@@ -158,6 +158,15 @@ typedef enum {
F_SI_64BIT_PTR = F_SI_BASE|F_64BIT_PTR
} GPUCodeGenFlags;
typedef enum {
// Bits for each feature.
F_FP32_DENORMS = 0x0001,
// Bitmasks for each device type.
F_CI_BASE = 0,
F_VI_BASE = F_CI_BASE | F_FP32_DENORMS,
F_AI_BASE = F_VI_BASE
} HSAILCodeGenFlags;
static const char* GPUCodeGenFlagTable[] = {
"fp64",
"byte_addressable_store",
@@ -180,6 +189,10 @@ static const char* GPUCodeGenFlagTable[] = {
"macro-call"
};
static const char* HSAILCodeGenFlagTable[] = {
"fp32-denormals"
};
static const char* calTargetMapping[] = {
"RV600", "RV610", "RV630", "RV670",
"RV770", "RV770", "RV710", "RV730",
projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail.h
+14 -14
View File
@@ -13,24 +13,24 @@
static const TargetMapping HSAILTargetMapping_0_8[] = {
UnknownTarget,
{ "KV", "Spectre", "generic", amd::GPU_Library_HSAIL, KV_SPECTRE_A0, 0, true, true, FAMILY_KV },
{ "KV", "Spooky", "generic", amd::GPU_Library_HSAIL, KV_SPOOKY_A0, 0, true, true, FAMILY_KV },
{ "KV", "Kalindi", "generic", amd::GPU_Library_HSAIL, KB_KALINDI_A0, 0, true, true, FAMILY_KV },
{ "KV", "Mullins", "generic", amd::GPU_Library_HSAIL, ML_GODAVARI_A0, 0, true, true, FAMILY_KV },
{ "CI", "Bonaire", "generic", amd::GPU_Library_HSAIL, CI_BONAIRE_M_A0, 0, true, false, FAMILY_CI },
{ "CI", "Bonaire", "generic", amd::GPU_Library_HSAIL, CI_BONAIRE_M_A1, 0, true, true, FAMILY_CI },
{ "CI", "Hawaii", "generic", amd::GPU_Library_HSAIL, CI_HAWAII_P_A0, 0, true, true, FAMILY_CI },
{ "VI", "Iceland", "generic", amd::GPU_Library_HSAIL, VI_ICELAND_M_A0, 0, true, true, FAMILY_VI },
{ "VI", "Tonga", "generic", amd::GPU_Library_HSAIL, VI_TONGA_P_A0, 0, true, true, FAMILY_VI },
{ "KV", "Spectre", "CI", amd::GPU_Library_HSAIL, KV_SPECTRE_A0, F_CI_BASE, true, true, FAMILY_KV },
{ "KV", "Spooky", "CI", amd::GPU_Library_HSAIL, KV_SPOOKY_A0, F_CI_BASE, true, true, FAMILY_KV },
{ "KV", "Kalindi", "CI", amd::GPU_Library_HSAIL, KB_KALINDI_A0, F_CI_BASE, true, true, FAMILY_KV },
{ "KV", "Mullins", "CI", amd::GPU_Library_HSAIL, ML_GODAVARI_A0, F_CI_BASE, true, true, FAMILY_KV },
{ "CI", "Bonaire", "CI", amd::GPU_Library_HSAIL, CI_BONAIRE_M_A0, F_CI_BASE, true, false, FAMILY_CI },
{ "CI", "Bonaire", "CI", amd::GPU_Library_HSAIL, CI_BONAIRE_M_A1, F_CI_BASE, true, true, FAMILY_CI },
{ "CI", "Hawaii", "CI", amd::GPU_Library_HSAIL, CI_HAWAII_P_A0, F_CI_BASE, true, true, FAMILY_CI },
{ "VI", "Iceland", "VI", amd::GPU_Library_HSAIL, VI_ICELAND_M_A0, F_VI_BASE, true, true, FAMILY_VI },
{ "VI", "Tonga", "VI", amd::GPU_Library_HSAIL, VI_TONGA_P_A0, F_VI_BASE, true, true, FAMILY_VI },
UnknownTarget,
UnknownTarget,
UnknownTarget,
{ "CZ", "Carrizo", "generic", amd::GPU_Library_HSAIL, CARRIZO_A0, 0, true, true, FAMILY_CZ },
{ "VI", "Fiji", "generic", amd::GPU_Library_HSAIL, VI_FIJI_P_A0, 0, true, true, FAMILY_VI },
{ "CZ", "Stoney", "generic", amd::GPU_Library_HSAIL, STONEY_A0, 0, true, true, FAMILY_CZ },
{ "VI", "Baffin", "generic", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A0, 0, true, true, FAMILY_VI },
{ "VI", "Ellesmere", "generic", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A0, 0, true, true, FAMILY_VI },
{ "CZ", "Carrizo", "VI", amd::GPU_Library_HSAIL, CARRIZO_A0, F_VI_BASE, true, true, FAMILY_CZ },
{ "VI", "Fiji", "VI", amd::GPU_Library_HSAIL, VI_FIJI_P_A0, F_VI_BASE, true, true, FAMILY_VI },
{ "CZ", "Stoney", "VI", amd::GPU_Library_HSAIL, STONEY_A0, F_VI_BASE, true, true, FAMILY_CZ },
{ "VI", "Baffin", "VI", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A0, F_VI_BASE, true, true, FAMILY_VI },
{ "VI", "Ellesmere", "VI", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A0, F_VI_BASE, true, true, FAMILY_VI },
InvalidTarget
};
projects/clr/rocclr/compiler/lib/utils/v0_8/target_mappings_hsail64.h
+14 -14
View File
@@ -12,24 +12,24 @@
static const TargetMapping HSAIL64TargetMapping_0_8[] = {
UnknownTarget,
{ "KV", "Spectre", "generic", amd::GPU_Library_HSAIL, KV_SPECTRE_A0, 0, true, true, FAMILY_KV },
{ "KV", "Spooky", "generic", amd::GPU_Library_HSAIL, KV_SPOOKY_A0, 0, true, true, FAMILY_KV },
{ "KV", "Kalindi", "generic", amd::GPU_Library_HSAIL, KB_KALINDI_A0, 0, true, true, FAMILY_KV },
{ "KV", "Mullins", "generic", amd::GPU_Library_HSAIL, ML_GODAVARI_A0, 0, true, true, FAMILY_KV },
{ "CI", "Bonaire", "generic", amd::GPU_Library_HSAIL, CI_BONAIRE_M_A0, 0, true, false, FAMILY_CI },
{ "CI", "Bonaire", "generic", amd::GPU_Library_HSAIL, CI_BONAIRE_M_A1, 0, true, true, FAMILY_CI },
{ "CI", "Hawaii", "generic", amd::GPU_Library_HSAIL, CI_HAWAII_P_A0, 0, true, true, FAMILY_CI },
{ "VI", "Iceland", "generic", amd::GPU_Library_HSAIL, VI_ICELAND_M_A0, 0, true, true, FAMILY_VI },
{ "VI", "Tonga", "generic", amd::GPU_Library_HSAIL, VI_TONGA_P_A0, 0, true, true, FAMILY_VI },
{ "KV", "Spectre", "CI", amd::GPU_Library_HSAIL, KV_SPECTRE_A0, F_CI_BASE, true, true, FAMILY_KV },
{ "KV", "Spooky", "CI", amd::GPU_Library_HSAIL, KV_SPOOKY_A0, F_CI_BASE, true, true, FAMILY_KV },
{ "KV", "Kalindi", "CI", amd::GPU_Library_HSAIL, KB_KALINDI_A0, F_CI_BASE, true, true, FAMILY_KV },
{ "KV", "Mullins", "CI", amd::GPU_Library_HSAIL, ML_GODAVARI_A0, F_CI_BASE, true, true, FAMILY_KV },
{ "CI", "Bonaire", "CI", amd::GPU_Library_HSAIL, CI_BONAIRE_M_A0, F_CI_BASE, true, false, FAMILY_CI },
{ "CI", "Bonaire", "CI", amd::GPU_Library_HSAIL, CI_BONAIRE_M_A1, F_CI_BASE, true, true, FAMILY_CI },
{ "CI", "Hawaii", "CI", amd::GPU_Library_HSAIL, CI_HAWAII_P_A0, F_CI_BASE, true, true, FAMILY_CI },
{ "VI", "Iceland", "VI", amd::GPU_Library_HSAIL, VI_ICELAND_M_A0, F_VI_BASE, true, true, FAMILY_VI },
{ "VI", "Tonga", "VI", amd::GPU_Library_HSAIL, VI_TONGA_P_A0, F_VI_BASE, true, true, FAMILY_VI },
UnknownTarget,
UnknownTarget,
UnknownTarget,
{ "CZ", "Carrizo", "generic", amd::GPU_Library_HSAIL, CARRIZO_A0, 0, true, true, FAMILY_CZ },
{ "VI", "Fiji", "generic", amd::GPU_Library_HSAIL, VI_FIJI_P_A0, 0, true, true, FAMILY_VI },
{ "CZ", "Stoney", "generic", amd::GPU_Library_HSAIL, STONEY_A0, 0, true, true, FAMILY_CZ },
{ "VI", "Baffin", "generic", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A0, 0, true, true, FAMILY_VI },
{ "VI", "Ellesmere", "generic", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A0, 0, true, true, FAMILY_VI },
{ "CZ", "Carrizo", "VI", amd::GPU_Library_HSAIL, CARRIZO_A0, F_VI_BASE, true, true, FAMILY_CZ },
{ "VI", "Fiji", "VI", amd::GPU_Library_HSAIL, VI_FIJI_P_A0, F_VI_BASE, true, true, FAMILY_VI },
{ "CZ", "Stoney", "VI", amd::GPU_Library_HSAIL, STONEY_A0, F_VI_BASE, true, true, FAMILY_CZ },
{ "VI", "Baffin", "VI", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A0, F_VI_BASE, true, true, FAMILY_VI },
{ "VI", "Ellesmere", "VI", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A0, F_VI_BASE, true, true, FAMILY_VI },
InvalidTarget
};