Adding HW Block Information (#1021)
* Adding HW Block Information * Addressed Review comments
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@@ -15,6 +15,7 @@ AvgNumActiveThreads:
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gfx90a:
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expression: SQ_THREAD_CYCLES_VALU/SQ_ACTIVE_INST_VALU
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description: 'Unit: percent'
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# CPC Block (Command Processor Compute) - The CPC block is responsible for the compute workloads
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CPC_CPC_STAT_BUSY:
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architectures:
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gfx942/gfx941/gfx940/gfx90a:
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@@ -81,6 +82,7 @@ CPC_UTCL1_STALL_ON_TRANSLATION:
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block: CPC
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event: 24
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description: One of the UTCL1s is stalled waiting on translation, XNACK or PENDING response.
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# Block CPF(Command Processor Fetch) - The CPF block is responsible for fetching the compute workloads
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CPF_CMP_UTCL1_STALL_ON_TRANSLATION:
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architectures:
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gfx942/gfx941/gfx940/gfx90a:
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@@ -253,6 +255,7 @@ GDS_UTIL:
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gfx10/gfx1010/gfx1030/gfx1031/gfx1032:
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expression: 100*GRBM_GDS_BUSY/GRBM_GUI_ACTIVE
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description: Percentage of the GRBM_GUI_ACTIVE time that the Global Data Share (GDS) is busy.
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# Block GL2C (Graphic L2 Cache) - The GL2C block is a cache that sits between the L1 cache and the memory
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GL2C_EA_RDREQ_128B:
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architectures:
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gfx10/gfx1010/gfx1030/gfx1031/gfx11/gfx1032/gfx1102/gfx1100/gfx1101:
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@@ -378,6 +381,7 @@ GPU_UTIL:
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gfx942/gfx941/gfx10/gfx1010/gfx1030/gfx1031/gfx11/gfx1032/gfx1102/gfx906/gfx1100/gfx1101/gfx940/gfx908/gfx90a/gfx9:
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expression: 100*GRBM_GUI_ACTIVE/GRBM_COUNT
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description: Percentage of the time that GUI is active
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# Block GRBM (Graphics Register Bus Manager Block)
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GRBM_COUNT:
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architectures:
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gfx942/gfx941/gfx10/gfx1010/gfx1030/gfx1031/gfx11/gfx1032/gfx1102/gfx906/gfx1100/gfx1101/gfx940/gfx908/gfx8/gfx900/gfx90a/gfx9:
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@@ -623,6 +627,7 @@ SIMD_NUM:
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gfx942/gfx941/gfx10/gfx1010/gfx1030/gfx1031/gfx11/gfx1032/gfx1102/gfx906/gfx1100/gfx1101/gfx940/gfx908/gfx8/gfx900/gfx90a/gfx9:
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expression: simd_per_cu/CU_NUM
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description: SIMD Number
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# SPI Block(Shader Pipe Interpolator- The Shader Processor Input/Interpolator (SPI), is in charge of managing all resources (wave-slots, GPRs, LDS, barrier), in the shader array, as well as launching and tracking waves on SIMDs)
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SPI_CSN_BUSY:
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architectures:
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gfx942/gfx941/gfx940/gfx90a:
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@@ -749,6 +754,7 @@ SPI_VWC_CSC_WR:
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description: Number of clocks to write CSC waves to VGPRs (need to multiply this value by 4) Requires
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SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL
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= 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;
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# Block SQ( Shader SeQuencer Block)
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SQC_DCACHE_ATOMIC:
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architectures:
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gfx942/gfx941/gfx940/gfx90a:
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@@ -2063,6 +2069,8 @@ SpiUtil:
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gfx90a:
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expression: 100*GRBM_SPI_BUSY/GRBM_GUI_ACTIVE
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description: 'Unit: percent'
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# TA block( The Texture Addressing block) processes address components and write data from the shaders and passes them to the TCP and texture data TD blocks.
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TA_ADDR_STALLED_BY_TC_CYCLES:
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architectures:
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gfx90a:
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@@ -2357,6 +2365,7 @@ TA_UTIL:
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expression: 100*GRBM_TA_BUSY/GRBM_GUI_ACTIVE
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description: Percentage of the GRBM_GUI_ACTIVE time that any of the Texture Pipes (TA) are busy in the
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shader engine(s).
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# TCA block(The Texture Cache Arbiter)
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TCA_BUSY:
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architectures:
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gfx942/gfx941/gfx940/gfx90a:
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@@ -2379,6 +2388,7 @@ TCA_CYCLE_sum:
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gfx942/gfx941/gfx940/gfx90a:
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expression: reduce(TCA_CYCLE,sum)
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description: 'Number of cycles. Sum over all TCA instances '
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# TCC Block (Texture Cache per Channel)
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TCC_ALL_TC_OP_INV_EVICT:
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architectures:
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gfx942/gfx941/gfx940/gfx90a:
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@@ -3264,6 +3274,7 @@ TCC_WRREQ_STALL_max:
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gfx942/gfx941/gfx940:
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expression: reduce(TCC_EA0_WRREQ_STALL,max)
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description: Number of cycles a write request was stalled. Max over TCC instances.
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# TCP Block (Texture Cache per Pipe)
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TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES:
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architectures:
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gfx90a:
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@@ -3830,6 +3841,7 @@ TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum:
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gfx942/gfx941/gfx940/gfx90a:
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expression: reduce(TCP_WRITE_TAGCONFLICT_STALL_CYCLES,sum)
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description: Tagram conflict stall on a write. Sum over TCP instances.
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# Block TD (Texture Data Block)
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TD_ATOMIC_WAVEFRONT:
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architectures:
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gfx90a:
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