libhsakmt: Limit control stack size on gfx10

The queue control stack size cannot exceed 0x7000 on ASICs
gfx1010 through gfx1031. The lower limit is not achievable
with AQL so this should have no practical effect.

Fixes control stack size overflow on large ASICs.

Change-Id: Ib78cf6e4c5f096044bf8de24debe211689891caa
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>

src/queues.c

@@ -430,6 +430,15 @@ static bool update_ctx_save_restore_size(uint32_t nodeid, struct queue *q)
 		q->ctl_stack_size = PAGE_ALIGN_UP(ctl_stack_size
 					+ sizeof(HsaUserContextSaveAreaHeader));
 
+		if (q->dev_info->asic_family >= CHIP_NAVI10 &&
+			q->dev_info->asic_family <= CHIP_NAVY_FLOUNDER) {
+			/* HW design limits control stack size to 0x7000.
+			 * This is insufficient for theoretical PM4 cases
+			 * but sufficient for AQL, limited by SPI events.
+			 */
+			q->ctl_stack_size = MIN(q->ctl_stack_size, 0x7000);
+		}
+
 		q->ctx_save_restore_size = q->ctl_stack_size
 					+ PAGE_ALIGN_UP(wg_data_size);
 		return true;