SWDEV-525231 - Update changelog for ROCm 7.0 release (#319)
[ROCm/clr commit: d14cfb9c25]
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Jiang, Julia
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@@ -2,26 +2,27 @@
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Full documentation for HIP is available at [rocm.docs.amd.com](https://rocm.docs.amd.com/projects/HIP/en/latest/index.html)
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## HIP 6.5 for ROCm 6.5
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## HIP 7.0 for ROCm 7.0
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### Added
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* New HIP APIs
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- `hipLaunchKernelEx` dispatches the provided kernel with the given launch configuration and forwards the kernel arguments.
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- `hipLaunchKernelExC` launches a HIP kernel using a generic function pointer and the specified configuration.
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- `hipDrvLaunchKernelEx` dispatches the device kernel represented by a HIP function object
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- `hipDrvLaunchKernelEx` dispatches the device kernel represented by a HIP function object.
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- `hipMemGetHandleForAddressRange` gets a handle for the address range requested.
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* New support for Open Compute Project (OCP) floating-point `FP4`/`FP6`/`FP8` as the following. For details, see [Low precision floating point document](https://rocm.docs.amd.com/projects/HIP/en/latest/reference/low_fp_types.html).
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- Data types for `FP4`/`FP6`/`FP8`.
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- HIP APIs for `FP4`/`FP6`/`FP8`, which are compatible with corresponding CUDA APIs.
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- HIP Extensions APIs for microscaling formats, which are supported on AMD GPUs.
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* New `wptr` and `rptr` values in `ClPrint`, for better logging in dispatch barrier methods.
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* New debug mask, to print precise code object information for logging.
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* The `_sync()` version of crosslane builtins such as `shfl_sync()` and `__reduce_add_sync` are enabled by default. These can be
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disabled by setting the preprocessor macro `HIP_DISABLE_WARP_SYNC_BUILTINS`.
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* The `_sync()` version of crosslane builtins such as `shfl_sync()` and `__reduce_add_sync` are enabled by default. These can be disabled by setting the preprocessor macro `HIP_DISABLE_WARP_SYNC_BUILTINS`.
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### Changed
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* Some unsupported GPUs such as gfx8, gfx8 and gfx7 are deprecated on Microsoft Windows.
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* Some unsupported GPUs such as gfx9, gfx8 and gfx7 are deprecated on Microsoft Windows.
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* Stream validation in some HIP APIs are removed, to match the behavior with CUDA.
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### Optimized
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@@ -36,11 +37,52 @@ HIP runtime has the following functional improvements which greatly improve runt
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* Improved kernel logging using demangling shader names.
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* Advanced support for SPIRV, now kernel compilation caching is enabled by default. This feature is controlled by the environment variable `AMD_COMGR_CACHE`, for details, see [hip_rtc document](https://rocm.docs.amd.com/projects/HIP/en/latest/how-to/hip_rtc.html).
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* Programmatic support for scratch limit on GPU device. Developer can now use the environment variable `HSA_SCRATCH_SINGLE_LIMIT` to change the default allocation size with expected scratch limit.
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* HIP runtime now enables peer-to-peer (P2P) memory copies to utilize all available SDMA engines, rather than being limited to a single engine. It also selects the best engine first to give optimal bindwidth.
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* Improved launch latency for `D2D` copies and `memset` on MI300 series.
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### Resolved issues
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* Error of "unable to find modules" in HIP clean up for code object module.
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## HIP 6.4.2 for ROCm 6.4.2
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### Added
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* Support for the pointer attribute `HIP_POINTER_ATTRIBUTE_CONTEXT`.
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### Optimized
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* Improved implementation in `hipEventSynchronize`, HIP runtime now makes internal callbacks non-blocking to gain performance.
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### Resolved issues
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* Issue of dependency on `libgcc-s1` during rocm-dev install on Debian Buster. HIP runtime removed this Debian package dependency, and uses `libgcc1` instead for this distros.
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* Building issue for `COMGR` dynamic load on Fedora and other Distros. HIP runtime now doesn't link against `libamd_comgr.so`.
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* Failure in the API `hipStreamDestroy`, when stream type is `hipStreamLegacy`. The API now returns error code `hipErrorInvalidResourceHandle` on this condition.
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* Kernel launch errors, such as `shared object initialization failed`, `invalid device function` or `kernel execution failure`. HIP runtime now loads `COMGR` properly considering the file with its name and mapped mage.
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* Memory access fault in some appplications. HIP runtime fixed offset accumulation in memory address.
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## HIP 6.4.1 for ROCm 6.4.1
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### Added
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* New log mask enumeration `LOG_COMGR` enables logging precise code object information.
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### Changed
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* HIP runtime uses device bitcode before SPIRV.
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* The implementation of preventing `hipLaunchKernel` latency degradation with number of idle streams is reverted/disabled by default.
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### Optimized
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* Improved kernel logging includes de-mangling shader names.
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* Refined implementation in HIP APIs `hipEventRecords` and `hipStreamWaitEvent` for performance improvement.
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### Resolved issues
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* Stale state during the graph capture. The return error was fixed, HIP runtime now always uses the latest dependent nodes during `hipEventRecord` capture.
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* Segmentation fault during kernel execution. HIP runtime now allows maximum stack size as per ISA on the GPU device.
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## HIP 6.4 (For ROCm 6.4)
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### Added
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@@ -75,6 +117,9 @@ HIP runtime has the following functional improvements which greatly improve runt
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- Kernel copy path is enabled for unpinned `H2D`/`D2H` methods.
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- The default environment variable `GPU_FORCE_BLIT_COPY_SIZE` is set to `16`, which limits the kernel copy to sizes less than 16 KB, while copies about that would be handled by `SDMA` engine.
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- Blit code is refactored and ASAN instrumentation is cleaned up.
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* HIP runtime uses signals without interrupts.
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- In active wait mode, uses signals without interrupts by default.
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- Only when a callback is required, switches to the interrupts.
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### Resolved issues
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@@ -87,10 +132,12 @@ HIP runtime has the following functional improvements which greatly improve runt
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The following are the list of backwards incompatible changes planned for the upcoming major ROCm release.
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* Signature changes in APIs to match corresponding CUDA APIs,
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- `hiprtcCreatreProgram`
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- `hiprtcCreateProgram`
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- `hiprtcCompileProgram`
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- `hipCtxGetApiVersion`
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* Behaviour of `hipPointerGetAttributes` is changed to match corresponding CUDA API in version 11 and later releases.
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* Behavior of `hipPointerGetAttributes` is changed to match corresponding CUDA API in version 11 and later releases.
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* Behavior of `hipFree` is changed to match corresponding CUDA API `cudaFree`.
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* HIP vector constructor changes for `hipComplex`.
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* Return error/value codes update in the following hip APIs, they now match the corresponding CUDA APIs,
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- `hipModuleLaunchKernel`
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- `hipExtModuleLaunchKernel`
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@@ -114,11 +161,11 @@ The following are the list of backwards incompatible changes planned for the upc
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- `hipMemPoolDestory`
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- `hipDeviceSetMemPool`
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- `hipEventQuery`
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* The implementation of `hipStreamAddCallback` is updated, to match the behaviour of CUDA.
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* The implementation of `hipStreamAddCallback` is updated, to match the behavior of CUDA.
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* Removal of hiprtc symbols from hip library.
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- hiprtc will be a independent library, all symbols supported in hip library are removed.
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- Any application using hiprtc APIs should link explicitly with hiprtc library.
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- This change makes the usage of hiprtc library on Linux the same as on Windows, and matches the behaviour of CUDA nvrtc.
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- This change makes the usage of hiprtc library on Linux the same as on Windows, and matches the behavior of CUDA nvrtc.
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* Removal of deprecated struct `HIP_MEMSET_NODE_PARAMS`, developers can use definition `hipMemsetParams` instead.
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@@ -158,10 +205,9 @@ The following are the list of backwards incompatible changes planned for the upc
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* An activeQueues set that tracks only the queues that have a command submitted to them, which allows fast iteration in `waitActiveStreams`.
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### Resolved issues
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* A Deadlock in a specific customer application by preventing hipLaunchKernel latency degradation with number of idle streams.
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### Optimized
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* Mechanism of preventing `hipLaunchKernel` latency degradation with number of idle streams is implemented for performance improvement.
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## HIP 6.3 for ROCm 6.3
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@@ -189,6 +235,11 @@ The following are the list of backwards incompatible changes planned for the upc
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* Optimized multi-threaded dispatches to improve performance.
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* Limited the software batch size to control the number of command submissions for runtime to handle efficiently.
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* Optimizes HSA callback performance when a large number of events are recorded by multiple threads and submitted to multiple GPUs.
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* HIP graph execution perfomance improvement.
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- Added the optimized multistream path in graph execution. It uses a fixed number of async streams in the execution
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- Optimized the launch latency, where commands creation and execution is done at the same time
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- Optimized the scheduling to use less barriers and waiting signals if the same queue can be detected
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- The new path is controlled by a new environment variable, with the options either to use the original path, or to force the number of asynchronous queues for execution.
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### Resolved issues
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@@ -356,7 +407,7 @@ This header exists alongside the older bfloat16 header in`amd_hip_bfloat16.h` wh
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### Resolved issues
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- Kernel launch maximum dimension validation is added specifically on gridY and gridZ in the HIP API hipModule-LaunchKernel. As a result,when hipGetDeviceAttribute is called for the value of hipDeviceAttributeMaxGrid-Dim, the behavior on the AMD platform is equivalent to NVIDIA.
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- The HIP stream synchronisation behaviour is changed in internal stream functions, in which a flag "wait" is added and set when the current stream is null pointer while executing stream synchronisation on other explicitly created streams. This change avoids blocking of execution on null/default stream.
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- The HIP stream synchronisation behavior is changed in internal stream functions, in which a flag "wait" is added and set when the current stream is null pointer while executing stream synchronisation on other explicitly created streams. This change avoids blocking of execution on null/default stream.
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The change won't affect usage of applications, and makes them behave the same on the AMD platform as NVIDIA.
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- Error handling behavior on unsupported GPU is fixed, HIP runtime will log out error message, instead of creating signal abortion error which is invisible to developers but continued kernel execution process. This is for the case when developers compile any application via hipcc, setting the option --offload-arch with GPU ID which is different from the one on the system.
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