P4 to Git Change 1179663 by gandryey@gera-dev-w7 on 2015/08/12 13:14:46
EPR #419072 - [OpenCL2.0] Enable 16MB large on device queues
- Enable device queue creation up to 12MB. That should allow to run Intel SDK sample from the EPR that requires 6MB queue only.
- Currently a queue with >12.5MB size has a significant performance degradation. Thus the current max possible is 12MB. In general it's preferable to use the queue size more suitable for the task, rather than max possible.
Affected files ...
... //depot/stg/opencl/drivers/opencl/library/hsa/hsail/src/devenq/schedule.cl#10 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpublit.cpp#115 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpublit.hpp#38 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpudefs.hpp#123 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpudevice.cpp#517 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpusched.hpp#17 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuvirtual.cpp#372 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuvirtual.hpp#131 edit
[ROCm/clr commit: 1386191b6c]
Šī revīzija ir iekļauta:
foreman
@@ -2727,7 +2727,7 @@ KernelBlitManager::runScheduler(
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device::Memory& vqueue,
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device::Memory& params,
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uint paramIdx,
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uint numSlots
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uint threads
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) const
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{
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amd::ScopedLock k(lockXferOps_);
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@@ -2735,7 +2735,7 @@ KernelBlitManager::runScheduler(
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size_t dim = 1;
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size_t globalWorkOffset[1] = { 0 };
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size_t globalWorkSize[1] = { numSlots / 32 };
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size_t globalWorkSize[1] = { threads };
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size_t localWorkSize[1] = { 1 };
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// Program kernels arguments
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@@ -379,7 +379,7 @@ public:
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device::Memory& vqueue, //!< Memory object for virtual queue
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device::Memory& params, //!< Extra arguments for the scheduler
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uint paramIdx, //!< Parameter index
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uint numSlots //!< Number of slots in the queue
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uint threads //!< Number of scheduling threads
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) const;
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private:
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@@ -61,6 +61,9 @@ const static uint HsaImageObjectAlignment = 16;
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const static uint HsaSamplerObjectSize = 32;
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const static uint HsaSamplerObjectAlignment = 16;
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//! HSA path specific defines for images
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const static uint DeviceQueueMaskSize = 32;
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//! Defines all supported ASIC families
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enum AsicFamilies {
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Family7xx,
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@@ -490,7 +490,7 @@ void NullDevice::fillDeviceInfo(
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info_.queueOnDeviceProperties_ =
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CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE | CL_QUEUE_PROFILING_ENABLE;
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info_.queueOnDevicePreferredSize_ = 256 * Ki;
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info_.queueOnDeviceMaxSize_ = 512 * Ki;
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info_.queueOnDeviceMaxSize_ = 12 * Mi;
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info_.maxOnDeviceQueues_ = 1;
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info_.maxOnDeviceEvents_ = settings().numDeviceEvents_;
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info_.globalVariablePreferredTotalSize_ = static_cast<size_t>(info_.globalMemSize_);
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@@ -70,6 +70,8 @@ struct SchedulerParam {
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uint64_t parentAQL; //!< Host parent AmdAqlWrap packet
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uint32_t dedicatedQueue; //!< Scheduler uses a dedicated queue
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uint32_t scratchOffset; //!< Scratch buffer offset
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uint32_t mask_groups; //!< Processed mask groups by one thread
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uint32_t reserved; //!< Reserved
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};
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} // namespace gpu
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@@ -278,9 +278,18 @@ VirtualGPU::createVirtualQueue(uint deviceQueueSize)
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{
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uint MinDeviceQueueSize = 16 * 1024;
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deviceQueueSize = std::max(deviceQueueSize, MinDeviceQueueSize);
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maskGroups_ = deviceQueueSize / (512 * Ki);
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maskGroups_ = (maskGroups_== 0) ? 1 : maskGroups_;
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// Align the queue size for the multiple dispatch scheduler.
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// Each thread works with 32 entries
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deviceQueueSize = amd::alignUp(deviceQueueSize, sizeof(AmdAqlWrap) * 32);
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// Each thread works with 32 entries * maskGroups
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uint extra = deviceQueueSize % (sizeof(AmdAqlWrap) *
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DeviceQueueMaskSize * maskGroups_);
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if (extra != 0) {
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deviceQueueSize += (sizeof(AmdAqlWrap) *
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DeviceQueueMaskSize * maskGroups_) - extra;
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}
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if (deviceQueueSize_ == deviceQueueSize) {
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return true;
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@@ -319,11 +328,11 @@ VirtualGPU::createVirtualQueue(uint deviceQueueSize)
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uint eventMaskOffs = allocSize;
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// Add mask array for events
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allocSize += amd::alignUp(dev().settings().numDeviceEvents_, 32) / 8;
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allocSize += amd::alignUp(dev().settings().numDeviceEvents_, DeviceQueueMaskSize) / 8;
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uint slotMaskOffs = allocSize;
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// Add mask array for AmdAqlWrap slots
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allocSize += amd::alignUp(numSlots, 32) / 8;
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allocSize += amd::alignUp(numSlots, DeviceQueueMaskSize) / 8;
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virtualQueue_ = new Memory(dev(), allocSize);
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Resource::MemoryType type = (GPU_PRINT_CHILD_KERNEL == 0) ?
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@@ -402,6 +411,7 @@ VirtualGPU::VirtualGPU(
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, schedParams_(NULL)
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, schedParamIdx_(0)
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, deviceQueueSize_(0)
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, maskGroups_(1)
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, hsaQueueMem_(NULL)
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, profileEnabled_(false)
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{
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@@ -1908,7 +1918,7 @@ VirtualGPU::submitKernelInternalHSA(
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static_cast<KernelBlitManager&>(gpuDefQueue->blitMgr()).runScheduler(
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*gpuDefQueue->virtualQueue_,
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*gpuDefQueue->schedParams_, gpuDefQueue->schedParamIdx_,
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gpuDefQueue->vqHeader_->aql_slot_num);
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gpuDefQueue->vqHeader_->aql_slot_num / (DeviceQueueMaskSize * maskGroups_));
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const static bool FlushL2 = true;
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gpuDefQueue->flushCUCaches(FlushL2);
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@@ -1928,6 +1938,7 @@ VirtualGPU::submitKernelInternalHSA(
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param->parentAQL = vmParentWrap;
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param->dedicatedQueue = dev().settings().useDeviceQueue_;
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param->useATC = dev().settings().svmFineGrainSystem_;
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param->mask_groups = maskGroups_;
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// Fill the scratch buffer information
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if (hsaKernel.prog().maxScratchRegs() > 0) {
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@@ -1958,7 +1969,8 @@ VirtualGPU::submitKernelInternalHSA(
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gpuDefQueue->schedParamIdx_ * sizeof(SchedulerParam);
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gpuDefQueue->virtualQueueDispatcherEnd(gpuEvent,
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gpuDefQueue->vmMems(), gpuDefQueue->cal_.memCount_,
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signalAddr, loopStart, gpuDefQueue->vqHeader_->aql_slot_num / 32);
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signalAddr, loopStart, gpuDefQueue->vqHeader_->aql_slot_num /
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(DeviceQueueMaskSize * maskGroups_));
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// Set GPU event for the used resources
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for (uint i = 0; i < memList.size(); ++i) {
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@@ -545,6 +545,7 @@ private:
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Memory* schedParams_; //!< The scheduler parameters
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uint schedParamIdx_; //!< Index in the scheduler parameters buffer
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uint deviceQueueSize_; //!< Device queue size
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uint maskGroups_; //!< The number of mask groups processed in the scheduler by one thread
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Memory* hsaQueueMem_; //!< Memory for the amd_queue_t object
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bool profileEnabled_;//!< Profiling is enabled
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