Updated amd_aql_queue for GFX12
Added GFX12 implementation for InitScratchSRD and for compute_tmpring.
Implementation for compute_tmpring could be combined with GFX11 with some
refactoring as a possible future improvement.
Signed-off-by: David Belanger <david.belanger@amd.com>
Change-Id: I8013cbe4438786bf41bbfd03f6a5d3b9ef51e7bf
Signed-off-by: Chris Freehill <cfreehil@amd.com>
[ROCm/ROCR-Runtime commit: def4a6c326]
Esse commit está contido em:
@@ -252,9 +252,11 @@ class AqlQueue : public core::Queue, private core::LocalSignal, public core::Doo
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void FillBufRsrcWord3();
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void FillBufRsrcWord3_Gfx10();
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void FillBufRsrcWord3_Gfx11();
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void FillBufRsrcWord3_Gfx12();
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void FillComputeTmpRingSize();
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void FillAltComputeTmpRingSize();
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void FillComputeTmpRingSize_Gfx11();
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void FillComputeTmpRingSize_Gfx12();
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void FreeMainScratchSpace();
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void FreeAltScratchSpace();
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@@ -1674,6 +1674,26 @@ void AqlQueue::FillBufRsrcWord3_Gfx11() {
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amd_queue_.scratch_resource_descriptor[3] = srd3.u32All;
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}
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void AqlQueue::FillBufRsrcWord3_Gfx12() {
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SQ_BUF_RSRC_WORD3_GFX12 srd3;
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srd3.bits.DST_SEL_X = SQ_SEL_X;
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srd3.bits.DST_SEL_Y = SQ_SEL_Y;
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srd3.bits.DST_SEL_Z = SQ_SEL_Z;
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srd3.bits.DST_SEL_W = SQ_SEL_W;
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srd3.bits.FORMAT = BUF_FORMAT_32_UINT;
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srd3.bits.RESERVED1 = 0;
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srd3.bits.INDEX_STRIDE = 0; // filled in by CP
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srd3.bits.ADD_TID_ENABLE = 1;
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srd3.bits.WRITE_COMPRESS_ENABLE = 0;
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srd3.bits.COMPRESSION_EN = 0;
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srd3.bits.COMPRESSION_ACCESS_MODE = 0;
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srd3.bits.OOB_SELECT = 2; // no bounds check in swizzle mode
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srd3.bits.TYPE = SQ_RSRC_BUF;
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amd_queue_.scratch_resource_descriptor[3] = srd3.u32All;
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}
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// Set concurrent wavefront limits only when scratch is being used.
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void AqlQueue::FillComputeTmpRingSize() {
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COMPUTE_TMPRING_SIZE tmpring_size = {};
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@@ -1772,11 +1792,52 @@ void AqlQueue::FillComputeTmpRingSize_Gfx11() {
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amd_queue_.compute_tmpring_size = tmpring_size.u32All;
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}
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// Set concurrent wavefront limits only when scratch is being used.
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void AqlQueue::FillComputeTmpRingSize_Gfx12() {
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// For GFX12, struct field size changes.
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// Consider refactoring code for GFX11/GFX12 if no other changes.
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COMPUTE_TMPRING_SIZE_GFX12 tmpring_size = {};
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if (queue_scratch_.main_size == 0) {
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amd_queue_.compute_tmpring_size = tmpring_size.u32All;
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return;
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}
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const auto& agent_props = agent_->properties();
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const uint32_t num_xcc = agent_props.NumXcc;
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// Determine the maximum number of waves device can support
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uint32_t num_cus = agent_props.NumFComputeCores / (agent_props.NumSIMDPerCU * num_xcc);
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uint32_t max_scratch_waves = num_cus * agent_props.MaxSlotsScratchCU;
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// Scratch is allocated program COMPUTE_TMPRING_SIZE register
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// Scratch Size per Wave is specified in terms of kilobytes
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uint32_t wave_scratch = (((queue_scratch_.main_lanes_per_wave * queue_scratch_.main_size_per_thread) +
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queue_scratch_.mem_alignment_size - 1) /
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queue_scratch_.mem_alignment_size);
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tmpring_size.bits.WAVESIZE = wave_scratch;
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assert(wave_scratch == tmpring_size.bits.WAVESIZE && "WAVESIZE Overflow.");
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uint32_t num_waves =
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queue_scratch_.main_size / (tmpring_size.bits.WAVESIZE * queue_scratch_.mem_alignment_size);
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// For GFX11 we specify number of waves per engine instead of total
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num_waves /= agent_->properties().NumShaderBanks;
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tmpring_size.bits.WAVES = std::min(num_waves, max_scratch_waves);
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amd_queue_.compute_tmpring_size = tmpring_size.u32All;
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}
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// @brief Define the Scratch Buffer Descriptor and related parameters
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// that enable kernel access scratch memory
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void AqlQueue::InitScratchSRD() {
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switch (agent_->isa()->GetMajorVersion()) {
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case 12:
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FillBufRsrcWord0();
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FillBufRsrcWord1_Gfx11();
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FillBufRsrcWord2();
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FillBufRsrcWord3_Gfx12();
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FillComputeTmpRingSize_Gfx12();
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break;
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case 11:
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FillBufRsrcWord0();
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FillBufRsrcWord1_Gfx11();
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