Fix init process apertures
Kernel ioctl AMDKFD_IOC_GET_PROCESS_APERTURES returns process apertures only for GPU nodes. The current implementation assumed that this list of GPU nodes returned by the ioctl has one to one correpondence to sysfs topology nodes. This fails when non-GPU nodes exist in topology as in case of Intel + gfx802 Fix this by using gpu_id (./sys/.../kfd/topology/nodes/1/gpu_id) to map information obtained from kernel ioctl call. Change-Id: I4ab8ae5354f12cf0b6609fc4b24182b82eb3677f
Bu işleme şunda yer alıyor:
Harish Kasiviswanathan
+86
-64
@@ -92,6 +92,9 @@ typedef struct {
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typedef struct {
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uint32_t gpu_id;
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uint32_t device_id;
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uint32_t node_id;
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uint64_t local_mem_size;
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aperture_t lds_aperture;
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manageble_aperture_t scratch_aperture;
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manageble_aperture_t scratch_physical;
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@@ -108,7 +111,7 @@ static gpu_mem_t gpu_mem[] = INIT_GPUs_MEM;
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static void *dgpu_shared_aperture_base = NULL;
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static void *dgpu_shared_aperture_limit = NULL;
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static HSAKMT_STATUS dgpu_mem_init(uint8_t node_id, void **base, void **limit);
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static HSAKMT_STATUS dgpu_mem_init(uint32_t node_id, void **base, void **limit);
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static int set_dgpu_aperture(uint32_t node_id, uint64_t base, uint64_t limit);
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static void __fmm_release(uint32_t gpu_id, void *address,
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uint64_t MemorySizeInBytes, manageble_aperture_t *aperture);
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@@ -845,79 +848,104 @@ static int fmm_set_memory_policy(uint32_t gpu_id, int default_policy, int alt_po
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HSAKMT_STATUS fmm_init_process_apertures(void)
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{
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struct kfd_ioctl_get_process_apertures_args args;
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uint8_t node_id;
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uint32_t i = 0;
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int32_t gpu_mem_id =0;
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uint32_t gpu_id;
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HsaSystemProperties sys_props;
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HsaNodeProperties props;
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HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS;
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ret = topology_sysfs_get_system_props(&sys_props);
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if (ret != HSAKMT_STATUS_SUCCESS)
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return ret;
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/* Initialize gpu_mem[] from sysfs topology. This is necessary because this function
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* gets called before hsaKmtAcquireSystemProperties() is called.*/
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while (i < sys_props.NumNodes) {
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ret = topology_sysfs_get_node_props(i, &props, &gpu_id);
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if (ret != HSAKMT_STATUS_SUCCESS)
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return ret;
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i++;
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/* Skip non-GPU nodes */
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if (gpu_id == 0)
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continue;
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gpu_mem[gpu_mem_id].gpu_id = gpu_id;
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gpu_mem[gpu_mem_id].local_mem_size = props.LocalMemSize;
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gpu_mem[gpu_mem_id].device_id = props.DeviceId;
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gpu_mem[gpu_mem_id].node_id = i;
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gpu_mem_id++;
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}
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if (kmtIoctl(kfd_fd, AMDKFD_IOC_GET_PROCESS_APERTURES, (void *) &args))
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return HSAKMT_STATUS_ERROR;
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for (node_id = 0 ; node_id < args.num_of_nodes ; node_id++) {
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gpu_mem[node_id].gpu_id =
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args.process_apertures[node_id].gpu_id;
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for (i = 0 ; i < args.num_of_nodes ; i++) {
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/* Map Kernel process device data node i <--> gpu_mem_id which indexes into gpu_mem[]
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* based on gpu_id */
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gpu_mem_id = gpu_mem_find_by_gpu_id(args.process_apertures[i].gpu_id);
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if (gpu_mem_id < 0)
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return HSAKMT_STATUS_ERROR;
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gpu_mem[node_id].lds_aperture.base =
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PORT_UINT64_TO_VPTR(args.process_apertures[node_id].lds_base);
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gpu_mem[gpu_mem_id].lds_aperture.base =
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PORT_UINT64_TO_VPTR(args.process_apertures[i].lds_base);
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gpu_mem[node_id].lds_aperture.limit =
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PORT_UINT64_TO_VPTR(args.process_apertures[node_id].lds_limit);
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gpu_mem[gpu_mem_id].lds_aperture.limit =
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PORT_UINT64_TO_VPTR(args.process_apertures[i].lds_limit);
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gpu_mem[node_id].gpuvm_aperture.base =
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PORT_UINT64_TO_VPTR(args.process_apertures[node_id].gpuvm_base);
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gpu_mem[gpu_mem_id].gpuvm_aperture.base =
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PORT_UINT64_TO_VPTR(args.process_apertures[i].gpuvm_base);
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gpu_mem[node_id].gpuvm_aperture.limit =
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PORT_UINT64_TO_VPTR(args.process_apertures[node_id].gpuvm_limit);
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gpu_mem[gpu_mem_id].gpuvm_aperture.limit =
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PORT_UINT64_TO_VPTR(args.process_apertures[i].gpuvm_limit);
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gpu_mem[node_id].scratch_aperture.base =
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PORT_UINT64_TO_VPTR(args.process_apertures[node_id].scratch_base);
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gpu_mem[gpu_mem_id].scratch_aperture.base =
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PORT_UINT64_TO_VPTR(args.process_apertures[i].scratch_base);
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gpu_mem[node_id].scratch_aperture.limit =
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PORT_UINT64_TO_VPTR(args.process_apertures[node_id].scratch_limit);
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gpu_mem[gpu_mem_id].scratch_aperture.limit =
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PORT_UINT64_TO_VPTR(args.process_apertures[i].scratch_limit);
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if (topology_sysfs_get_node_props(node_id, &props, &gpu_id) ==
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HSAKMT_STATUS_SUCCESS) {
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if (topology_is_dgpu(props.DeviceId)) {
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uintptr_t alt_base;
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uint64_t alt_size;
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int err;
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if (topology_is_dgpu(gpu_mem[gpu_mem_id].device_id)) {
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uintptr_t alt_base;
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uint64_t alt_size;
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int err;
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dgpu_mem_init(node_id, &gpu_mem[node_id].dgpu_aperture.base,
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&gpu_mem[node_id].dgpu_aperture.limit);
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set_dgpu_aperture(node_id, (uint64_t)gpu_mem[node_id].dgpu_aperture.base,
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(uint64_t)gpu_mem[node_id].dgpu_aperture.limit);
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gpu_mem[node_id].dgpu_aperture.align = TONGA_PAGE_SIZE;
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dgpu_mem_init(gpu_mem_id, &gpu_mem[gpu_mem_id].dgpu_aperture.base,
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&gpu_mem[gpu_mem_id].dgpu_aperture.limit);
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/* Set kernel process dgpu aperture. */
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set_dgpu_aperture(i, (uint64_t)gpu_mem[gpu_mem_id].dgpu_aperture.base,
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(uint64_t)gpu_mem[gpu_mem_id].dgpu_aperture.limit);
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gpu_mem[gpu_mem_id].dgpu_aperture.align = TONGA_PAGE_SIZE;
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/* Place GPUVM aperture after dGPU aperture
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* (FK: I think this is broken but leaving it for now) */
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gpu_mem[node_id].gpuvm_aperture.base = VOID_PTR_ADD(gpu_mem[node_id].dgpu_aperture.limit, 1);
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gpu_mem[node_id].gpuvm_aperture.limit = (void *)VOID_PTRS_SUB(gpu_mem[node_id].dgpu_aperture.limit,
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gpu_mem[node_id].dgpu_aperture.base);
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gpu_mem[node_id].gpuvm_aperture.limit = VOID_PTR_ADD(gpu_mem[node_id].gpuvm_aperture.limit,
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(unsigned long)gpu_mem[node_id].gpuvm_aperture.base);
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gpu_mem[node_id].gpuvm_aperture.align = TONGA_PAGE_SIZE;
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/* Place GPUVM aperture after dGPU aperture
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* (FK: I think this is broken but leaving it for now) */
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gpu_mem[gpu_mem_id].gpuvm_aperture.base = VOID_PTR_ADD(gpu_mem[gpu_mem_id].dgpu_aperture.limit, 1);
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gpu_mem[gpu_mem_id].gpuvm_aperture.limit = (void *)VOID_PTRS_SUB(gpu_mem[gpu_mem_id].dgpu_aperture.limit,
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gpu_mem[gpu_mem_id].dgpu_aperture.base);
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gpu_mem[gpu_mem_id].gpuvm_aperture.limit = VOID_PTR_ADD(gpu_mem[gpu_mem_id].gpuvm_aperture.limit,
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(unsigned long)gpu_mem[gpu_mem_id].gpuvm_aperture.base);
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gpu_mem[gpu_mem_id].gpuvm_aperture.align = TONGA_PAGE_SIZE;
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/* Use the first 1/4 of the dGPU aperture as
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* alternate aperture for coherent access.
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* Base and size must be 64KB aligned. */
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alt_base = (uintptr_t)gpu_mem[node_id].dgpu_aperture.base;
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alt_size = (VOID_PTRS_SUB(gpu_mem[node_id].dgpu_aperture.limit,
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gpu_mem[node_id].dgpu_aperture.base) + 1) >> 2;
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alt_base = (alt_base + 0xffff) & ~0xffffULL;
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alt_size = (alt_size + 0xffff) & ~0xffffULL;
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gpu_mem[node_id].dgpu_alt_aperture.base = (void *)alt_base;
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gpu_mem[node_id].dgpu_alt_aperture.limit = (void *)(alt_base + alt_size - 1);
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gpu_mem[node_id].dgpu_aperture.base = VOID_PTR_ADD(gpu_mem[node_id].dgpu_alt_aperture.limit, 1);
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err = fmm_set_memory_policy(gpu_id,
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KFD_IOC_CACHE_POLICY_NONCOHERENT,
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KFD_IOC_CACHE_POLICY_COHERENT,
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alt_base, alt_size);
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if (err != 0) {
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fprintf(stderr, "Error! Failed to set alt aperture for node %d\n", node_id);
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ret = HSAKMT_STATUS_ERROR;
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}
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gpu_mem[node_id].dgpu_alt_aperture.align = TONGA_PAGE_SIZE;
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/* Use the first 1/4 of the dGPU aperture as
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* alternate aperture for coherent access.
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* Base and size must be 64KB aligned. */
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alt_base = (uintptr_t)gpu_mem[gpu_mem_id].dgpu_aperture.base;
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alt_size = (VOID_PTRS_SUB(gpu_mem[gpu_mem_id].dgpu_aperture.limit,
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gpu_mem[gpu_mem_id].dgpu_aperture.base) + 1) >> 2;
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alt_base = (alt_base + 0xffff) & ~0xffffULL;
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alt_size = (alt_size + 0xffff) & ~0xffffULL;
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gpu_mem[gpu_mem_id].dgpu_alt_aperture.base = (void *)alt_base;
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gpu_mem[gpu_mem_id].dgpu_alt_aperture.limit = (void *)(alt_base + alt_size - 1);
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gpu_mem[gpu_mem_id].dgpu_aperture.base = VOID_PTR_ADD(gpu_mem[gpu_mem_id].dgpu_alt_aperture.limit, 1);
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err = fmm_set_memory_policy(gpu_mem[gpu_mem_id].gpu_id,
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KFD_IOC_CACHE_POLICY_NONCOHERENT,
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KFD_IOC_CACHE_POLICY_COHERENT,
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alt_base, alt_size);
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if (err != 0) {
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fprintf(stderr, "Error! Failed to set alt aperture for GPU [0x%x]\n", gpu_mem[gpu_mem_id].gpu_id);
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ret = HSAKMT_STATUS_ERROR;
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}
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gpu_mem[gpu_mem_id].dgpu_alt_aperture.align = TONGA_PAGE_SIZE;
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}
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}
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@@ -1197,7 +1225,7 @@ err:
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return ret;
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}
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static HSAKMT_STATUS dgpu_mem_init(uint8_t node_id, void **base, void **limit)
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static HSAKMT_STATUS dgpu_mem_init(uint32_t gpu_mem_id, void **base, void **limit)
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{
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bool found;
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HSAKMT_STATUS ret;
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@@ -1205,8 +1233,6 @@ static HSAKMT_STATUS dgpu_mem_init(uint8_t node_id, void **base, void **limit)
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HSAuint64 max_len, max_vm_limit;
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uint32_t max_vm_limit_in_gb;
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long long unsigned int temp;
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uint32_t gpu_id;
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HsaNodeProperties props;
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if (is_dgpu_mem_init) {
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if (base)
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@@ -1216,11 +1242,7 @@ static HSAKMT_STATUS dgpu_mem_init(uint8_t node_id, void **base, void **limit)
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return HSAKMT_STATUS_SUCCESS;
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}
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ret = topology_sysfs_get_node_props(node_id, &props, &gpu_id);
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if (ret != HSAKMT_STATUS_SUCCESS)
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return ret;
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max_len = props.LocalMemSize;
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max_len = gpu_mem[gpu_mem_id].local_mem_size;
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found = false;
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for (addr = (void *)TONGA_PAGE_SIZE, ret_addr = NULL;
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@@ -72,6 +72,7 @@ uint16_t get_device_id_by_gpu_id(HSAuint32 gpu_id);
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HSAKMT_STATUS topology_sysfs_get_gpu_id(uint32_t node_id, uint32_t *gpu_id);
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HSAKMT_STATUS topology_sysfs_get_node_props(uint32_t node_id, HsaNodeProperties *props, uint32_t *gpu_id);
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HSAKMT_STATUS topology_sysfs_get_system_props(HsaSystemProperties *props);
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bool topology_is_dgpu(uint16_t gpu_id);
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HSAuint32 PageSizeFromFlags(unsigned int pageSizeFlags);
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@@ -139,7 +139,7 @@ err:
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return ret;
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}
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static HSAKMT_STATUS
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HSAKMT_STATUS
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topology_sysfs_get_system_props(HsaSystemProperties *props) {
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FILE *fd;
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DIR *dirp;
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