P4 to Git Change 1250949 by gandryey@gera-w8 on 2016/03/24 12:06:49
SWDEV-90618 - cl_kernel_info_amd always returns 0 when working via HSAIL path - Allow null kernel creation for offline compilation Affected files ... ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpukernel.cpp#312 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuprogram.cpp#224 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuprogram.hpp#66 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuscsi.cpp#36 edit
Этот коммит содержится в:
foreman
@@ -3422,10 +3422,7 @@ HSAILKernel::init(amd::hsa::loader::Symbol *sym, bool finalize)
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}
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}
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// Allocate HW resources for the real program only
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if (!prog().isNull()) {
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aqlCreateHWInfo(sym);
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}
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aqlCreateHWInfo(sym);
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// Pull out metadata from the ELF
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size_t sizeOfArgList;
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@@ -2151,7 +2151,7 @@ HSAILProgram::linkImpl(amd::option::Options* options)
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// ACL_TYPE_CG stage is not performed for offline compilation
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hsa_agent_t agent;
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agent.handle = 1;
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if (!isNull() && hsaLoad) {
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if (hsaLoad) {
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executable_ = loader_->CreateExecutable(HSA_PROFILE_FULL, NULL);
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if (executable_ == NULL) {
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buildLog_ += "Error: Executable for AMD HSA Code Object isn't created.\n";
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@@ -2176,7 +2176,7 @@ HSAILProgram::linkImpl(amd::option::Options* options)
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buildLog_ += "Error: Querying of kernel names size from the binary failed.\n";
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return false;
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}
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if (!isNull() && kernelNamesSize > 0) {
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if (kernelNamesSize > 0) {
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char* kernelNames = new char[kernelNamesSize];
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errorCode = aclQueryInfo(dev().hsaCompiler(), binaryElf_, RT_KERNEL_NAMES, NULL, kernelNames, &kernelNamesSize);
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if (errorCode != ACL_SUCCESS) {
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@@ -2447,8 +2447,10 @@ void* ORCAHSALoaderContext::SegmentAddress(amdgpu_hsa_elf_segment_t segment,
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case AMDGPU_HSA_SEGMENT_GLOBAL_PROGRAM:
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case AMDGPU_HSA_SEGMENT_GLOBAL_AGENT:
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case AMDGPU_HSA_SEGMENT_READONLY_AGENT: {
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gpu::Memory *gpuMem = reinterpret_cast<gpu::Memory*>(seg);
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return reinterpret_cast<void*>(gpuMem->vmAddress() + offset);
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if (!program_->isNull()) {
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gpu::Memory *gpuMem = reinterpret_cast<gpu::Memory*>(seg);
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return reinterpret_cast<void*>(gpuMem->vmAddress() + offset);
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}
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}
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case AMDGPU_HSA_SEGMENT_CODE_AGENT: return (char*) seg + offset;
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default:
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@@ -2487,7 +2489,7 @@ hsa_status_t ORCAHSALoaderContext::SamplerCreate(
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case HSA_EXT_SAMPLER_ADDRESSING_MODE_CLAMP_TO_BORDER: state |= amd::Sampler::StateAddressClamp; break;
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case HSA_EXT_SAMPLER_ADDRESSING_MODE_REPEAT: state |= amd::Sampler::StateAddressRepeat; break;
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case HSA_EXT_SAMPLER_ADDRESSING_MODE_MIRRORED_REPEAT: state |= amd::Sampler::StateAddressMirroredRepeat; break;
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case HSA_EXT_SAMPLER_ADDRESSING_MODE_UNDEFINED: state |= amd::Sampler::StateAddressNone; break;
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case HSA_EXT_SAMPLER_ADDRESSING_MODE_UNDEFINED: state |= amd::Sampler::StateAddressNone; break;
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default:
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assert(false);
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return HSA_STATUS_ERROR_INVALID_ARGUMENT;
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@@ -2540,6 +2542,10 @@ void* ORCAHSALoaderContext::GpuMemAlloc(size_t size, size_t align, bool zero) {
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assert(size);
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assert(align);
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assert(sizeof(void*) == 8 || sizeof(void*) == 4);
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if (program_->isNull()) {
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return new char [size];
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}
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gpu::Memory* mem = new gpu::Memory(program_->dev(), amd::alignUp(size, align));
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if (!mem || !mem->create(gpu::Resource::Local)) {
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delete mem;
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@@ -2562,10 +2568,24 @@ bool ORCAHSALoaderContext::GpuMemCopy(void *dst, size_t offset, const void *src,
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if (0 == size) {
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return true;
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}
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if (program_->isNull()) {
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memcpy(reinterpret_cast<address>(dst) + offset, src, size);
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return true;
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}
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assert(program_->dev().xferQueue());
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gpu::Memory* mem = reinterpret_cast<gpu::Memory*>(dst);
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return program_->dev().xferMgr().writeBuffer(src, *mem, amd::Coord3D(offset), amd::Coord3D(size), true);
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return true;
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}
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void ORCAHSALoaderContext::GpuMemFree(void *ptr, size_t size)
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{
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if (program_->isNull()) {
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delete [] reinterpret_cast<char*>(ptr);
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}
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else {
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delete reinterpret_cast<gpu::Memory*>(ptr);
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}
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}
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} // namespace gpu
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@@ -480,9 +480,7 @@ private:
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bool GpuMemCopy(void *dst, size_t offset, const void *src, size_t size);
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void GpuMemFree(void *ptr, size_t size = 0) {
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delete reinterpret_cast<gpu::Memory*>(ptr);
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}
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void GpuMemFree(void *ptr, size_t size = 0);
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ORCAHSALoaderContext(const ORCAHSALoaderContext &c);
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@@ -153,26 +153,27 @@ HSAILKernel::aqlCreateHWInfo(amd::hsa::loader::Symbol *sym)
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if (!sym->GetInfo(HSA_EXT_EXECUTABLE_SYMBOL_INFO_KERNEL_OBJECT_ALIGN, reinterpret_cast<void*>(&akc_align))) {
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return false;
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}
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code_ = new gpu::Memory(dev(), amd::alignUp(codeSize_, akc_align));
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// Initialize kernel ISA code
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if (code_ && code_->create(Resource::Shader)) {
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address cpuCodePtr = static_cast<address>(code_->map(NULL, Resource::WriteOnly));
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// Copy only amd_kernel_code_t
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memcpy(cpuCodePtr, reinterpret_cast<address>(akc), codeSize_);
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code_->unmap(NULL);
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}
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else {
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LogError("Failed to allocate ISA code!");
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return false;
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// Allocate HW resources for the real program only
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if (!prog().isNull()) {
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code_ = new gpu::Memory(dev(), amd::alignUp(codeSize_, akc_align));
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// Initialize kernel ISA code
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if (code_ && code_->create(Resource::Shader)) {
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address cpuCodePtr = static_cast<address>(code_->map(NULL, Resource::WriteOnly));
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// Copy only amd_kernel_code_t
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memcpy(cpuCodePtr, reinterpret_cast<address>(akc), codeSize_);
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code_->unmap(NULL);
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}
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else {
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LogError("Failed to allocate ISA code!");
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return false;
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}
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}
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assert((akc->workitem_private_segment_byte_size & 3) == 0 &&
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"Scratch must be DWORD aligned");
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workGroupInfo_.scratchRegs_ =
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amd::alignUp(akc->workitem_private_segment_byte_size, 16) / sizeof(uint);
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workGroupInfo_.availableSGPRs_ = dev().gslCtx()->getNumSGPRsAvailable();
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workGroupInfo_.availableVGPRs_ = dev().gslCtx()->getNumVGPRsAvailable();
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workGroupInfo_.preferredSizeMultiple_ = dev().getAttribs().wavefrontSize;
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workGroupInfo_.privateMemSize_ = akc->workitem_private_segment_byte_size;
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workGroupInfo_.availableLDSSize_ = dev().info().localMemSize_;
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workGroupInfo_.localMemSize_ =
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@@ -180,8 +181,19 @@ HSAILKernel::aqlCreateHWInfo(amd::hsa::loader::Symbol *sym)
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workGroupInfo_.usedSGPRs_ = akc->wavefront_sgpr_count;
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workGroupInfo_.usedStackSize_ = 0;
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workGroupInfo_.usedVGPRs_ = akc->workitem_vgpr_count;
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workGroupInfo_.wavefrontPerSIMD_ = dev().getAttribs().wavefrontSize;
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if (!prog().isNull()) {
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workGroupInfo_.availableSGPRs_ = dev().gslCtx()->getNumSGPRsAvailable();
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workGroupInfo_.availableVGPRs_ = dev().gslCtx()->getNumVGPRsAvailable();
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workGroupInfo_.preferredSizeMultiple_ = dev().getAttribs().wavefrontSize;
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workGroupInfo_.wavefrontPerSIMD_ = dev().getAttribs().wavefrontSize;
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}
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else {
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workGroupInfo_.availableSGPRs_ = 104;
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workGroupInfo_.availableVGPRs_ = 256;
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workGroupInfo_.preferredSizeMultiple_ =
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workGroupInfo_.wavefrontPerSIMD_ = 64;
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}
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return true;
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}
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} // namespace gpu
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