Disable CPU cache info in non-x86
CPU cache information reported by Thunk topology is obtained from cpuid
instruction. This instruction only applies to X86 systems. It can cause
compile errors on non-X86 platforms. This patch temporarily disables CPU
cache functions in topology for non-X86 platforms in order to compile.
Change-Id: If86671817b0d036cb324eebf3f354682bfb75856
[ROCm/ROCR-Runtime commit: 660a6ebbd4]
This commit is contained in:
Amber Lin
@@ -252,6 +252,7 @@ static int num_subdirs(char *dirpath, char *prefix)
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return count;
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}
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#if defined(__x86_64__) || defined(__i386__)
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/* cpuid instruction returns processor identification and feature information
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* to the EAX, EBX, ECX, and EDX registers, as determined by input entered in
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* EAX (in some cases, ECX as well).
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@@ -308,6 +309,118 @@ static int get_count_order(unsigned int count)
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return bit;
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}
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/* cpuid_find_num_cache_leaves - Use cpuid instruction to find out how many
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* cache leaves the CPU has.
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* @op - cpuid opcode to get cache information
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* Return - the number of cache leaves
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*/
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static int cpuid_find_num_cache_leaves(uint32_t op)
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{
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union _cpuid_leaf_eax eax;
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union _cpuid_leaf_ebx ebx;
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unsigned int ecx;
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unsigned int edx;
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int idx = -1;
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do {
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++idx;
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cpuid_count(op, idx, &eax.full, &ebx.full, &ecx, &edx);
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} while (eax.split.type != CACHE_TYPE_NULL);
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return idx;
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}
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/* cpuid_get_cpu_cache_info - Use cpuid instruction to get cache information
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* @op - cpuid opcode to get cache information
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* @cpu_ci - this parameter is an input and also an output.
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* [IN] cpu_ci->num_caches: the number of caches of this cpu
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* [OUT] cpu_ci->cache_info: to store cache info collected
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*/
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static void cpuid_get_cpu_cache_info(uint32_t op, cpu_cacheinfo_t *cpu_ci)
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{
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union _cpuid_leaf_eax eax;
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union _cpuid_leaf_ebx ebx;
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uint32_t ecx;
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uint32_t edx;
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uint32_t index;
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cacheinfo_t *this_leaf;
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for (index = 0; index < cpu_ci->num_caches; index++) {
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cpuid_count(op, index, &eax.full, &ebx.full, &ecx, &edx);
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this_leaf = cpu_ci->cache_info + index;
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this_leaf->hsa_cache_prop.ProcessorIdLow = cpu_ci->apicid;
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this_leaf->num_threads_sharing =
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eax.split.num_threads_sharing + 1;
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this_leaf->hsa_cache_prop.CacheLevel = eax.split.level;
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this_leaf->hsa_cache_prop.CacheType.ui32.CPU = 1;
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if (eax.split.type & CACHE_TYPE_DATA )
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this_leaf->hsa_cache_prop.CacheType.ui32.Data = 1;
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if (eax.split.type & CACHE_TYPE_INST )
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this_leaf->hsa_cache_prop.CacheType.ui32.Instruction = 1;
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this_leaf->hsa_cache_prop.CacheLineSize =
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ebx.split.coherency_line_size + 1;
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this_leaf->hsa_cache_prop.CacheAssociativity =
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ebx.split.ways_of_associativity + 1;
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this_leaf->hsa_cache_prop.CacheLinesPerTag =
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ebx.split.physical_line_partition + 1;
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this_leaf->hsa_cache_prop.CacheSize = (ecx + 1) *
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(ebx.split.coherency_line_size + 1) *
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(ebx.split.physical_line_partition + 1) *
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(ebx.split.ways_of_associativity + 1);
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}
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}
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/* find_cpu_cache_siblings - In the cache list, some caches may be listed more
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* than once if they are shared by multiple CPUs. Identify the cache's CPU
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* siblings, record it to SiblingMap[], then remove the duplicated cache by
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* changing the cache size to 0.
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*/
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static void find_cpu_cache_siblings(cpu_cacheinfo_t *cpu_ci_list)
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{
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cacheinfo_t *this_leaf, *leaf2;
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uint32_t n, j, idx_msb, apicid1, apicid2;
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cpu_cacheinfo_t *this_cpu, *cpu2;
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uint32_t index;
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for (n = 0; n < cpu_ci_list->len; n++) {
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this_cpu = cpu_ci_list + n;
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for (index = 0; index < this_cpu->num_caches; index++) {
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this_leaf = this_cpu->cache_info + index;
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/* CacheSize 0 means an invalid cache */
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if (!this_leaf->hsa_cache_prop.CacheSize)
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continue;
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if (this_leaf->num_threads_sharing == 1) // no siblings
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continue;
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idx_msb = get_count_order(this_leaf->num_threads_sharing);
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for (j = n + 1; j < cpu_ci_list->len; j++) {
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cpu2 = cpu_ci_list + j;
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leaf2 = cpu2->cache_info + index;
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apicid1 = this_leaf->hsa_cache_prop.ProcessorIdLow;
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apicid2 = leaf2->hsa_cache_prop.ProcessorIdLow;
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if ((apicid2 >> idx_msb) != (apicid1 >> idx_msb))
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continue;
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/* A sibling leaf is found. Cache properties
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* use ProcIdLow as offset to represent siblings
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* in SiblingMap, so keep the lower apicid and
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* delete the other by changing CacheSize to 0.
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*/
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if (apicid1 < apicid2) {
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this_leaf->hsa_cache_prop.SiblingMap[0] = 1;
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this_leaf->hsa_cache_prop.SiblingMap[apicid2 - apicid1] = 1;
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leaf2->hsa_cache_prop.CacheSize = 0;
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cpu2->num_duplicated_caches++;
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}
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else {
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leaf2->hsa_cache_prop.SiblingMap[0] = 1;
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leaf2->hsa_cache_prop.SiblingMap[apicid1 - apicid2] = 1;
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this_leaf->hsa_cache_prop.CacheSize = 0;
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this_cpu->num_duplicated_caches++;
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}
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}
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}
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}
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}
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#endif /* X86 platform */
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static HSAKMT_STATUS
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topology_sysfs_get_generation(uint32_t *gen) {
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FILE *fd;
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@@ -765,117 +878,7 @@ err1:
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return ret;
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}
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/* cpuid_find_num_cache_leaves - Use cpuid instruction to find out how many
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* cache leaves the CPU has.
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* @op - cpuid opcode to get cache information
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* Return - the number of cache leaves
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*/
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static int cpuid_find_num_cache_leaves(uint32_t op)
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{
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union _cpuid_leaf_eax eax;
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union _cpuid_leaf_ebx ebx;
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unsigned int ecx;
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unsigned int edx;
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int idx = -1;
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do {
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++idx;
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cpuid_count(op, idx, &eax.full, &ebx.full, &ecx, &edx);
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} while (eax.split.type != CACHE_TYPE_NULL);
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return idx;
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}
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/* cpuid_get_cpu_cache_info - Use cpuid instruction to get cache information
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* @op - cpuid opcode to get cache information
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* @cpu_ci - this parameter is an input and also an output.
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* [IN] cpu_ci->num_caches: the number of caches of this cpu
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* [OUT] cpu_ci->cache_info: to store cache info collected
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*/
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static void cpuid_get_cpu_cache_info(uint32_t op, cpu_cacheinfo_t *cpu_ci)
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{
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union _cpuid_leaf_eax eax;
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union _cpuid_leaf_ebx ebx;
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uint32_t ecx;
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uint32_t edx;
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uint32_t index;
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cacheinfo_t *this_leaf;
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for (index = 0; index < cpu_ci->num_caches; index++) {
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cpuid_count(op, index, &eax.full, &ebx.full, &ecx, &edx);
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this_leaf = cpu_ci->cache_info + index;
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this_leaf->hsa_cache_prop.ProcessorIdLow = cpu_ci->apicid;
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this_leaf->num_threads_sharing =
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eax.split.num_threads_sharing + 1;
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this_leaf->hsa_cache_prop.CacheLevel = eax.split.level;
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this_leaf->hsa_cache_prop.CacheType.ui32.CPU = 1;
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if (eax.split.type & CACHE_TYPE_DATA )
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this_leaf->hsa_cache_prop.CacheType.ui32.Data = 1;
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if (eax.split.type & CACHE_TYPE_INST )
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this_leaf->hsa_cache_prop.CacheType.ui32.Instruction = 1;
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this_leaf->hsa_cache_prop.CacheLineSize =
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ebx.split.coherency_line_size + 1;
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this_leaf->hsa_cache_prop.CacheAssociativity =
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ebx.split.ways_of_associativity + 1;
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this_leaf->hsa_cache_prop.CacheLinesPerTag =
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ebx.split.physical_line_partition + 1;
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this_leaf->hsa_cache_prop.CacheSize = (ecx + 1) *
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(ebx.split.coherency_line_size + 1) *
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(ebx.split.physical_line_partition + 1) *
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(ebx.split.ways_of_associativity + 1);
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}
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}
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/* find_cpu_cache_siblings - In the cache list, some caches may be listed more
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* than once if they are shared by multiple CPUs. Identify the cache's CPU
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* siblings, record it to SiblingMap[], then remove the duplicated cache by
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* changing the cache size to 0.
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*/
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static void find_cpu_cache_siblings(cpu_cacheinfo_t *cpu_ci_list)
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{
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cacheinfo_t *this_leaf, *leaf2;
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uint32_t n, j, idx_msb, apicid1, apicid2;
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cpu_cacheinfo_t *this_cpu, *cpu2;
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uint32_t index;
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for (n = 0; n < cpu_ci_list->len; n++) {
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this_cpu = cpu_ci_list + n;
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for (index = 0; index < this_cpu->num_caches; index++) {
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this_leaf = this_cpu->cache_info + index;
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/* CacheSize 0 means an invalid cache */
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if (!this_leaf->hsa_cache_prop.CacheSize)
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continue;
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if (this_leaf->num_threads_sharing == 1) // no siblings
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continue;
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idx_msb = get_count_order(this_leaf->num_threads_sharing);
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for (j = n + 1; j < cpu_ci_list->len; j++) {
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cpu2 = cpu_ci_list + j;
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leaf2 = cpu2->cache_info + index;
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apicid1 = this_leaf->hsa_cache_prop.ProcessorIdLow;
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apicid2 = leaf2->hsa_cache_prop.ProcessorIdLow;
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if ((apicid2 >> idx_msb) != (apicid1 >> idx_msb))
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continue;
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/* A sibling leaf is found. Cache properties
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* use ProcIdLow as offset to represent siblings
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* in SiblingMap, so keep the lower apicid and
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* delete the other by changing CacheSize to 0.
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*/
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if (apicid1 < apicid2) {
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this_leaf->hsa_cache_prop.SiblingMap[0] = 1;
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this_leaf->hsa_cache_prop.SiblingMap[apicid2 - apicid1] = 1;
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leaf2->hsa_cache_prop.CacheSize = 0;
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cpu2->num_duplicated_caches++;
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}
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else {
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leaf2->hsa_cache_prop.SiblingMap[0] = 1;
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leaf2->hsa_cache_prop.SiblingMap[apicid1 - apicid2] = 1;
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this_leaf->hsa_cache_prop.CacheSize = 0;
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this_cpu->num_duplicated_caches++;
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}
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}
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}
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}
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}
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#if defined(__x86_64__) || defined(__i386__)
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/* topology_destroy_temp_cpu_cache_list - Free the memory allocated in
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* topology_create_temp_cpu_cache_list().
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*/
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@@ -1043,6 +1046,23 @@ topology_get_cpu_cache_props(node_t *tbl, cpu_cacheinfo_t *cpu_ci_list)
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exit:
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return ret;
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}
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#else /* not X86 */
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static void topology_destroy_temp_cpu_cache_list(void *temp_cpu_ci_list)
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{
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}
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static HSAKMT_STATUS
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topology_create_temp_cpu_cache_list(void **temp_cpu_ci_list)
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{
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return HSAKMT_STATUS_SUCCESS;
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}
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static HSAKMT_STATUS
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topology_get_cpu_cache_props(node_t *tbl, cpu_cacheinfo_t *cpu_ci_list)
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{
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return HSAKMT_STATUS_SUCCESS;
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}
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#endif
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static HSAKMT_STATUS
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topology_sysfs_get_cache_props(uint32_t node_id, uint32_t cache_id, HsaCacheProperties *props) {
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