[SPM] Clean up obsolete SPM logics and refine some SPM-related definition (#157)
* Clean up obsolete SPM logics * Add PERFCOUNTER_SELECT1 to CounterRegInfo * Add RLC_SPM_PERFMON_SAMPLE_DELAY_MAX
This commit is contained in:
Ma, Bing
GitHub
@@ -31,124 +31,140 @@ namespace gfx10 {
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*/
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static const CounterRegInfo CpcCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER0_HI)},
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REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER0_HI),
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REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER1_HI)}};
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REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER1_HI),
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REG_32B_NULL}};
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/*
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* CPF
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*/
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static const CounterRegInfo CpfCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER0_HI)},
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REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER0_HI),
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REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER1_HI)}};
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REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER1_HI),
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REG_32B_NULL}};
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/*
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* GDS
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*/
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static const CounterRegInfo GdsCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER0_HI)},
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REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER0_HI),
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REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER1_HI)},
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REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER1_HI),
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REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER2_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER2_HI)},
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REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER2_HI),
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REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER3_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER3_HI)}};
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REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER3_HI),
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REG_32B_NULL}};
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/*
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* GRBM
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*/
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static const CounterRegInfo GrbmCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER0_HI)},
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REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER0_HI),
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REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER1_HI)}};
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REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER1_HI),
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REG_32B_NULL}};
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/*
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* GRBM_SE
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*/
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static const CounterRegInfo GrbmSeCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, mmGRBM_SE0_PERFCOUNTER_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmGRBM_SE0_PERFCOUNTER_LO),
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REG_32B_ADDR(GC, 0, mmGRBM_SE0_PERFCOUNTER_HI)},
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REG_32B_ADDR(GC, 0, mmGRBM_SE0_PERFCOUNTER_LO), REG_32B_ADDR(GC, 0, mmGRBM_SE0_PERFCOUNTER_HI),
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REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmGRBM_SE1_PERFCOUNTER_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmGRBM_SE1_PERFCOUNTER_LO),
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REG_32B_ADDR(GC, 0, mmGRBM_SE1_PERFCOUNTER_HI)},
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REG_32B_ADDR(GC, 0, mmGRBM_SE1_PERFCOUNTER_LO), REG_32B_ADDR(GC, 0, mmGRBM_SE1_PERFCOUNTER_HI),
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REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmGRBM_SE2_PERFCOUNTER_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmGRBM_SE2_PERFCOUNTER_LO),
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REG_32B_ADDR(GC, 0, mmGRBM_SE2_PERFCOUNTER_HI)},
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REG_32B_ADDR(GC, 0, mmGRBM_SE2_PERFCOUNTER_LO), REG_32B_ADDR(GC, 0, mmGRBM_SE2_PERFCOUNTER_HI),
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REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmGRBM_SE3_PERFCOUNTER_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmGRBM_SE3_PERFCOUNTER_LO),
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REG_32B_ADDR(GC, 0, mmGRBM_SE3_PERFCOUNTER_HI)}};
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REG_32B_ADDR(GC, 0, mmGRBM_SE3_PERFCOUNTER_LO), REG_32B_ADDR(GC, 0, mmGRBM_SE3_PERFCOUNTER_HI),
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REG_32B_NULL}};
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/*
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* SPI
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*/
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static const CounterRegInfo SpiCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER0_HI)},
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REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER0_HI),
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REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER1_HI)},
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REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER1_HI),
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REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER2_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER2_HI)},
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REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER2_HI),
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REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER3_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER3_HI)},
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REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER3_HI),
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REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER4_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER4_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER4_HI)},
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REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER4_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER4_HI),
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REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER5_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER5_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER5_HI)}};
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REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER5_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER5_HI),
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REG_32B_NULL}};
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/*
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* SQ
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*/
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static const CounterRegInfo SqCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER0_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER0_HI)},
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER0_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER1_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER1_HI)},
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER1_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER2_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER2_HI)},
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER2_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER3_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER3_HI)},
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER3_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER4_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER4_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER4_HI)},
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER4_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER4_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER5_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER5_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER5_HI)},
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER5_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER5_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER6_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER6_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER6_HI)},
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER6_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER6_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER7_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER7_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER7_HI)},
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER7_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER7_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER8_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER8_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER8_HI)},
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER8_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER8_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER9_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER9_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER9_HI)},
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER9_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER9_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER10_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER10_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER10_HI)},
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER10_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER10_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER11_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER11_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER11_HI)},
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER11_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER11_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER12_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER12_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER12_HI)},
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER12_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER12_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER13_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER13_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER13_HI)},
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER13_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER13_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER14_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER14_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER14_HI)},
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER14_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER14_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER15_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER15_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER15_HI)}};
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REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER15_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER15_HI), REG_32B_NULL}};
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/*
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* SX
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*/
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static const CounterRegInfo SxCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER0_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER0_HI)},
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REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER0_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER1_HI)},
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REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER1_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER2_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER2_HI)},
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REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER2_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER3_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER3_HI)}};
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REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER3_HI), REG_32B_NULL}};
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/*
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* GCEA
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@@ -156,10 +172,10 @@ static const CounterRegInfo SxCounterRegAddr[] = {
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static const CounterRegInfo GceaCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER0_CFG),
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REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER_RSLT_CNTL), REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER_LO),
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REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER_HI)},
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REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER1_CFG),
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REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER_RSLT_CNTL), REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER_LO),
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REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER_HI)}};
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REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER_HI), REG_32B_NULL}};
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// Define GFX10 specific blocks table entries like GC caches blocks
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/*
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@@ -167,35 +183,35 @@ static const CounterRegInfo GceaCounterRegAddr[] = {
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*/
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static const CounterRegInfo GcrCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, mmGCR_PERFCOUNTER0_SELECT), REG_32B_ADDR(GC, 0, mmGCR_GENERAL_CNTL),
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REG_32B_ADDR(GC, 0, mmGCR_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmGCR_PERFCOUNTER0_HI)},
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REG_32B_ADDR(GC, 0, mmGCR_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmGCR_PERFCOUNTER0_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmGCR_PERFCOUNTER1_SELECT), REG_32B_ADDR(GC, 0, mmGCR_GENERAL_CNTL),
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REG_32B_ADDR(GC, 0, mmGCR_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmGCR_PERFCOUNTER1_HI)}};
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REG_32B_ADDR(GC, 0, mmGCR_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmGCR_PERFCOUNTER1_HI), REG_32B_NULL}};
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/*
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* GL1A
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*/
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static const CounterRegInfo Gl1aCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmGL1A_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmGL1A_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmGL1A_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmGL1A_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmGL1A_PERFCOUNTER0_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmGL1A_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmGL1A_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmGL1A_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmGL1A_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmGL1A_PERFCOUNTER1_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmGL1A_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmGL1A_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmGL1A_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmGL1A_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmGL1A_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmGL1A_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmGL1A_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmGL1A_PERFCOUNTER3_HI)}};
|
||||
REG_32B_ADDR(GC, 0, mmGL1A_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmGL1A_PERFCOUNTER3_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* GL1C
|
||||
*/
|
||||
static const CounterRegInfo Gl1cCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmGL1C_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmGL1C_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmGL1C_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmGL1C_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmGL1C_PERFCOUNTER0_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmGL1C_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmGL1C_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmGL1C_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmGL1C_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmGL1C_PERFCOUNTER1_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmGL1C_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmGL1C_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmGL1C_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmGL1C_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmGL1C_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmGL1C_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmGL1C_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmGL1C_PERFCOUNTER3_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmGL1C_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmGL1C_PERFCOUNTER3_HI), REG_32B_NULL},
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -203,13 +219,13 @@ static const CounterRegInfo Gl1cCounterRegAddr[] = {
|
||||
*/
|
||||
static const CounterRegInfo Gl2aCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmGL2A_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmGL2A_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmGL2A_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmGL2A_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmGL2A_PERFCOUNTER0_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmGL2A_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmGL2A_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmGL2A_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmGL2A_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmGL2A_PERFCOUNTER1_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmGL2A_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmGL2A_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmGL2A_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmGL2A_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmGL2A_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmGL2A_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmGL2A_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmGL2A_PERFCOUNTER3_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmGL2A_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmGL2A_PERFCOUNTER3_HI), REG_32B_NULL},
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -217,13 +233,13 @@ static const CounterRegInfo Gl2aCounterRegAddr[] = {
|
||||
*/
|
||||
static const CounterRegInfo Gl2cCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmGL2C_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmGL2C_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmGL2C_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmGL2C_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmGL2C_PERFCOUNTER0_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmGL2C_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmGL2C_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmGL2C_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmGL2C_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmGL2C_PERFCOUNTER1_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmGL2C_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmGL2C_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmGL2C_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmGL2C_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmGL2C_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmGL2C_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmGL2C_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmGL2C_PERFCOUNTER3_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmGL2C_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmGL2C_PERFCOUNTER3_HI), REG_32B_NULL},
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -231,9 +247,9 @@ static const CounterRegInfo Gl2cCounterRegAddr[] = {
|
||||
*/
|
||||
static const CounterRegInfo GusCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmGUS_PERFCOUNTER0_CFG), REG_32B_ADDR(GC, 0, mmGUS_PERFCOUNTER_RSLT_CNTL),
|
||||
REG_32B_ADDR(GC, 0, mmGUS_PERFCOUNTER_LO), REG_32B_ADDR(GC, 0, mmGUS_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmGUS_PERFCOUNTER_LO), REG_32B_ADDR(GC, 0, mmGUS_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmGUS_PERFCOUNTER1_CFG), REG_32B_ADDR(GC, 0, mmGUS_PERFCOUNTER_RSLT_CNTL),
|
||||
REG_32B_ADDR(GC, 0, mmGUS_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmGUS_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmGUS_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmGUS_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -241,9 +257,9 @@ static const CounterRegInfo GusCounterRegAddr[] = {
|
||||
*/
|
||||
static const CounterRegInfo TaCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER0_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER1_HI)}};
|
||||
REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER1_HI), REG_32B_NULL}};
|
||||
|
||||
// Counter block CPC
|
||||
static const GpuBlockInfo CpcCounterBlockInfo = {
|
||||
@@ -255,8 +271,7 @@ static const GpuBlockInfo CpcCounterBlockInfo = {
|
||||
CpcCounterRegAddr,
|
||||
gfx10_cntx_prim::select_value_CPC_PERFCOUNTER0_SELECT,
|
||||
CounterBlockDfltAttr | CounterBlockSpmGlobalAttr,
|
||||
NULL /*CpcBlockDelayInfo*/,
|
||||
SPM_GLOBAL_BLOCK_NAME_CPC};
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block CPF
|
||||
static const GpuBlockInfo CpfCounterBlockInfo = {
|
||||
"CPF",
|
||||
@@ -267,8 +282,7 @@ static const GpuBlockInfo CpfCounterBlockInfo = {
|
||||
CpfCounterRegAddr,
|
||||
gfx10_cntx_prim::select_value_CPF_PERFCOUNTER0_SELECT,
|
||||
CounterBlockDfltAttr | CounterBlockSpmGlobalAttr,
|
||||
NULL /*CpfBlockDelayInfo*/,
|
||||
SPM_GLOBAL_BLOCK_NAME_CPF};
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block GDS
|
||||
static const GpuBlockInfo GdsCounterBlockInfo = {
|
||||
"GDS",
|
||||
@@ -279,8 +293,7 @@ static const GpuBlockInfo GdsCounterBlockInfo = {
|
||||
GdsCounterRegAddr,
|
||||
gfx10_cntx_prim::select_value_GDS_PERFCOUNTER0_SELECT,
|
||||
CounterBlockDfltAttr | CounterBlockSpmGlobalAttr,
|
||||
NULL /*GdsBlockDelayInfo*/,
|
||||
SPM_GLOBAL_BLOCK_NAME_GDS};
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block GRBM
|
||||
static const GpuBlockInfo GrbmCounterBlockInfo = {
|
||||
"GRBM",
|
||||
@@ -290,7 +303,8 @@ static const GpuBlockInfo GrbmCounterBlockInfo = {
|
||||
GrbmCounterBlockNumCounters,
|
||||
GrbmCounterRegAddr,
|
||||
gfx10_cntx_prim::select_value_GRBM_PERFCOUNTER0_SELECT,
|
||||
CounterBlockDfltAttr | CounterBlockGRBMAttr};
|
||||
CounterBlockDfltAttr | CounterBlockGRBMAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block GRBMSE
|
||||
static const GpuBlockInfo GrbmSeCounterBlockInfo = {
|
||||
"GRBM_SE",
|
||||
@@ -300,7 +314,8 @@ static const GpuBlockInfo GrbmSeCounterBlockInfo = {
|
||||
GrbmSeCounterBlockNumCounters,
|
||||
GrbmSeCounterRegAddr,
|
||||
gfx10_cntx_prim::select_value_GRBM_SE0_PERFCOUNTER_SELECT,
|
||||
CounterBlockDfltAttr};
|
||||
CounterBlockDfltAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block SPI
|
||||
static const GpuBlockInfo SpiCounterBlockInfo = {
|
||||
"SPI",
|
||||
@@ -311,8 +326,7 @@ static const GpuBlockInfo SpiCounterBlockInfo = {
|
||||
SpiCounterRegAddr,
|
||||
gfx10_cntx_prim::select_value_SPI_PERFCOUNTER0_SELECT,
|
||||
CounterBlockSeAttr | CounterBlockSPIAttr,
|
||||
NULL /*SpiBlockDelayInfo*/,
|
||||
SPM_SE_BLOCK_NAME_SPI};
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block SQ
|
||||
static const GpuBlockInfo SqCounterBlockInfo = {"SQ",
|
||||
SqCounterBlockId,
|
||||
@@ -322,8 +336,7 @@ static const GpuBlockInfo SqCounterBlockInfo = {"SQ",
|
||||
SqCounterRegAddr,
|
||||
gfx10_cntx_prim::sq_select_value,
|
||||
CounterBlockSeAttr | CounterBlockSqAttr,
|
||||
NULL,
|
||||
SPM_SE_BLOCK_NAME_SQG};
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block SX
|
||||
static const GpuBlockInfo SxCounterBlockInfo = {
|
||||
"SX",
|
||||
@@ -334,8 +347,7 @@ static const GpuBlockInfo SxCounterBlockInfo = {
|
||||
SxCounterRegAddr,
|
||||
gfx10_cntx_prim::select_value_SX_PERFCOUNTER0_SELECT,
|
||||
CounterBlockSeAttr | CounterBlockCleanAttr,
|
||||
NULL /*SxBlockDelayInfo*/,
|
||||
SPM_SE_BLOCK_NAME_SX};
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block GCEA
|
||||
static const GpuBlockInfo GceaCounterBlockInfo = {
|
||||
"GCEA",
|
||||
@@ -345,7 +357,8 @@ static const GpuBlockInfo GceaCounterBlockInfo = {
|
||||
GceaCounterBlockNumCounters,
|
||||
GceaCounterRegAddr,
|
||||
gfx10_cntx_prim::mc_select_value_GCEA_PERFCOUNTER0_CFG,
|
||||
CounterBlockMcAttr};
|
||||
CounterBlockMcAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block GL1A
|
||||
static const GpuBlockInfo Gl1aCounterBlockInfo = {
|
||||
"GL1A",
|
||||
@@ -355,7 +368,8 @@ static const GpuBlockInfo Gl1aCounterBlockInfo = {
|
||||
Gl1aCounterBlockNumCounters,
|
||||
Gl1aCounterRegAddr,
|
||||
gfx10_cntx_prim::select_value_TCP_PERFCOUNTER0_SELECT,
|
||||
CounterBlockSeAttr | CounterBlockSaAttr | CounterBlockTcAttr};
|
||||
CounterBlockSeAttr | CounterBlockSaAttr | CounterBlockTcAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block GL1C
|
||||
static const GpuBlockInfo Gl1cCounterBlockInfo = {
|
||||
"GL1C",
|
||||
@@ -365,7 +379,8 @@ static const GpuBlockInfo Gl1cCounterBlockInfo = {
|
||||
Gl1cCounterBlockNumCounters,
|
||||
Gl1cCounterRegAddr,
|
||||
gfx10_cntx_prim::select_value_TCP_PERFCOUNTER0_SELECT,
|
||||
CounterBlockSeAttr | CounterBlockSaAttr | CounterBlockTcAttr};
|
||||
CounterBlockSeAttr | CounterBlockSaAttr | CounterBlockTcAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block GL2A
|
||||
static const GpuBlockInfo Gl2aCounterBlockInfo = {
|
||||
"GL2A",
|
||||
@@ -375,7 +390,8 @@ static const GpuBlockInfo Gl2aCounterBlockInfo = {
|
||||
Gl2aCounterBlockNumCounters,
|
||||
Gl2aCounterRegAddr,
|
||||
gfx10_cntx_prim::select_value_TCP_PERFCOUNTER0_SELECT,
|
||||
CounterBlockTcAttr};
|
||||
CounterBlockTcAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block GL2C
|
||||
static const GpuBlockInfo Gl2cCounterBlockInfo = {
|
||||
"GL2C",
|
||||
@@ -385,7 +401,8 @@ static const GpuBlockInfo Gl2cCounterBlockInfo = {
|
||||
Gl2cCounterBlockNumCounters,
|
||||
Gl2cCounterRegAddr,
|
||||
gfx10_cntx_prim::select_value_TCP_PERFCOUNTER0_SELECT,
|
||||
CounterBlockTcAttr};
|
||||
CounterBlockTcAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block GCR
|
||||
static const GpuBlockInfo GcrCounterBlockInfo = {
|
||||
"GCR",
|
||||
@@ -395,7 +412,8 @@ static const GpuBlockInfo GcrCounterBlockInfo = {
|
||||
GcrCounterBlockNumCounters,
|
||||
GcrCounterRegAddr,
|
||||
gfx10_cntx_prim::select_value_TCP_PERFCOUNTER0_SELECT,
|
||||
CounterBlockTcAttr};
|
||||
CounterBlockTcAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block GUS
|
||||
static const GpuBlockInfo GusCounterBlockInfo = {
|
||||
"GUS",
|
||||
@@ -405,7 +423,8 @@ static const GpuBlockInfo GusCounterBlockInfo = {
|
||||
GusCounterBlockNumCounters,
|
||||
GusCounterRegAddr,
|
||||
gfx10_cntx_prim::mc_select_value_RPB_PERFCOUNTER0_CFG,
|
||||
CounterBlockGusAttr};
|
||||
CounterBlockGusAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block TA
|
||||
static const GpuBlockInfo TaCounterBlockInfo = {
|
||||
"TA",
|
||||
@@ -416,8 +435,7 @@ static const GpuBlockInfo TaCounterBlockInfo = {
|
||||
TaCounterRegAddr,
|
||||
gfx10_cntx_prim::select_value_TA_PERFCOUNTER0_SELECT,
|
||||
CounterBlockSeAttr | CounterBlockTcAttr,
|
||||
NULL /*TaBlockDelayInfo*/,
|
||||
SPM_SE_BLOCK_NAME_TA};
|
||||
BLOCK_DELAY_NONE};
|
||||
|
||||
} // namespace gfx10
|
||||
} // namespace gfxip
|
||||
|
||||
@@ -128,6 +128,7 @@ class gfx10_cntx_prim {
|
||||
REG_32B_ADDR(GC, 0, mmRLC_SPM_SE_MUXSEL_ADDR);
|
||||
static constexpr Register RLC_SPM_SE_MUXSEL_DATA__ADDR =
|
||||
REG_32B_ADDR(GC, 0, mmRLC_SPM_SE_MUXSEL_DATA);
|
||||
static constexpr Register RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__ADDR = REG_32B_NULL;
|
||||
static const uint32_t RLC_SPM_COUNTERS_PER_LINE = 16;
|
||||
static const uint32_t RLC_SPM_TIMESTAMP_SIZE16 = 4;
|
||||
|
||||
@@ -165,7 +166,7 @@ class gfx10_cntx_prim {
|
||||
static uint32_t get_spm_global_delay(const counter_des_t& counter_des,
|
||||
const uint32_t& instance_index) {
|
||||
const auto* block_info = counter_des.block_info;
|
||||
return block_info->delay_info[instance_index].val - 1;
|
||||
return block_info->delay_info.val[instance_index];
|
||||
}
|
||||
|
||||
// SPM delay functions for se instance
|
||||
@@ -173,7 +174,7 @@ class gfx10_cntx_prim {
|
||||
const uint32_t& instance_index) {
|
||||
const auto* block_info = counter_des.block_info;
|
||||
int delay_index = se_index * block_info->instance_count + instance_index;
|
||||
return block_info->delay_info[delay_index].val - 1;
|
||||
return block_info->delay_info.val[delay_index];
|
||||
}
|
||||
|
||||
// GRBM broadcasting mode
|
||||
|
||||
@@ -31,39 +31,39 @@ namespace gfx11 {
|
||||
*/
|
||||
static const CounterRegInfo CpcCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER0_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER1_HI)}};
|
||||
REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regCPC_PERFCOUNTER1_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* CPF CORRECT
|
||||
*/
|
||||
static const CounterRegInfo CpfCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER0_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER1_HI)}};
|
||||
REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regCPF_PERFCOUNTER1_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* GDS CORRECT
|
||||
*/
|
||||
static const CounterRegInfo GdsCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER0_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER1_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER3_HI)}};
|
||||
REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regGDS_PERFCOUNTER3_HI), REG_32B_NULL}};
|
||||
/*
|
||||
* GRBM CORRECT
|
||||
*/
|
||||
static const CounterRegInfo GrbmCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER0_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER1_HI)}};
|
||||
REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGRBM_PERFCOUNTER1_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* GRBM_SE CORRECT
|
||||
@@ -71,74 +71,74 @@ static const CounterRegInfo GrbmCounterRegAddr[] = {
|
||||
static const CounterRegInfo GrbmSeCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, regGRBM_SE0_PERFCOUNTER_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGRBM_SE0_PERFCOUNTER_LO),
|
||||
REG_32B_ADDR(GC, 0, regGRBM_SE0_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGRBM_SE0_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGRBM_SE1_PERFCOUNTER_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGRBM_SE1_PERFCOUNTER_LO),
|
||||
REG_32B_ADDR(GC, 0, regGRBM_SE1_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGRBM_SE1_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGRBM_SE2_PERFCOUNTER_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGRBM_SE2_PERFCOUNTER_LO),
|
||||
REG_32B_ADDR(GC, 0, regGRBM_SE2_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGRBM_SE2_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGRBM_SE3_PERFCOUNTER_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGRBM_SE3_PERFCOUNTER_LO),
|
||||
REG_32B_ADDR(GC, 0, regGRBM_SE3_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGRBM_SE3_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGRBM_SE4_PERFCOUNTER_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGRBM_SE4_PERFCOUNTER_LO),
|
||||
REG_32B_ADDR(GC, 0, regGRBM_SE4_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGRBM_SE4_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGRBM_SE5_PERFCOUNTER_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGRBM_SE5_PERFCOUNTER_LO),
|
||||
REG_32B_ADDR(GC, 0, regGRBM_SE5_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGRBM_SE5_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGRBM_SE6_PERFCOUNTER_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGRBM_SE6_PERFCOUNTER_LO),
|
||||
REG_32B_ADDR(GC, 0, regGRBM_SE6_PERFCOUNTER_HI)}};
|
||||
REG_32B_ADDR(GC, 0, regGRBM_SE6_PERFCOUNTER_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* SPI CORRECT
|
||||
*/
|
||||
static const CounterRegInfo SpiCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER0_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER1_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER3_HI)},
|
||||
REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER3_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER4_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER4_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER4_HI)},
|
||||
REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER4_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER4_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER5_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER5_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER5_HI)}};
|
||||
REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER5_LO), REG_32B_ADDR(GC, 0, regSPI_PERFCOUNTER5_HI), REG_32B_NULL}};
|
||||
/*
|
||||
* SQ CORRECT
|
||||
*/
|
||||
static const CounterRegInfo SqCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER0_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER0_LO), REG_32B_NULL},
|
||||
REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER0_LO), REG_32B_NULL, REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER2_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER1_LO), REG_32B_NULL},
|
||||
REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER1_LO), REG_32B_NULL, REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER4_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER2_LO), REG_32B_NULL},
|
||||
REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER2_LO), REG_32B_NULL, REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER6_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER3_LO), REG_32B_NULL},
|
||||
REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER3_LO), REG_32B_NULL, REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER8_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER4_LO), REG_32B_NULL},
|
||||
REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER4_LO), REG_32B_NULL, REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER10_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER5_LO), REG_32B_NULL},
|
||||
REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER5_LO), REG_32B_NULL, REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER12_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER6_LO), REG_32B_NULL},
|
||||
REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER6_LO), REG_32B_NULL, REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER14_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER7_LO), REG_32B_NULL}};
|
||||
REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER7_LO), REG_32B_NULL, REG_32B_NULL}};
|
||||
/*
|
||||
* SX CORRECT
|
||||
*/
|
||||
static const CounterRegInfo SxCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER0_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER1_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER3_HI)}};
|
||||
REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regSX_PERFCOUNTER3_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* GCEA
|
||||
@@ -146,10 +146,10 @@ static const CounterRegInfo SxCounterRegAddr[] = {
|
||||
static const CounterRegInfo GceaCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER0_CFG),
|
||||
REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_RSLT_CNTL),
|
||||
REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_LO), REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_LO), REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER1_CFG),
|
||||
REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_RSLT_CNTL),
|
||||
REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_LO), REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_HI)}};
|
||||
REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_LO), REG_32B_ADDR(GC, 0, regGCEA_PERFCOUNTER_HI), REG_32B_NULL}};
|
||||
|
||||
// Define GFX10 specific blocks table entries like GC caches blocks
|
||||
/*
|
||||
@@ -157,34 +157,34 @@ static const CounterRegInfo GceaCounterRegAddr[] = {
|
||||
*/
|
||||
static const CounterRegInfo GcrCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, regGCR_PERFCOUNTER0_SELECT), REG_32B_ADDR(GC, 0, regGCR_GENERAL_CNTL),
|
||||
REG_32B_ADDR(GC, 0, regGCR_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGCR_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGCR_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGCR_PERFCOUNTER0_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGCR_PERFCOUNTER1_SELECT), REG_32B_ADDR(GC, 0, regGCR_GENERAL_CNTL),
|
||||
REG_32B_ADDR(GC, 0, regGCR_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGCR_PERFCOUNTER1_HI)}};
|
||||
REG_32B_ADDR(GC, 0, regGCR_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGCR_PERFCOUNTER1_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* TCP
|
||||
*/
|
||||
static const CounterRegInfo TcpCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER0_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER1_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER3_HI)}};
|
||||
REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regTCP_PERFCOUNTER3_HI), REG_32B_NULL}};
|
||||
/*
|
||||
* GL1A CORRECT
|
||||
*/
|
||||
static const CounterRegInfo Gl1aCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER0_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER1_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER3_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regGL1A_PERFCOUNTER3_HI), REG_32B_NULL},
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -192,13 +192,13 @@ static const CounterRegInfo Gl1aCounterRegAddr[] = {
|
||||
*/
|
||||
static const CounterRegInfo Gl1cCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER0_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER1_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER3_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regGL1C_PERFCOUNTER3_HI), REG_32B_NULL},
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -206,13 +206,13 @@ static const CounterRegInfo Gl1cCounterRegAddr[] = {
|
||||
*/
|
||||
static const CounterRegInfo Gl2aCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER0_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER1_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER3_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regGL2A_PERFCOUNTER3_HI), REG_32B_NULL},
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -220,13 +220,13 @@ static const CounterRegInfo Gl2aCounterRegAddr[] = {
|
||||
*/
|
||||
static const CounterRegInfo Gl2cCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER0_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER1_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER3_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, regGL2C_PERFCOUNTER3_HI), REG_32B_NULL},
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -235,10 +235,10 @@ static const CounterRegInfo Gl2cCounterRegAddr[] = {
|
||||
static const CounterRegInfo GusCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, regGUS_PERFCOUNTER0_CFG),
|
||||
REG_32B_ADDR(GC, 0, regGUS_PERFCOUNTER_RSLT_CNTL), REG_32B_ADDR(GC, 0, regGUS_PERFCOUNTER_LO),
|
||||
REG_32B_ADDR(GC, 0, regGUS_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGUS_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGUS_PERFCOUNTER1_CFG),
|
||||
REG_32B_ADDR(GC, 0, regGUS_PERFCOUNTER_RSLT_CNTL), REG_32B_ADDR(GC, 0, regGUS_PERFCOUNTER2_LO),
|
||||
REG_32B_ADDR(GC, 0, regGUS_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, regGUS_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -246,9 +246,9 @@ static const CounterRegInfo GusCounterRegAddr[] = {
|
||||
*/
|
||||
static const CounterRegInfo TaCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER0_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER1_HI)}};
|
||||
REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, regTA_PERFCOUNTER1_HI), REG_32B_NULL}};
|
||||
|
||||
// Counter block CPC
|
||||
static const GpuBlockInfo CpcCounterBlockInfo = {
|
||||
@@ -260,8 +260,7 @@ static const GpuBlockInfo CpcCounterBlockInfo = {
|
||||
CpcCounterRegAddr,
|
||||
gfx11_cntx_prim::select_value_CPC_PERFCOUNTER0_SELECT,
|
||||
CounterBlockDfltAttr | CounterBlockSpmGlobalAttr,
|
||||
NULL /*CpcBlockDelayInfo*/,
|
||||
SPM_GLOBAL_BLOCK_NAME_CPC};
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block CPF
|
||||
static const GpuBlockInfo CpfCounterBlockInfo = {
|
||||
"CPF",
|
||||
@@ -272,8 +271,7 @@ static const GpuBlockInfo CpfCounterBlockInfo = {
|
||||
CpfCounterRegAddr,
|
||||
gfx11_cntx_prim::select_value_CPF_PERFCOUNTER0_SELECT,
|
||||
CounterBlockDfltAttr | CounterBlockSpmGlobalAttr,
|
||||
NULL /*CpfBlockDelayInfo*/,
|
||||
SPM_GLOBAL_BLOCK_NAME_CPF};
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block GDS
|
||||
static const GpuBlockInfo GdsCounterBlockInfo = {
|
||||
"GDS",
|
||||
@@ -284,8 +282,7 @@ static const GpuBlockInfo GdsCounterBlockInfo = {
|
||||
GdsCounterRegAddr,
|
||||
gfx11_cntx_prim::select_value_GDS_PERFCOUNTER0_SELECT,
|
||||
CounterBlockDfltAttr | CounterBlockSpmGlobalAttr,
|
||||
NULL /*GdsBlockDelayInfo*/,
|
||||
SPM_GLOBAL_BLOCK_NAME_GDS};
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block GRBM
|
||||
static const GpuBlockInfo GrbmCounterBlockInfo = {
|
||||
"GRBM",
|
||||
@@ -295,7 +292,8 @@ static const GpuBlockInfo GrbmCounterBlockInfo = {
|
||||
GrbmCounterBlockNumCounters,
|
||||
GrbmCounterRegAddr,
|
||||
gfx11_cntx_prim::select_value_GRBM_PERFCOUNTER0_SELECT,
|
||||
CounterBlockDfltAttr | CounterBlockGRBMAttr};
|
||||
CounterBlockDfltAttr | CounterBlockGRBMAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block GRBMSE
|
||||
static const GpuBlockInfo GrbmSeCounterBlockInfo = {
|
||||
"GRBM_SE",
|
||||
@@ -305,7 +303,8 @@ static const GpuBlockInfo GrbmSeCounterBlockInfo = {
|
||||
GrbmSeCounterBlockNumCounters,
|
||||
GrbmSeCounterRegAddr,
|
||||
gfx11_cntx_prim::select_value_GRBM_SE0_PERFCOUNTER_SELECT,
|
||||
CounterBlockDfltAttr};
|
||||
CounterBlockDfltAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block SPI
|
||||
static const GpuBlockInfo SpiCounterBlockInfo = {
|
||||
"SPI",
|
||||
@@ -316,8 +315,7 @@ static const GpuBlockInfo SpiCounterBlockInfo = {
|
||||
SpiCounterRegAddr,
|
||||
gfx11_cntx_prim::select_value_SPI_PERFCOUNTER0_SELECT,
|
||||
CounterBlockSeAttr | CounterBlockSPIAttr,
|
||||
NULL /*SpiBlockDelayInfo*/,
|
||||
SPM_SE_BLOCK_NAME_SPI};
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block SQ
|
||||
static const GpuBlockInfo SqCounterBlockInfo = {
|
||||
"SQ",
|
||||
@@ -328,8 +326,7 @@ static const GpuBlockInfo SqCounterBlockInfo = {
|
||||
SqCounterRegAddr,
|
||||
gfx11_cntx_prim::sq_select_value,
|
||||
CounterBlockSeAttr | CounterBlockSqAttr | CounterBlockSaAttr,
|
||||
NULL,
|
||||
SPM_SE_BLOCK_NAME_SQG};
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block SX
|
||||
static const GpuBlockInfo SxCounterBlockInfo = {
|
||||
"SX",
|
||||
@@ -340,8 +337,7 @@ static const GpuBlockInfo SxCounterBlockInfo = {
|
||||
SxCounterRegAddr,
|
||||
gfx11_cntx_prim::select_value_SX_PERFCOUNTER0_SELECT,
|
||||
CounterBlockSeAttr | CounterBlockCleanAttr,
|
||||
NULL /*SxBlockDelayInfo*/,
|
||||
SPM_SE_BLOCK_NAME_SX};
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block GCEA
|
||||
static const GpuBlockInfo GceaCounterBlockInfo = {
|
||||
"GCEA",
|
||||
@@ -351,7 +347,8 @@ static const GpuBlockInfo GceaCounterBlockInfo = {
|
||||
GceaCounterBlockNumCounters,
|
||||
GceaCounterRegAddr,
|
||||
gfx11_cntx_prim::mc_select_value_GCEA_PERFCOUNTER0_CFG,
|
||||
CounterBlockMcAttr};
|
||||
CounterBlockMcAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block TCP
|
||||
static const GpuBlockInfo TcpCounterBlockInfo = {
|
||||
"TCP",
|
||||
@@ -361,7 +358,8 @@ static const GpuBlockInfo TcpCounterBlockInfo = {
|
||||
TcpCounterBlockNumCounters,
|
||||
TcpCounterRegAddr,
|
||||
gfx11_cntx_prim::select_value_TCP_PERFCOUNTER0_SELECT,
|
||||
CounterBlockDfltAttr | CounterBlockSeAttr | CounterBlockSaAttr};
|
||||
CounterBlockDfltAttr | CounterBlockSeAttr | CounterBlockSaAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block GL1A
|
||||
static const GpuBlockInfo Gl1aCounterBlockInfo = {
|
||||
"GL1A",
|
||||
@@ -371,7 +369,8 @@ static const GpuBlockInfo Gl1aCounterBlockInfo = {
|
||||
Gl1aCounterBlockNumCounters,
|
||||
Gl1aCounterRegAddr,
|
||||
gfx11_cntx_prim::select_value_TCP_PERFCOUNTER0_SELECT,
|
||||
CounterBlockDfltAttr | CounterBlockSeAttr | CounterBlockSaAttr | CounterBlockTcAttr};
|
||||
CounterBlockDfltAttr | CounterBlockSeAttr | CounterBlockSaAttr | CounterBlockTcAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block GL1C
|
||||
static const GpuBlockInfo Gl1cCounterBlockInfo = {
|
||||
"GL1C",
|
||||
@@ -381,7 +380,8 @@ static const GpuBlockInfo Gl1cCounterBlockInfo = {
|
||||
Gl1cCounterBlockNumCounters,
|
||||
Gl1cCounterRegAddr,
|
||||
gfx11_cntx_prim::select_value_TCP_PERFCOUNTER0_SELECT,
|
||||
CounterBlockDfltAttr | CounterBlockSeAttr | CounterBlockSaAttr | CounterBlockTcAttr};
|
||||
CounterBlockDfltAttr | CounterBlockSeAttr | CounterBlockSaAttr | CounterBlockTcAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block GL2A
|
||||
static const GpuBlockInfo Gl2aCounterBlockInfo = {
|
||||
"GL2A",
|
||||
@@ -391,7 +391,8 @@ static const GpuBlockInfo Gl2aCounterBlockInfo = {
|
||||
Gl2aCounterBlockNumCounters,
|
||||
Gl2aCounterRegAddr,
|
||||
gfx11_cntx_prim::select_value_TCP_PERFCOUNTER0_SELECT,
|
||||
CounterBlockDfltAttr | CounterBlockTcAttr};
|
||||
CounterBlockDfltAttr | CounterBlockTcAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block GL2C
|
||||
static const GpuBlockInfo Gl2cCounterBlockInfo = {
|
||||
"GL2C",
|
||||
@@ -401,7 +402,8 @@ static const GpuBlockInfo Gl2cCounterBlockInfo = {
|
||||
Gl2cCounterBlockNumCounters,
|
||||
Gl2cCounterRegAddr,
|
||||
gfx11_cntx_prim::select_value_TCP_PERFCOUNTER0_SELECT,
|
||||
CounterBlockDfltAttr | CounterBlockTcAttr};
|
||||
CounterBlockDfltAttr | CounterBlockTcAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block GCR
|
||||
static const GpuBlockInfo GcrCounterBlockInfo = {
|
||||
"GCR",
|
||||
@@ -411,7 +413,8 @@ static const GpuBlockInfo GcrCounterBlockInfo = {
|
||||
GcrCounterBlockNumCounters,
|
||||
GcrCounterRegAddr,
|
||||
gfx11_cntx_prim::select_value_TCP_PERFCOUNTER0_SELECT,
|
||||
CounterBlockTcAttr};
|
||||
CounterBlockTcAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block GUS
|
||||
static const GpuBlockInfo GusCounterBlockInfo = {
|
||||
"GUS",
|
||||
@@ -421,7 +424,8 @@ static const GpuBlockInfo GusCounterBlockInfo = {
|
||||
GusCounterBlockNumCounters,
|
||||
GusCounterRegAddr,
|
||||
gfx11_cntx_prim::mc_select_value_RPB_PERFCOUNTER0_CFG,
|
||||
CounterBlockGusAttr};
|
||||
CounterBlockGusAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block TA
|
||||
static const GpuBlockInfo TaCounterBlockInfo = {
|
||||
"TA",
|
||||
@@ -432,8 +436,7 @@ static const GpuBlockInfo TaCounterBlockInfo = {
|
||||
TaCounterRegAddr,
|
||||
gfx11_cntx_prim::select_value_TA_PERFCOUNTER0_SELECT,
|
||||
CounterBlockSeAttr | CounterBlockTcAttr,
|
||||
NULL /*TaBlockDelayInfo*/,
|
||||
SPM_SE_BLOCK_NAME_TA};
|
||||
BLOCK_DELAY_NONE};
|
||||
|
||||
} // namespace gfx11
|
||||
} // namespace gfxip
|
||||
|
||||
@@ -135,6 +135,7 @@ class gfx11_cntx_prim {
|
||||
REG_32B_ADDR(GC, 0, regRLC_SPM_SE_MUXSEL_ADDR);
|
||||
static constexpr Register RLC_SPM_SE_MUXSEL_DATA__ADDR =
|
||||
REG_32B_ADDR(GC, 0, regRLC_SPM_SE_MUXSEL_DATA);
|
||||
static constexpr Register RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__ADDR = REG_32B_NULL;
|
||||
static const uint32_t RLC_SPM_COUNTERS_PER_LINE = 16;
|
||||
static const uint32_t RLC_SPM_TIMESTAMP_SIZE16 = 4;
|
||||
|
||||
@@ -172,7 +173,7 @@ class gfx11_cntx_prim {
|
||||
static uint32_t get_spm_global_delay(const counter_des_t& counter_des,
|
||||
const uint32_t& instance_index) {
|
||||
const auto* block_info = counter_des.block_info;
|
||||
return block_info->delay_info[instance_index].val - 1;
|
||||
return block_info->delay_info.val[instance_index];
|
||||
}
|
||||
|
||||
// SPM delay functions for se instance
|
||||
@@ -180,7 +181,7 @@ class gfx11_cntx_prim {
|
||||
const uint32_t& instance_index) {
|
||||
const auto* block_info = counter_des.block_info;
|
||||
int delay_index = se_index * block_info->instance_count + instance_index;
|
||||
return block_info->delay_info[delay_index].val - 1;
|
||||
return block_info->delay_info.val[delay_index];
|
||||
}
|
||||
|
||||
// GRBM broadcasting mode
|
||||
|
||||
@@ -26,7 +26,7 @@
|
||||
#define _GFX12_BLOCKTABLE_H_
|
||||
|
||||
#define REG_INFO_WITH_CTRL(BLOCK, CTRL, INDEX) \
|
||||
{REG_32B_ADDR(GC, 0, reg##BLOCK##_PERFCOUNTER##INDEX##_SELECT), CTRL, REG_32B_ADDR(GC, 0, reg##BLOCK##_PERFCOUNTER##INDEX##_LO), REG_32B_ADDR(GC, 0, reg##BLOCK##_PERFCOUNTER##INDEX##_HI)}
|
||||
{REG_32B_ADDR(GC, 0, reg##BLOCK##_PERFCOUNTER##INDEX##_SELECT), CTRL, REG_32B_ADDR(GC, 0, reg##BLOCK##_PERFCOUNTER##INDEX##_LO), REG_32B_ADDR(GC, 0, reg##BLOCK##_PERFCOUNTER##INDEX##_HI), REG_32B_NULL}
|
||||
#define REG_INFO_WITH_CTRL_1(BLOCK, CTRL) REG_INFO_WITH_CTRL(BLOCK, CTRL, 0)
|
||||
#define REG_INFO_WITH_CTRL_2(BLOCK, CTRL) REG_INFO_WITH_CTRL_1(BLOCK, CTRL), REG_INFO_WITH_CTRL(BLOCK, CTRL, 1)
|
||||
#define REG_INFO_WITH_CTRL_3(BLOCK, CTRL) REG_INFO_WITH_CTRL_2(BLOCK, CTRL), REG_INFO_WITH_CTRL(BLOCK, CTRL, 2)
|
||||
@@ -45,7 +45,7 @@
|
||||
#define REG_INFO_8(BLOCK) REG_INFO_WITH_CTRL_8(BLOCK, REG_32B_NULL)
|
||||
|
||||
#define REG_INFO_WITH_CFG(IP, BLOCK, INDEX) \
|
||||
{REG_32B_ADDR(IP, 0, reg##BLOCK##_PERFCOUNTER##INDEX##_CFG), REG_32B_ADDR(IP, 0, reg##BLOCK##_PERFCOUNTER_RSLT_CNTL), REG_32B_ADDR(IP, 0, reg##BLOCK##_PERFCOUNTER_LO), REG_32B_ADDR(IP, 0, reg##BLOCK##_PERFCOUNTER_HI)}
|
||||
{REG_32B_ADDR(IP, 0, reg##BLOCK##_PERFCOUNTER##INDEX##_CFG), REG_32B_ADDR(IP, 0, reg##BLOCK##_PERFCOUNTER_RSLT_CNTL), REG_32B_ADDR(IP, 0, reg##BLOCK##_PERFCOUNTER_LO), REG_32B_ADDR(IP, 0, reg##BLOCK##_PERFCOUNTER_HI), REG_32B_NULL}
|
||||
#define REG_INFO_WITH_CFG_1(IP, BLOCK) REG_INFO_WITH_CFG(IP, BLOCK, 0)
|
||||
#define REG_INFO_WITH_CFG_2(IP, BLOCK) REG_INFO_WITH_CFG_1(IP, BLOCK), REG_INFO_WITH_CFG(IP, BLOCK, 1)
|
||||
#define REG_INFO_WITH_CFG_3(IP, BLOCK) REG_INFO_WITH_CFG_2(IP, BLOCK), REG_INFO_WITH_CFG(IP, BLOCK, 2)
|
||||
@@ -92,66 +92,64 @@ static const CounterRegInfo Utcl1CounterRegAddr[] = {REG_INFO_4(UTCL1)};
|
||||
// regSQ_PERFCOUNTER#even_number#_SELECT is used by PMC and SPM
|
||||
// regSQ_PERFCOUNTER#odd_number#_SELECT is used by SPM only
|
||||
static const CounterRegInfo SqcCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER0_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER0_LO), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER2_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER1_LO), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER4_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER2_LO), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER6_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER3_LO), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER8_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER4_LO), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER10_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER5_LO), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER12_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER6_LO), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER14_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER7_LO), REG_32B_NULL}};
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER0_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER0_LO), REG_32B_NULL, REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER2_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER1_LO), REG_32B_NULL, REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER4_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER2_LO), REG_32B_NULL, REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER6_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER3_LO), REG_32B_NULL, REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER8_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER4_LO), REG_32B_NULL, REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER10_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER5_LO), REG_32B_NULL, REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER12_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER6_LO), REG_32B_NULL, REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER14_SELECT), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER_CTRL), REG_32B_ADDR(GC, 0, regSQ_PERFCOUNTER7_LO), REG_32B_NULL, REG_32B_NULL}};
|
||||
|
||||
// Special handling of GCVML2 (SPM only):
|
||||
static const CounterRegInfo Gcvml2CounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, regGCVML2_PERFCOUNTER2_0_SELECT), REG_32B_NULL, REG_32B_ADDR(GC, 0, regGCVML2_PERFCOUNTER2_0_LO), REG_32B_ADDR(GC, 0, regGCVML2_PERFCOUNTER2_0_HI)},
|
||||
{REG_32B_ADDR(GC, 0, regGCVML2_PERFCOUNTER2_1_SELECT), REG_32B_NULL, REG_32B_ADDR(GC, 0, regGCVML2_PERFCOUNTER2_1_LO), REG_32B_ADDR(GC, 0, regGCVML2_PERFCOUNTER2_1_HI)}};
|
||||
{REG_32B_ADDR(GC, 0, regGCVML2_PERFCOUNTER2_0_SELECT), REG_32B_NULL, REG_32B_ADDR(GC, 0, regGCVML2_PERFCOUNTER2_0_LO), REG_32B_ADDR(GC, 0, regGCVML2_PERFCOUNTER2_0_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, regGCVML2_PERFCOUNTER2_1_SELECT), REG_32B_NULL, REG_32B_ADDR(GC, 0, regGCVML2_PERFCOUNTER2_1_LO), REG_32B_ADDR(GC, 0, regGCVML2_PERFCOUNTER2_1_HI), REG_32B_NULL}};
|
||||
|
||||
// Global blocks: ATCL2 CHA CHC CPC CPF CPG EA FFBM GCR GL2A GL2C GRBM RLC SDMA VML2 UTCL2
|
||||
// (Grphics only - not supported in ROCm): GE1 GE2_DIST PH
|
||||
// (Grphics only): CPG is for graphics, but it is not physically removed for compute products
|
||||
// (Not enabled for gfx12): CHCG GDS GUS
|
||||
static const GpuBlockInfo Gl2aCounterBlockInfo = {"GL2A", __BLOCK_ID_HSA(GL2A), Gl2aCounterBlockNumInstances, Gl2aCounterBlockMaxEvent, Gl2aCounterBlockNumCounters, Gl2aCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockTcAttr};
|
||||
static const GpuBlockInfo Gl2cCounterBlockInfo = {"GL2C", __BLOCK_ID_HSA(GL2C), Gl2cCounterBlockNumInstances, Gl2cCounterBlockMaxEvent, Gl2cCounterBlockNumCounters, Gl2cCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockTcAttr};
|
||||
static const GpuBlockInfo Atcl2CounterBlockInfo = {"ATCL2", __BLOCK_ID_HSA(ATCL2)}; // Placeholder now
|
||||
static const GpuBlockInfo GcFfbmCounterBlockInfo = {"GC_FFBM", __BLOCK_ID(GC_FFBM)}; // Placeholder now
|
||||
static const GpuBlockInfo RpbCounterBlockInfo = {"RPB", __BLOCK_ID_HSA(RPB), 1, RpbCounterBlockMaxEvent, RpbCounterBlockNumCounters, RpbCounterRegAddr, gfx12_cntx_prim::mc_select_value, CounterBlockRpbAttr|CounterBlockAidAttr};
|
||||
static const GpuBlockInfo GcUtcl2CounterBlockInfo = {"GC_UTCL2", __BLOCK_ID(GC_UTCL2), 1, Gcutcl2CounterBlockMaxEvent, Gcutcl2CounterBlockNumCounters, Gcutcl2CounterRegAddr, gfx12_cntx_prim::mc_select_value, CounterBlockRpbAttr|CounterBlockAidAttr};
|
||||
static const GpuBlockInfo GcVml2CounterBlockInfo = {"GC_VML2", __BLOCK_ID(GC_VML2), 1, GcmcVmL2CounterBlockMaxEvent, GcmcVmL2CounterBlockNumCounters, GcmcVmL2CounterRegAddr, gfx12_cntx_prim::mc_select_value, CounterBlockRpbAttr|CounterBlockAidAttr};
|
||||
static const GpuBlockInfo GcVml2SpmCounterBlockInfo = {"GC_VML2_SPM", __BLOCK_ID(GC_VML2_SPM), 1, Gcvml2CounterBlockMaxEvent, Gcvml2CounterBlockNumCounters, Gcvml2CounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr};
|
||||
static const GpuBlockInfo ChaCounterBlockInfo = {"CHA", __BLOCK_ID(CHA), ChaCounterBlockNumInstances, ChaCounterBlockMaxEvent, ChaCounterBlockNumCounters, ChaCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockTcAttr};
|
||||
static const GpuBlockInfo ChcCounterBlockInfo = {"CHC", __BLOCK_ID(CHC), ChcCounterBlockNumInstances, ChcCounterBlockMaxEvent, ChcCounterBlockNumCounters, ChcCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockTcAttr};
|
||||
static const GpuBlockInfo CpcCounterBlockInfo = {"CPC", __BLOCK_ID_HSA(CPC), CpcCounterBlockNumInstances, CpcCounterBlockMaxEvent, CpcCounterBlockNumCounters, CpcCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockSpmGlobalAttr, NULL, SPM_GLOBAL_BLOCK_NAME_CPC};
|
||||
static const GpuBlockInfo CpfCounterBlockInfo = {"CPF", __BLOCK_ID_HSA(CPF), CpfCounterBlockNumInstances, CpfCounterBlockMaxEvent, CpfCounterBlockNumCounters, CpfCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockSpmGlobalAttr, NULL, SPM_GLOBAL_BLOCK_NAME_CPF};
|
||||
static const GpuBlockInfo CpgCounterBlockInfo = {"CPG", __BLOCK_ID(CPG), CpgCounterBlockNumInstances, CpgCounterBlockMaxEvent, CpgCounterBlockNumCounters, CpgCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockSpmGlobalAttr, NULL, SPM_GLOBAL_BLOCK_NAME_CPG};
|
||||
static const GpuBlockInfo GcrCounterBlockInfo = {"GCR", __BLOCK_ID_HSA(GCR), GcrCounterBlockNumInstances, GcrCounterBlockMaxEvent, GcrCounterBlockNumCounters, GcrCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockTcAttr};
|
||||
static const GpuBlockInfo GceaCounterBlockInfo = {"GCEA", __BLOCK_ID_HSA(GCEA), GcEaCpwdCounterBlockNumInstances, GcEaCpwdCounterBlockMaxEvent, GcEaCpwdCounterBlockNumCounters, GcEaCpwdCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr};
|
||||
static const GpuBlockInfo GrbmCounterBlockInfo = {"GRBM", __BLOCK_ID_HSA(GRBM), GrbmCounterBlockNumInstances, GrbmCounterBlockMaxEvent, GrbmCounterBlockNumCounters, GrbmCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockGRBMAttr};
|
||||
static const GpuBlockInfo RlcCounterBlockInfo = {"RLC", __BLOCK_ID(RLC), RlcCounterBlockNumInstances, RlcCounterBlockMaxEvent, RlcCounterBlockNumCounters, RlcCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr};
|
||||
static const GpuBlockInfo SdmaCounterBlockInfo = {"SDMA", __BLOCK_ID_HSA(SDMA), SdmaCounterBlockNumInstances, SdmaCounterBlockMaxEvent, SdmaCounterBlockNumCounters, SdmaCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockExplInstAttr|CounterBlockSpmGlobalAttr, NULL, SPM_GLOBAL_BLOCK_NAME_SDMA};
|
||||
static const GpuBlockInfo Gl2aCounterBlockInfo = {"GL2A", __BLOCK_ID_HSA(GL2A), Gl2aCounterBlockNumInstances, Gl2aCounterBlockMaxEvent, Gl2aCounterBlockNumCounters, Gl2aCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockTcAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo Gl2cCounterBlockInfo = {"GL2C", __BLOCK_ID_HSA(GL2C), Gl2cCounterBlockNumInstances, Gl2cCounterBlockMaxEvent, Gl2cCounterBlockNumCounters, Gl2cCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockTcAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo RpbCounterBlockInfo = {"RPB", __BLOCK_ID_HSA(RPB), 1, RpbCounterBlockMaxEvent, RpbCounterBlockNumCounters, RpbCounterRegAddr, gfx12_cntx_prim::mc_select_value, CounterBlockRpbAttr|CounterBlockAidAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo GcUtcl2CounterBlockInfo = {"GC_UTCL2", __BLOCK_ID(GC_UTCL2), 1, Gcutcl2CounterBlockMaxEvent, Gcutcl2CounterBlockNumCounters, Gcutcl2CounterRegAddr, gfx12_cntx_prim::mc_select_value, CounterBlockRpbAttr|CounterBlockAidAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo GcVml2CounterBlockInfo = {"GC_VML2", __BLOCK_ID(GC_VML2), 1, GcmcVmL2CounterBlockMaxEvent, GcmcVmL2CounterBlockNumCounters, GcmcVmL2CounterRegAddr, gfx12_cntx_prim::mc_select_value, CounterBlockRpbAttr|CounterBlockAidAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo GcVml2SpmCounterBlockInfo = {"GC_VML2_SPM", __BLOCK_ID(GC_VML2_SPM), 1, Gcvml2CounterBlockMaxEvent, Gcvml2CounterBlockNumCounters, Gcvml2CounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo ChaCounterBlockInfo = {"CHA", __BLOCK_ID(CHA), ChaCounterBlockNumInstances, ChaCounterBlockMaxEvent, ChaCounterBlockNumCounters, ChaCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockTcAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo ChcCounterBlockInfo = {"CHC", __BLOCK_ID(CHC), ChcCounterBlockNumInstances, ChcCounterBlockMaxEvent, ChcCounterBlockNumCounters, ChcCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockTcAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo CpcCounterBlockInfo = {"CPC", __BLOCK_ID_HSA(CPC), CpcCounterBlockNumInstances, CpcCounterBlockMaxEvent, CpcCounterBlockNumCounters, CpcCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockSpmGlobalAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo CpfCounterBlockInfo = {"CPF", __BLOCK_ID_HSA(CPF), CpfCounterBlockNumInstances, CpfCounterBlockMaxEvent, CpfCounterBlockNumCounters, CpfCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockSpmGlobalAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo CpgCounterBlockInfo = {"CPG", __BLOCK_ID(CPG), CpgCounterBlockNumInstances, CpgCounterBlockMaxEvent, CpgCounterBlockNumCounters, CpgCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockSpmGlobalAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo GcrCounterBlockInfo = {"GCR", __BLOCK_ID_HSA(GCR), GcrCounterBlockNumInstances, GcrCounterBlockMaxEvent, GcrCounterBlockNumCounters, GcrCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockTcAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo GceaCounterBlockInfo = {"GCEA", __BLOCK_ID_HSA(GCEA), GcEaCpwdCounterBlockNumInstances, GcEaCpwdCounterBlockMaxEvent, GcEaCpwdCounterBlockNumCounters, GcEaCpwdCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo GrbmCounterBlockInfo = {"GRBM", __BLOCK_ID_HSA(GRBM), GrbmCounterBlockNumInstances, GrbmCounterBlockMaxEvent, GrbmCounterBlockNumCounters, GrbmCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockGRBMAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo RlcCounterBlockInfo = {"RLC", __BLOCK_ID(RLC), RlcCounterBlockNumInstances, RlcCounterBlockMaxEvent, RlcCounterBlockNumCounters, RlcCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo SdmaCounterBlockInfo = {"SDMA", __BLOCK_ID_HSA(SDMA), SdmaCounterBlockNumInstances, SdmaCounterBlockMaxEvent, SdmaCounterBlockNumCounters, SdmaCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockExplInstAttr|CounterBlockSpmGlobalAttr, BLOCK_DELAY_NONE};
|
||||
// SE blocks: EA_SE GL2A GL2C GRBMH SPI SQG UTCL1
|
||||
// (Grphics only - not supported in ROCm): GE GL1XA GL1XC PA PC WGS
|
||||
static const GpuBlockInfo GceaSeCounterBlockInfo = {"GCEA_SE", __BLOCK_ID(GCEA_SE), GcEaSeCounterBlockNumInstances, GcEaSeCounterBlockMaxEvent, GcEaSeCounterBlockNumCounters, GcEaSeCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr};
|
||||
static const GpuBlockInfo GrbmhCounterBlockInfo = {"GRBMH", __BLOCK_ID(GRBMH), GrbmhCounterBlockNumInstances, GrbmhCounterBlockMaxEvent, GrbmhCounterBlockNumCounters, GrbmhCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr};
|
||||
static const GpuBlockInfo SpiCounterBlockInfo = {"SPI", __BLOCK_ID_HSA(SPI), SpiCounterBlockNumInstances, SpiCounterBlockMaxEvent, SpiCounterBlockNumCounters, SpiCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr|CounterBlockSPIAttr, NULL, SPM_SE_BLOCK_NAME_SPI};
|
||||
static const GpuBlockInfo SqgCounterBlockInfo = {"SQG", __BLOCK_ID(SQG), SqgCounterBlockNumInstances, SqgCounterBlockMaxEvent, SqgCounterBlockNumCounters, SqgCounterRegAddr, gfx12_cntx_prim::sq_select_value, CounterBlockSeAttr|CounterBlockSqAttr, NULL, SPM_SE_BLOCK_NAME_SQG};
|
||||
static const GpuBlockInfo GcUtcl1CounterBlockInfo = {"GC_UTCL1", __BLOCK_ID(GC_UTCL1), Utcl1CounterBlockNumInstances, Utcl1CounterBlockMaxEvent, Utcl1CounterBlockNumCounters, Utcl1CounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr, NULL, SPM_SE_BLOCK_NAME_UTCL1};
|
||||
static const GpuBlockInfo GceaSeCounterBlockInfo = {"GCEA_SE", __BLOCK_ID(GCEA_SE), GcEaSeCounterBlockNumInstances, GcEaSeCounterBlockMaxEvent, GcEaSeCounterBlockNumCounters, GcEaSeCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo GrbmhCounterBlockInfo = {"GRBMH", __BLOCK_ID(GRBMH), GrbmhCounterBlockNumInstances, GrbmhCounterBlockMaxEvent, GrbmhCounterBlockNumCounters, GrbmhCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo SpiCounterBlockInfo = {"SPI", __BLOCK_ID_HSA(SPI), SpiCounterBlockNumInstances, SpiCounterBlockMaxEvent, SpiCounterBlockNumCounters, SpiCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr|CounterBlockSPIAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo SqgCounterBlockInfo = {"SQG", __BLOCK_ID(SQG), SqgCounterBlockNumInstances, SqgCounterBlockMaxEvent, SqgCounterBlockNumCounters, SqgCounterRegAddr, gfx12_cntx_prim::sq_select_value, CounterBlockSeAttr|CounterBlockSqAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo GcUtcl1CounterBlockInfo = {"GC_UTCL1", __BLOCK_ID(GC_UTCL1), Utcl1CounterBlockNumInstances, Utcl1CounterBlockMaxEvent, Utcl1CounterBlockNumCounters, Utcl1CounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr, BLOCK_DELAY_NONE};
|
||||
// SA blocks: GL1A GL1C
|
||||
// (Grphics only - not supported in ROCm): CB DB SC SX
|
||||
// (Not enabled for gfx12): GL1CG
|
||||
static const GpuBlockInfo Gl1aCounterBlockInfo = {"GL1A", __BLOCK_ID_HSA(GL1A), Gl1aCounterBlockNumInstances, Gl1aCounterBlockMaxEvent, Gl1aCounterBlockNumCounters, Gl1aCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr|CounterBlockSaAttr|CounterBlockTcAttr};
|
||||
static const GpuBlockInfo Gl1cCounterBlockInfo = {"GL1C", __BLOCK_ID_HSA(GL1C), Gl1cCounterBlockNumInstances, Gl1cCounterBlockMaxEvent, Gl1cCounterBlockNumCounters, Gl1cCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr|CounterBlockSaAttr|CounterBlockTcAttr};
|
||||
static const GpuBlockInfo Gl1aCounterBlockInfo = {"GL1A", __BLOCK_ID_HSA(GL1A), Gl1aCounterBlockNumInstances, Gl1aCounterBlockMaxEvent, Gl1aCounterBlockNumCounters, Gl1aCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr|CounterBlockSaAttr|CounterBlockTcAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo Gl1cCounterBlockInfo = {"GL1C", __BLOCK_ID_HSA(GL1C), Gl1cCounterBlockNumInstances, Gl1cCounterBlockMaxEvent, Gl1cCounterBlockNumCounters, Gl1cCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr|CounterBlockSaAttr|CounterBlockTcAttr, BLOCK_DELAY_NONE};
|
||||
// WGP blocks: SQC TA TCP TD
|
||||
static const GpuBlockInfo SqcCounterBlockInfo = {"SQ", __BLOCK_ID_HSA(SQ), SqcCounterBlockNumInstances, SqcCounterBlockMaxEvent, SqcCounterBlockNumCounters, SqcCounterRegAddr, gfx12_cntx_prim::sq_select_value, CounterBlockSeAttr|CounterBlockSaAttr|CounterBlockWgpAttr|CounterBlockSqAttr, NULL, SPM_SE_BLOCK_NAME_SQC};
|
||||
static const GpuBlockInfo TaCounterBlockInfo = {"TA", __BLOCK_ID_HSA(TA), TaCounterBlockNumInstances, TaCounterBlockMaxEvent, TaCounterBlockNumCounters, TaCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr|CounterBlockSaAttr|CounterBlockWgpAttr|CounterBlockTcAttr, NULL/*TaBlockDelayInfo*/, SPM_SE_BLOCK_NAME_TA};
|
||||
static const GpuBlockInfo TdCounterBlockInfo = {"TD", __BLOCK_ID_HSA(TD), TdCounterBlockNumInstances, TdCounterBlockMaxEvent, TdCounterBlockNumCounters, TdCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr|CounterBlockSaAttr|CounterBlockWgpAttr|CounterBlockTcAttr, NULL/*TdBlockDelayInfo*/, SPM_SE_BLOCK_NAME_TD};
|
||||
static const GpuBlockInfo TcpCounterBlockInfo = {"TCP", __BLOCK_ID_HSA(TCP), TcpCounterBlockNumInstances, TcpCounterBlockMaxEvent, TcpCounterBlockNumCounters, TcpCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr|CounterBlockSaAttr|CounterBlockWgpAttr|CounterBlockTcAttr, NULL/*TdBlockDelayInfo*/, SPM_SE_BLOCK_NAME_TCP};
|
||||
static const GpuBlockInfo SqcCounterBlockInfo = {"SQ", __BLOCK_ID_HSA(SQ), SqcCounterBlockNumInstances, SqcCounterBlockMaxEvent, SqcCounterBlockNumCounters, SqcCounterRegAddr, gfx12_cntx_prim::sq_select_value, CounterBlockSeAttr|CounterBlockSaAttr|CounterBlockWgpAttr|CounterBlockSqAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo TaCounterBlockInfo = {"TA", __BLOCK_ID_HSA(TA), TaCounterBlockNumInstances, TaCounterBlockMaxEvent, TaCounterBlockNumCounters, TaCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr|CounterBlockSaAttr|CounterBlockWgpAttr|CounterBlockTcAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo TdCounterBlockInfo = {"TD", __BLOCK_ID_HSA(TD), TdCounterBlockNumInstances, TdCounterBlockMaxEvent, TdCounterBlockNumCounters, TdCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr|CounterBlockSaAttr|CounterBlockWgpAttr|CounterBlockTcAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo TcpCounterBlockInfo = {"TCP", __BLOCK_ID_HSA(TCP), TcpCounterBlockNumInstances, TcpCounterBlockMaxEvent, TcpCounterBlockNumCounters, TcpCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr|CounterBlockSaAttr|CounterBlockWgpAttr|CounterBlockTcAttr, BLOCK_DELAY_NONE};
|
||||
} // namespace gfx1200
|
||||
|
||||
namespace gfx1201 {
|
||||
static const GpuBlockInfo Gl2cCounterBlockInfo = {"GL2C", __BLOCK_ID_HSA(GL2C), gfx1201::Gl2cCounterBlockNumInstances, Gl2cCounterBlockMaxEvent, Gl2cCounterBlockNumCounters, Gl2cCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockTcAttr};
|
||||
static const GpuBlockInfo ChcCounterBlockInfo = {"CHC", __BLOCK_ID(CHC), gfx1201::ChcCounterBlockNumInstances, ChcCounterBlockMaxEvent, ChcCounterBlockNumCounters, ChcCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockTcAttr};
|
||||
static const GpuBlockInfo GceaCounterBlockInfo = {"GCEA", __BLOCK_ID_HSA(GCEA), gfx1201::GcEaCpwdCounterBlockNumInstances, GcEaCpwdCounterBlockMaxEvent, GcEaCpwdCounterBlockNumCounters, GcEaCpwdCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr};
|
||||
static const GpuBlockInfo GceaSeCounterBlockInfo = {"GCEA_SE", __BLOCK_ID(GCEA_SE), gfx1201::GcEaSeCounterBlockNumInstances, GcEaSeCounterBlockMaxEvent, GcEaSeCounterBlockNumCounters, GcEaSeCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr};
|
||||
static const GpuBlockInfo Gl2cCounterBlockInfo = {"GL2C", __BLOCK_ID_HSA(GL2C), gfx1201::Gl2cCounterBlockNumInstances, Gl2cCounterBlockMaxEvent, Gl2cCounterBlockNumCounters, Gl2cCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockTcAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo ChcCounterBlockInfo = {"CHC", __BLOCK_ID(CHC), gfx1201::ChcCounterBlockNumInstances, ChcCounterBlockMaxEvent, ChcCounterBlockNumCounters, ChcCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockTcAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo GceaCounterBlockInfo = {"GCEA", __BLOCK_ID_HSA(GCEA), gfx1201::GcEaCpwdCounterBlockNumInstances, GcEaCpwdCounterBlockMaxEvent, GcEaCpwdCounterBlockNumCounters, GcEaCpwdCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr, BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo GceaSeCounterBlockInfo = {"GCEA_SE", __BLOCK_ID(GCEA_SE), gfx1201::GcEaSeCounterBlockNumInstances, GcEaSeCounterBlockMaxEvent, GcEaSeCounterBlockNumCounters, GcEaSeCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr, BLOCK_DELAY_NONE};
|
||||
} // namespace gfx1201
|
||||
|
||||
} // namespace gfx12
|
||||
|
||||
@@ -113,6 +113,7 @@ class gfx12_cntx_prim {
|
||||
REG_32B_ADDR(GC, 0, regRLC_SPM_SE_MUXSEL_ADDR);
|
||||
static constexpr Register RLC_SPM_SE_MUXSEL_DATA__ADDR =
|
||||
REG_32B_ADDR(GC, 0, regRLC_SPM_SE_MUXSEL_DATA);
|
||||
static constexpr Register RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__ADDR = REG_32B_NULL;
|
||||
static const uint32_t RLC_SPM_COUNTERS_PER_LINE = 16;
|
||||
static const uint32_t RLC_SPM_TIMESTAMP_SIZE16 = 4;
|
||||
|
||||
@@ -153,7 +154,7 @@ class gfx12_cntx_prim {
|
||||
static uint32_t get_spm_global_delay(const counter_des_t& counter_des,
|
||||
const uint32_t& instance_index) {
|
||||
const auto* block_info = counter_des.block_info;
|
||||
return block_info->delay_info[instance_index].val - 1;
|
||||
return block_info->delay_info.val[instance_index];
|
||||
}
|
||||
|
||||
// SPM delay functions for se instance
|
||||
@@ -161,7 +162,7 @@ class gfx12_cntx_prim {
|
||||
const uint32_t& instance_index) {
|
||||
const auto* block_info = counter_des.block_info;
|
||||
int delay_index = se_index * block_info->instance_count + instance_index;
|
||||
return block_info->delay_info[delay_index].val - 1;
|
||||
return block_info->delay_info.val[delay_index];
|
||||
}
|
||||
|
||||
// GRBM broadcasting mode
|
||||
|
||||
@@ -34,52 +34,46 @@ namespace gfx9 {
|
||||
*/
|
||||
static const CounterRegInfo SqCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER0_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER0_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER1_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER1_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER2_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER3_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER3_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER3_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER4_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER4_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER4_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER4_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER4_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER5_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER5_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER5_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER5_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER5_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER6_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER6_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER6_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER6_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER6_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER7_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER7_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER7_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER7_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER7_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER8_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER8_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER8_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER8_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER8_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER9_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER9_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER9_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER9_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER9_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER10_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER10_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER10_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER10_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER10_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER11_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER11_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER11_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER11_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER11_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER12_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER12_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER12_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER12_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER12_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER13_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER13_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER13_HI)},
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||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER13_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER13_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER14_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER14_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER14_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER14_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER14_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER15_SELECT), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER_CTRL),
|
||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER15_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER15_HI)}};
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||||
REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER15_LO), REG_32B_ADDR(GC, 0, mmSQ_PERFCOUNTER15_HI), REG_32B_NULL}};
|
||||
|
||||
static const BlockDelayInfo SqBlockDelayInfo[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY), 0x0000002c},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY), 0x00000029},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY), 0x0000002a},
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||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY), 0x00000027},
|
||||
};
|
||||
/*
|
||||
* GRBM
|
||||
*/
|
||||
static const CounterRegInfo GrbmCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER0_HI)},
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||||
REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER0_HI), REG_32B_NULL},
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||||
{REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER1_SELECT), REG_32B_NULL,
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||||
REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER1_HI)}};
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||||
REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmGRBM_PERFCOUNTER1_HI), REG_32B_NULL}};
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||||
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||||
/*
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||||
* GRBM_SE
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||||
@@ -87,650 +81,399 @@ static const CounterRegInfo GrbmCounterRegAddr[] = {
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||||
static const CounterRegInfo GrbmSeCounterRegAddr[] = {
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{REG_32B_ADDR(GC, 0, mmGRBM_SE0_PERFCOUNTER_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmGRBM_SE0_PERFCOUNTER_LO),
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||||
REG_32B_ADDR(GC, 0, mmGRBM_SE0_PERFCOUNTER_HI)},
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REG_32B_ADDR(GC, 0, mmGRBM_SE0_PERFCOUNTER_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmGRBM_SE1_PERFCOUNTER_SELECT), REG_32B_NULL,
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||||
REG_32B_ADDR(GC, 0, mmGRBM_SE1_PERFCOUNTER_LO),
|
||||
REG_32B_ADDR(GC, 0, mmGRBM_SE1_PERFCOUNTER_HI)},
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REG_32B_ADDR(GC, 0, mmGRBM_SE1_PERFCOUNTER_HI), REG_32B_NULL},
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||||
{REG_32B_ADDR(GC, 0, mmGRBM_SE2_PERFCOUNTER_SELECT), REG_32B_NULL,
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||||
REG_32B_ADDR(GC, 0, mmGRBM_SE2_PERFCOUNTER_LO),
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||||
REG_32B_ADDR(GC, 0, mmGRBM_SE2_PERFCOUNTER_HI)},
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REG_32B_ADDR(GC, 0, mmGRBM_SE2_PERFCOUNTER_HI), REG_32B_NULL},
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{REG_32B_ADDR(GC, 0, mmGRBM_SE3_PERFCOUNTER_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmGRBM_SE3_PERFCOUNTER_LO),
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||||
REG_32B_ADDR(GC, 0, mmGRBM_SE3_PERFCOUNTER_HI)}};
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REG_32B_ADDR(GC, 0, mmGRBM_SE3_PERFCOUNTER_HI), REG_32B_NULL}};
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||||
/*
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||||
* PA_SU
|
||||
*/
|
||||
static const CounterRegInfo PaSuCounterRegAddr[] = {
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||||
{REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER0_SELECT), REG_32B_NULL,
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||||
REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER0_HI)},
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||||
REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER0_SELECT1)},
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{REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER1_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER1_HI)},
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REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER1_SELECT1)},
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{REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER2_SELECT), REG_32B_NULL,
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REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER2_HI)},
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||||
REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER2_HI), REG_32B_NULL},
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||||
{REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER3_SELECT), REG_32B_NULL,
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||||
REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER3_HI)}};
|
||||
|
||||
static const BlockDelayInfo PaSuBlockDelayInfo[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY), 0x00000022},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY), 0x00000022},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY), 0x00000020},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY), 0x00000020}};
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||||
REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmPA_SU_PERFCOUNTER3_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* PA_SC
|
||||
*/
|
||||
static const CounterRegInfo PaScCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER0_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER1_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER3_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER3_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER4_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER4_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER4_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER4_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER4_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER5_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER5_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER5_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER5_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER5_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER6_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER6_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER6_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER6_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER6_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER7_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER7_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER7_HI)}};
|
||||
|
||||
static const BlockDelayInfo PaScBlockDelayInfo[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY), 0x00000026},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY), 0x00000026},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY), 0x00000022},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY), 0x00000022},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY), 0x00000023},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY), 0x00000023},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY), 0x00000021},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY), 0x00000021}};
|
||||
REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER7_LO), REG_32B_ADDR(GC, 0, mmPA_SC_PERFCOUNTER7_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* SPI
|
||||
*/
|
||||
static const CounterRegInfo SpiCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER0_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER1_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER2_HI), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER2_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER3_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER3_HI), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER3_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER4_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER4_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER4_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER4_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER4_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER5_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER5_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER5_HI)}};
|
||||
|
||||
static const BlockDelayInfo SpiBlockDelayInfo[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY), 0x0000002a},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY), 0x0000002a},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY), 0x00000027},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY), 0x00000027}};
|
||||
REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER5_LO), REG_32B_ADDR(GC, 0, mmSPI_PERFCOUNTER5_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* TCA
|
||||
*/
|
||||
static const CounterRegInfo TcaCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER0_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER1_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER3_HI)}};
|
||||
|
||||
static const BlockDelayInfo TcaBlockDelayInfo[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY), 0x00000018},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY), 0x0000001c}};
|
||||
REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmTCA_PERFCOUNTER3_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* TCC
|
||||
*/
|
||||
static const CounterRegInfo TccCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER0_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER1_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER3_HI)}};
|
||||
|
||||
static const BlockDelayInfo TccBlockDelayInfo[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY), 0x0000000F},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY), 0x00000015},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY), 0x00000017},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY), 0x0000001d},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY), 0x0000001b},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY), 0x00000017},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY), 0x00000013},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY), 0x0000000f},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY), 0x00000014},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY), 0x00000018},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY), 0x0000001c},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY), 0x00000020},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY), 0x0000001d},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY), 0x00000019},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY), 0x00000015},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY), 0x00000011}};
|
||||
REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmTCC_PERFCOUNTER3_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* TCP
|
||||
*/
|
||||
static const CounterRegInfo TcpCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER0_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER1_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER3_HI)}};
|
||||
|
||||
static const BlockDelayInfo TcpBlockDelayInfo[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000030}, // se0
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000002e},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000002c},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000002a},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000028},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000026},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000024},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000022},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000020},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000001e},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000001c},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000001a},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000018},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000016},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000014},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000012},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000002c}, // se1
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000002a},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000028},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000026},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000024},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000022},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000020},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000001e},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000001c},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000001a},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000018},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000016},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000014},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000012},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000010},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000000e},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000002c}, // se2
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000002a},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000028},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000026},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000024},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000022},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000020},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000001e},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000001c},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000001a},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000018},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000016},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000014},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000012},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000010},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000000e},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000002c}, // se3
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000028},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000026},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000024},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000022},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000020},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000001e},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000001c},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000001a},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000018},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000016},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000014},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000012},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x00000010},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000000e},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), 0x0000000c}};
|
||||
REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmTCP_PERFCOUNTER3_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* CB
|
||||
*/
|
||||
static const CounterRegInfo CbCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER0_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER1_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER3_HI)}};
|
||||
|
||||
static const BlockDelayInfo CbBlockDelayInfo[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY), 0x0000001d},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY), 0x00000008},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY), 0x00000014},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY), 0x00000011},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY), 0x00000019},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY), 0x00000004},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY), 0x00000010},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY), 0x0000000d},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY), 0x00000019},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY), 0x00000005},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY), 0x00000011},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY), 0x0000000e},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY), 0x00000015},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY), 0x00000000},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY), 0x0000000c},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY), 0x00000009}};
|
||||
REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmCB_PERFCOUNTER3_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* DB
|
||||
*/
|
||||
static const CounterRegInfo DbCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER0_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER1_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER3_HI)}};
|
||||
|
||||
static const BlockDelayInfo DbBlockDelayInfo[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY), 0x0000001b},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY), 0x0000000c},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY), 0x00000017},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY), 0x00000010},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY), 0x00000017},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY), 0x00000008},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY), 0x00000013},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY), 0x0000000c},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY), 0x00000017},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY), 0x00000009},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY), 0x00000014},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY), 0x0000000d},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY), 0x00000013},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY), 0x00000008},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY), 0x0000000f},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY), 0x00000008}};
|
||||
REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmDB_PERFCOUNTER3_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* RLC
|
||||
*/
|
||||
static const CounterRegInfo RlcCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmRLC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmRLC_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmRLC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmRLC_PERFCOUNTER0_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmRLC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmRLC_PERFCOUNTER1_HI)}};
|
||||
REG_32B_ADDR(GC, 0, mmRLC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmRLC_PERFCOUNTER1_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* SX
|
||||
*/
|
||||
static const CounterRegInfo SxCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER0_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER1_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER3_HI)}};
|
||||
|
||||
static const BlockDelayInfo SxBlockDelayInfo[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY), 0x00000006},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY), 0x00000006},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY), 0x00000008},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY), 0x00000004}};
|
||||
REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmSX_PERFCOUNTER3_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* TA
|
||||
*/
|
||||
static const CounterRegInfo TaCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER0_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER1_HI)}};
|
||||
|
||||
static const BlockDelayInfo TaBlockDelayInfo[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000002c},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000002a},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000028},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000026},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000024},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000022},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000020},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000001e},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000001c},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000001a},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000018},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000016},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000014},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000012},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000010},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000000e},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000028},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000026},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000025},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000023},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000021},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000001f},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000001d},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000001b},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000019},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000017},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000015},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000013},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000011},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000000f},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000000d},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000000b},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000028},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000026},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000024},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000022},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000020},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000001e},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000001c},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000001a},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000018},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000016},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000014},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000012},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000010},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000000e},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000000c},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000000a},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000027},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000025},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000023},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000021},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000001f},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000001d},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000001b},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000019},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000017},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000015},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000013},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000011},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000000f},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000000d},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x0000000b},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), 0x00000009}};
|
||||
REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmTA_PERFCOUNTER1_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* TD
|
||||
*/
|
||||
static const CounterRegInfo TdCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmTD_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmTD_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmTD_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmTD_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmTD_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmTD_PERFCOUNTER0_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmTD_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmTD_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmTD_PERFCOUNTER1_HI)}};
|
||||
|
||||
static const BlockDelayInfo TdBlockDelayInfo[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000002c},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000002a},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000028},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000026},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000024},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000022},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000020},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000001e},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000001c},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000001a},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000018},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000016},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000014},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000012},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000010},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000000e},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000028},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000026},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000025},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000023},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000021},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000001f},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000001d},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000001b},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000019},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000017},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000015},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000013},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000011},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000000f},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000000d},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000000b},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000028},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000027},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000025},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000023},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000021},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000001f},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000001d},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000001b},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000019},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000017},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000015},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000013},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000011},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000000f},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000000d},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000000b},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000027},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000025},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000023},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000021},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000001f},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000001d},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000001b},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000019},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000017},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000015},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000013},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000011},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000000f},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000000d},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x0000000b},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), 0x00000009}};
|
||||
REG_32B_ADDR(GC, 0, mmTD_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmTD_PERFCOUNTER1_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* GDS
|
||||
*/
|
||||
static const CounterRegInfo GdsCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER0_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER1_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER3_HI)}};
|
||||
|
||||
static const BlockDelayInfo GdsBlockDelayInfo[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY), 0x0000002d}};
|
||||
REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmGDS_PERFCOUNTER3_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* VGT
|
||||
*/
|
||||
static const CounterRegInfo VgtCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER0_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER1_HI), REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER1_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER3_HI)}};
|
||||
|
||||
static const BlockDelayInfo VgtBlockDelayInfo[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY), 0x00000027},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY), 0x00000027},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY), 0x00000023},
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY), 0x00000024}};
|
||||
REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmVGT_PERFCOUNTER3_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* IA
|
||||
*/
|
||||
static const CounterRegInfo IaCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER0_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER1_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER3_HI)}};
|
||||
|
||||
static const BlockDelayInfo IaBlockDelayInfo[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY), 0x00000032}};
|
||||
REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmIA_PERFCOUNTER3_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* WD
|
||||
*/
|
||||
static const CounterRegInfo WdCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER0_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER1_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER2_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER2_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER3_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER3_HI)}};
|
||||
REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmWD_PERFCOUNTER3_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* CPC
|
||||
*/
|
||||
static const CounterRegInfo CpcCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER0_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER1_HI)}};
|
||||
|
||||
static const BlockDelayInfo CpcBlockDelayInfo[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY), 0x0000002c}};
|
||||
REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmCPC_PERFCOUNTER1_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* CPF
|
||||
*/
|
||||
static const CounterRegInfo CpfCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER0_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER1_HI)}};
|
||||
|
||||
static const BlockDelayInfo CpfBlockDelayInfo[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY), 0x00000032}};
|
||||
REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmCPF_PERFCOUNTER1_HI), REG_32B_NULL}};
|
||||
|
||||
/*
|
||||
* CPG
|
||||
*/
|
||||
static const CounterRegInfo CpgCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmCPG_PERFCOUNTER0_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmCPG_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmCPG_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmCPG_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmCPG_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmCPG_PERFCOUNTER0_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmCPG_PERFCOUNTER1_SELECT), REG_32B_NULL,
|
||||
REG_32B_ADDR(GC, 0, mmCPG_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmCPG_PERFCOUNTER1_HI)}};
|
||||
|
||||
static const BlockDelayInfo CpgBlockDelayInfo[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY), 0x00000030}};
|
||||
REG_32B_ADDR(GC, 0, mmCPG_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmCPG_PERFCOUNTER1_HI), REG_32B_NULL}};
|
||||
|
||||
// RMI
|
||||
static const CounterRegInfo RmiCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER0_SELECT), REG_32B_ADDR(GC, 0, mmRMI_PERF_COUNTER_CNTL),
|
||||
REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER0_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER0_LO), REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER0_HI), REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER0_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER1_SELECT), REG_32B_ADDR(GC, 0, mmRMI_PERF_COUNTER_CNTL),
|
||||
REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER1_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER1_LO), REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER1_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER2_SELECT), REG_32B_ADDR(GC, 0, mmRMI_PERF_COUNTER_CNTL),
|
||||
REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER2_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER2_LO), REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER2_HI), REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER2_SELECT1)},
|
||||
{REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER3_SELECT), REG_32B_ADDR(GC, 0, mmRMI_PERF_COUNTER_CNTL),
|
||||
REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER3_HI)}};
|
||||
REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER3_LO), REG_32B_ADDR(GC, 0, mmRMI_PERFCOUNTER3_HI), REG_32B_NULL}};
|
||||
|
||||
// GCEA
|
||||
static const CounterRegInfo GceaCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER0_CFG),
|
||||
REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER_RSLT_CNTL), REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER_LO),
|
||||
REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER1_CFG),
|
||||
REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER_RSLT_CNTL), REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER_LO),
|
||||
REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER_HI)}};
|
||||
REG_32B_ADDR(GC, 0, mmGCEA_PERFCOUNTER_HI), REG_32B_NULL}};
|
||||
|
||||
// ATC
|
||||
static const CounterRegInfo AtcCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER0_CFG),
|
||||
REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_RSLT_CNTL),
|
||||
REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER1_CFG),
|
||||
REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_RSLT_CNTL),
|
||||
REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER2_CFG),
|
||||
REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_RSLT_CNTL),
|
||||
REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER3_CFG),
|
||||
REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_RSLT_CNTL),
|
||||
REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_HI)}};
|
||||
REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmATC_PERFCOUNTER_HI), REG_32B_NULL}};
|
||||
|
||||
// ATC L2
|
||||
static const CounterRegInfo AtcL2CounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmATC_L2_PERFCOUNTER0_CFG),
|
||||
REG_32B_ADDR(GC, 0, mmATC_L2_PERFCOUNTER_RSLT_CNTL),
|
||||
REG_32B_ADDR(GC, 0, mmATC_L2_PERFCOUNTER_LO), REG_32B_ADDR(GC, 0, mmATC_L2_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmATC_L2_PERFCOUNTER_LO), REG_32B_ADDR(GC, 0, mmATC_L2_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmATC_L2_PERFCOUNTER1_CFG),
|
||||
REG_32B_ADDR(GC, 0, mmATC_L2_PERFCOUNTER_RSLT_CNTL),
|
||||
REG_32B_ADDR(GC, 0, mmATC_L2_PERFCOUNTER_LO), REG_32B_ADDR(GC, 0, mmATC_L2_PERFCOUNTER_HI)}};
|
||||
REG_32B_ADDR(GC, 0, mmATC_L2_PERFCOUNTER_LO), REG_32B_ADDR(GC, 0, mmATC_L2_PERFCOUNTER_HI), REG_32B_NULL}};
|
||||
|
||||
// RPB
|
||||
static const CounterRegInfo RpbCounterRegAddr[] = {
|
||||
{REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER0_CFG),
|
||||
REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_RSLT_CNTL),
|
||||
REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER1_CFG),
|
||||
REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_RSLT_CNTL),
|
||||
REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER2_CFG),
|
||||
REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_RSLT_CNTL),
|
||||
REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER3_CFG),
|
||||
REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_RSLT_CNTL),
|
||||
REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_HI)}};
|
||||
REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_LO), REG_32B_ADDR(ATHUB, 0, mmRPB_PERFCOUNTER_HI), REG_32B_NULL}};
|
||||
|
||||
// MC VM L2
|
||||
static const CounterRegInfo McVmL2CounterRegAddr[] = {
|
||||
{REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER0_CFG),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_LO),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER1_CFG),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_LO),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER2_CFG),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_LO),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER3_CFG),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_LO),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER4_CFG),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_LO),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER5_CFG),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_LO),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER6_CFG),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_LO),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI)},
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL},
|
||||
{REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER7_CFG),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_LO),
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI)}};
|
||||
REG_32B_ADDR(GC, 0, mmMC_VM_L2_PERFCOUNTER_HI), REG_32B_NULL}};
|
||||
|
||||
// BlockDelayInfo for SPM
|
||||
static const uint32_t SqBlockDelayValue[] = {0x3b, 0x38, 0x39, 0x36}; // Verified
|
||||
static const uint32_t PaSuBlockDelayValue[] = {0x22, 0x22, 0x20, 0x20};
|
||||
static const uint32_t PaScBlockDelayValue[] = {0x26, 0x26, 0x22, 0x22, 0x23, 0x23, 0x21, 0x21};
|
||||
static const uint32_t SpiBlockDelayValue[] = {0x39, 0x39, 0x36, 0x36}; // Verified
|
||||
static const uint32_t TcaBlockDelayValue[] = {0x18, 0x1c};
|
||||
static const uint32_t TccBlockDelayValue[] = {
|
||||
0x0f, 0x15, 0x17, 0x1d, 0x1b, 0x17, 0x13, 0x0f, 0x14, 0x18, 0x1c, 0x20, 0x1d, 0x19, 0x15, 0x11};
|
||||
static const uint32_t TcpBlockDelayValue[] = {
|
||||
0x30, 0x2e, 0x2c, 0x2a, 0x28, 0x26, 0x24, 0x22, 0x20, 0x1e, 0x1c, 0x1a, 0x18, 0x16, 0x14, 0x12, // se0
|
||||
0x2c, 0x2a, 0x28, 0x26, 0x24, 0x22, 0x20, 0x1e, 0x1c, 0x1a, 0x18, 0x16, 0x14, 0x12, 0x10, 0x0e, // se1
|
||||
0x2c, 0x2a, 0x28, 0x26, 0x24, 0x22, 0x20, 0x1e, 0x1c, 0x1a, 0x18, 0x16, 0x14, 0x12, 0x10, 0x0e, // se2
|
||||
0x2c, 0x28, 0x26, 0x24, 0x22, 0x20, 0x1e, 0x1c, 0x1a, 0x18, 0x16, 0x14, 0x12, 0x10, 0x0e, 0x0c}; // se3
|
||||
static const uint32_t CbBlockDelayValue[] = {
|
||||
0x1d, 0x08, 0x14, 0x11, 0x19, 0x04, 0x10, 0x0d, 0x19, 0x05, 0x11, 0x0e, 0x15, 0x00, 0x0c, 0x09};
|
||||
static const uint32_t DbBlockDelayValue[] = {
|
||||
0x1b, 0x0c, 0x17, 0x10, 0x17, 0x08, 0x13, 0x0c, 0x17, 0x09, 0x14, 0x0d, 0x13, 0x08, 0x0f, 0x08};
|
||||
static const uint32_t SxBlockDelayValue[] = {0x06, 0x06, 0x08, 0x04};
|
||||
static const uint32_t TaBlockDelayValue[] = {
|
||||
0x2c, 0x2a, 0x28, 0x26, 0x24, 0x22, 0x20, 0x1e, 0x1c, 0x1a, 0x18, 0x16, 0x14, 0x12, 0x10, 0x0e,
|
||||
0x28, 0x26, 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b,
|
||||
0x28, 0x26, 0x24, 0x22, 0x20, 0x1e, 0x1c, 0x1a, 0x18, 0x16, 0x14, 0x12, 0x10, 0x0e, 0x0c, 0x0a,
|
||||
0x27, 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b, 0x09};
|
||||
static const uint32_t TdBlockDelayValue[] = {
|
||||
0x2c, 0x2a, 0x28, 0x26, 0x24, 0x22, 0x20, 0x1e, 0x1c, 0x1a, 0x18, 0x16, 0x14, 0x12, 0x10, 0x0e,
|
||||
0x28, 0x26, 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b,
|
||||
0x28, 0x27, 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b,
|
||||
0x27, 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b, 0x09};
|
||||
static const uint32_t GdsBlockDelayValue[] = {0x2d};
|
||||
static const uint32_t VgtBlockDelayValue[] = {0x27, 0x27, 0x23, 0x24};
|
||||
static const uint32_t IaBlockDelayValue[] = {0x32};
|
||||
static const uint32_t CpcBlockDelayValue[] = {0x3c};
|
||||
static const uint32_t CpfBlockDelayValue[] = {0x32};
|
||||
static const uint32_t CpgBlockDelayValue[] = {0x30}; // Verified
|
||||
|
||||
static const BlockDelayInfo SqBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY), SqBlockDelayValue};
|
||||
static const BlockDelayInfo PaSuBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY), PaSuBlockDelayValue};
|
||||
static const BlockDelayInfo PaScBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY), PaScBlockDelayValue};
|
||||
static const BlockDelayInfo SpiBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY), SpiBlockDelayValue};
|
||||
static const BlockDelayInfo TcaBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY), TcaBlockDelayValue};
|
||||
static const BlockDelayInfo TccBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY), TccBlockDelayValue};
|
||||
static const BlockDelayInfo TcpBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY), TcpBlockDelayValue};
|
||||
static const BlockDelayInfo CbBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY), CbBlockDelayValue};
|
||||
static const BlockDelayInfo DbBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY), DbBlockDelayValue};
|
||||
static const BlockDelayInfo SxBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY), SxBlockDelayValue};
|
||||
static const BlockDelayInfo TaBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY), TaBlockDelayValue};
|
||||
static const BlockDelayInfo TdBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY), TdBlockDelayValue};
|
||||
static const BlockDelayInfo GdsBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY), GdsBlockDelayValue};
|
||||
static const BlockDelayInfo VgtBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY), VgtBlockDelayValue};
|
||||
static const BlockDelayInfo IaBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY), IaBlockDelayValue};
|
||||
static const BlockDelayInfo CpcBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY), CpcBlockDelayValue};
|
||||
static const BlockDelayInfo CpfBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY), CpfBlockDelayValue};
|
||||
static const BlockDelayInfo CpgBlockDelayInfo = {REG_32B_ADDR(GC, 0, mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY), CpgBlockDelayValue};
|
||||
|
||||
// Counter block info table
|
||||
// SPM global blocks: CPG, CPC, CPF, GDS, TCC, TCA, IA, TCS
|
||||
@@ -766,7 +509,8 @@ static const GpuBlockInfo GrbmCounterBlockInfo = {
|
||||
GrbmCounterBlockNumCounters,
|
||||
GrbmCounterRegAddr,
|
||||
gfx9_cntx_prim::select_value_GRBM_PERFCOUNTER0_SELECT,
|
||||
CounterBlockDfltAttr | CounterBlockGRBMAttr};
|
||||
CounterBlockDfltAttr | CounterBlockGRBMAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block GRBMSE
|
||||
static const GpuBlockInfo GrbmSeCounterBlockInfo = {
|
||||
"GRBM_SE",
|
||||
@@ -776,7 +520,8 @@ static const GpuBlockInfo GrbmSeCounterBlockInfo = {
|
||||
GrbmSeCounterBlockNumCounters,
|
||||
GrbmSeCounterRegAddr,
|
||||
gfx9_cntx_prim::select_value_GRBM_SE0_PERFCOUNTER_SELECT,
|
||||
CounterBlockDfltAttr};
|
||||
CounterBlockDfltAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block PA_SU
|
||||
static const GpuBlockInfo PaSuCounterBlockInfo = {
|
||||
"PA_SU",
|
||||
@@ -831,7 +576,8 @@ static const GpuBlockInfo SqGsCounterBlockInfo = {"SQ_GS",
|
||||
SqCounterBlockNumCounters,
|
||||
SqCounterRegAddr,
|
||||
gfx9_cntx_prim::sq_select_value,
|
||||
CounterBlockSeAttr | CounterBlockSqAttr};
|
||||
CounterBlockSeAttr | CounterBlockSqAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo SqVsCounterBlockInfo = {"SQ_VS",
|
||||
SqCounterBlockId,
|
||||
1,
|
||||
@@ -839,7 +585,8 @@ static const GpuBlockInfo SqVsCounterBlockInfo = {"SQ_VS",
|
||||
SqCounterBlockNumCounters,
|
||||
SqCounterRegAddr,
|
||||
gfx9_cntx_prim::sq_select_value,
|
||||
CounterBlockSeAttr | CounterBlockSqAttr};
|
||||
CounterBlockSeAttr | CounterBlockSqAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo SqPsCounterBlockInfo = {"SQ_PS",
|
||||
SqCounterBlockId,
|
||||
1,
|
||||
@@ -847,7 +594,8 @@ static const GpuBlockInfo SqPsCounterBlockInfo = {"SQ_PS",
|
||||
SqCounterBlockNumCounters,
|
||||
SqCounterRegAddr,
|
||||
gfx9_cntx_prim::sq_select_value,
|
||||
CounterBlockSeAttr | CounterBlockSqAttr};
|
||||
CounterBlockSeAttr | CounterBlockSqAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo SqHsCounterBlockInfo = {"SQ_HS",
|
||||
SqCounterBlockId,
|
||||
1,
|
||||
@@ -855,7 +603,8 @@ static const GpuBlockInfo SqHsCounterBlockInfo = {"SQ_HS",
|
||||
SqCounterBlockNumCounters,
|
||||
SqCounterRegAddr,
|
||||
gfx9_cntx_prim::sq_select_value,
|
||||
CounterBlockSeAttr | CounterBlockSqAttr};
|
||||
CounterBlockSeAttr | CounterBlockSqAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
static const GpuBlockInfo SqCsCounterBlockInfo = {"SQ_CS",
|
||||
SqCounterBlockId,
|
||||
1,
|
||||
@@ -863,7 +612,8 @@ static const GpuBlockInfo SqCsCounterBlockInfo = {"SQ_CS",
|
||||
SqCounterBlockNumCounters,
|
||||
SqCounterRegAddr,
|
||||
gfx9_cntx_prim::sq_select_value,
|
||||
CounterBlockSeAttr | CounterBlockSqAttr};
|
||||
CounterBlockSeAttr | CounterBlockSqAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block SX
|
||||
static const GpuBlockInfo SxCounterBlockInfo = {"SX",
|
||||
SxCounterBlockId,
|
||||
@@ -976,7 +726,8 @@ static const GpuBlockInfo WdCounterBlockInfo = {"WD",
|
||||
WdCounterBlockNumCounters,
|
||||
WdCounterRegAddr,
|
||||
gfx9_cntx_prim::select_value_WD_PERFCOUNTER0_SELECT,
|
||||
CounterBlockDfltAttr};
|
||||
CounterBlockDfltAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block CPC
|
||||
static const GpuBlockInfo CpcCounterBlockInfo = {
|
||||
"CPC",
|
||||
@@ -1000,7 +751,7 @@ static const GpuBlockInfo CpfCounterBlockInfo = {
|
||||
gfx9_cntx_prim::select_value_CPF_PERFCOUNTER0_SELECT,
|
||||
CounterBlockDfltAttr | CounterBlockSpmGlobalAttr,
|
||||
CpfBlockDelayInfo,
|
||||
SPM_GLOBAL_BLOCK_NAME_CPF /*2*/};
|
||||
SPM_GLOBAL_BLOCK_NAME_CPF};
|
||||
// Counter block MCVM L2
|
||||
static const GpuBlockInfo McVmL2CounterBlockInfo = {
|
||||
"MCVML2",
|
||||
@@ -1010,7 +761,8 @@ static const GpuBlockInfo McVmL2CounterBlockInfo = {
|
||||
McVmL2CounterBlockNumCounters,
|
||||
McVmL2CounterRegAddr,
|
||||
gfx9_cntx_prim::mc_select_value_MC_VM_L2_PERFCOUNTER0_CFG,
|
||||
CounterBlockMcAttr};
|
||||
CounterBlockMcAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block ATC L2
|
||||
static const GpuBlockInfo AtcL2CounterBlockInfo = {
|
||||
"ATCL2",
|
||||
@@ -1020,7 +772,8 @@ static const GpuBlockInfo AtcL2CounterBlockInfo = {
|
||||
AtcL2CounterBlockNumCounters,
|
||||
AtcL2CounterRegAddr,
|
||||
gfx9_cntx_prim::mc_select_value_ATC_L2_PERFCOUNTER0_CFG,
|
||||
CounterBlockMcAttr};
|
||||
CounterBlockMcAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block ATC
|
||||
static const GpuBlockInfo AtcCounterBlockInfo = {
|
||||
"ATC",
|
||||
@@ -1030,7 +783,8 @@ static const GpuBlockInfo AtcCounterBlockInfo = {
|
||||
AtcCounterBlockNumCounters,
|
||||
AtcCounterRegAddr,
|
||||
gfx9_cntx_prim::mc_select_value_ATC_PERFCOUNTER0_CFG,
|
||||
CounterBlockAtcAttr | CounterBlockAidAttr};
|
||||
CounterBlockAtcAttr | CounterBlockAidAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block GCEA
|
||||
static const GpuBlockInfo GceaCounterBlockInfo = {
|
||||
"GCEA",
|
||||
@@ -1040,7 +794,8 @@ static const GpuBlockInfo GceaCounterBlockInfo = {
|
||||
GceaCounterBlockNumCounters,
|
||||
GceaCounterRegAddr,
|
||||
gfx9_cntx_prim::mc_select_value_GCEA_PERFCOUNTER0_CFG,
|
||||
CounterBlockMcAttr};
|
||||
CounterBlockMcAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
// Counter block RPB
|
||||
static const GpuBlockInfo RpbCounterBlockInfo = {
|
||||
"RPB",
|
||||
@@ -1050,7 +805,8 @@ static const GpuBlockInfo RpbCounterBlockInfo = {
|
||||
RpbCounterBlockNumCounters,
|
||||
RpbCounterRegAddr,
|
||||
gfx9_cntx_prim::mc_select_value_RPB_PERFCOUNTER0_CFG,
|
||||
CounterBlockRpbAttr | CounterBlockAidAttr};
|
||||
CounterBlockRpbAttr | CounterBlockAidAttr,
|
||||
BLOCK_DELAY_NONE};
|
||||
|
||||
} // namespace gfx9
|
||||
} // namespace gfxip
|
||||
|
||||
@@ -133,6 +133,8 @@ class gfx9_cntx_prim {
|
||||
REG_32B_ADDR(GC, 0, mmRLC_SPM_SE_MUXSEL_ADDR);
|
||||
static constexpr Register RLC_SPM_SE_MUXSEL_DATA__ADDR =
|
||||
REG_32B_ADDR(GC, 0, mmRLC_SPM_SE_MUXSEL_DATA);
|
||||
static constexpr Register RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__ADDR =
|
||||
REG_32B_ADDR(GC, 0, mmRLC_SPM_PERFMON_SAMPLE_DELAY_MAX);
|
||||
static const uint32_t RLC_SPM_COUNTERS_PER_LINE = 16;
|
||||
static const uint32_t RLC_SPM_TIMESTAMP_SIZE16 = 4;
|
||||
|
||||
@@ -189,7 +191,7 @@ class gfx9_cntx_prim {
|
||||
static uint32_t get_spm_global_delay(const counter_des_t& counter_des,
|
||||
const uint32_t& instance_index) {
|
||||
const auto* block_info = counter_des.block_info;
|
||||
return block_info->delay_info[instance_index].val - 1;
|
||||
return block_info->delay_info.val[instance_index];
|
||||
}
|
||||
|
||||
// SPM delay functions for se instance
|
||||
@@ -197,7 +199,7 @@ class gfx9_cntx_prim {
|
||||
const uint32_t& instance_index) {
|
||||
const auto* block_info = counter_des.block_info;
|
||||
int delay_index = se_index * block_info->instance_count + instance_index;
|
||||
return block_info->delay_info[delay_index].val - 1;
|
||||
return block_info->delay_info.val[delay_index];
|
||||
}
|
||||
|
||||
// GRBM broadcasting mode
|
||||
|
||||
@@ -52,10 +52,8 @@
|
||||
}
|
||||
|
||||
// Getting SPM data using driver API
|
||||
namespace spm_kfd_namespace {
|
||||
hsa_status_t spm_iterate_data(const hsa_ven_amd_aqlprofile_profile_t* profile,
|
||||
hsa_ven_amd_aqlprofile_data_callback_t callback, void* data);
|
||||
}
|
||||
|
||||
// PC sampling callback data
|
||||
struct pcsmp_callback_data_t {
|
||||
@@ -255,6 +253,16 @@ PUBLIC_API hsa_status_t hsa_ven_amd_aqlprofile_start(hsa_ven_amd_aqlprofile_prof
|
||||
pm4_builder::TraceConfig trace_config{};
|
||||
const uint64_t se_number_total = pm4_factory->GetShaderEnginesNumber();
|
||||
|
||||
trace_config.spm_sq_32bit_mode = true;
|
||||
trace_config.spm_has_core1 = (pm4_factory->GetGpuId() == aql_profile::MI100_GPU_ID) ||
|
||||
(pm4_factory->GetGpuId() == aql_profile::MI200_GPU_ID);
|
||||
trace_config.spm_sample_delay_max = pm4_factory->GetSpmSampleDelayMax();
|
||||
trace_config.sampleRate = 1600;
|
||||
|
||||
trace_config.xcc_number = pm4_factory->GetXccNumber();
|
||||
trace_config.se_number = se_number_total / trace_config.xcc_number;
|
||||
trace_config.sa_number = pm4_factory->GetGpuId() >= aql_profile::GFX10_GPU_ID ? 2 : 0;
|
||||
|
||||
if (profile->parameters) {
|
||||
for (const hsa_ven_amd_aqlprofile_parameter_t* p = profile->parameters;
|
||||
p < (profile->parameters + profile->parameter_count); ++p) {
|
||||
@@ -752,7 +760,7 @@ hsa_ven_amd_aqlprofile_iterate_data(const hsa_ven_amd_aqlprofile_profile_t* prof
|
||||
sample_ptr = reinterpret_cast<char*>(sample_ptr) + sample_capacity;
|
||||
}
|
||||
} else {
|
||||
status = spm_kfd_namespace::spm_iterate_data(profile, callback, data);
|
||||
status = spm_iterate_data(profile, callback, data);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
|
||||
@@ -52,6 +52,8 @@ class Mi100Factory : public Gfx9Factory {
|
||||
public:
|
||||
explicit Mi100Factory(const AgentInfo* agent_info);
|
||||
|
||||
virtual uint32_t GetSpmSampleDelayMax() { return 0x34; }
|
||||
|
||||
protected:
|
||||
static const GpuBlockInfo* block_table_[AQLPROFILE_BLOCKS_NUMBER];
|
||||
};
|
||||
|
||||
@@ -152,6 +152,9 @@ class Pm4Factory {
|
||||
// Return number of XCC on the GPU
|
||||
uint32_t GetXccNumber() const { return agent_info_->xcc_num; }
|
||||
|
||||
// SPM specific
|
||||
virtual uint32_t GetSpmSampleDelayMax() { return 0; }
|
||||
|
||||
const GpuBlockInfo* GetBlockInfo(const aqlprofile_pmc_event_t* event) const {
|
||||
const GpuBlockInfo* info = block_map_.Get(event->block_name);
|
||||
if (info == NULL) throw std::runtime_error("Bad Block");
|
||||
|
||||
@@ -20,220 +20,10 @@
|
||||
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
// THE SOFTWARE.
|
||||
|
||||
#include <dirent.h>
|
||||
#include "hsa/hsa_ext_amd.h"
|
||||
#include <pthread.h>
|
||||
#include <sys/types.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include <atomic>
|
||||
#include <iostream>
|
||||
#include <mutex>
|
||||
#include <string>
|
||||
#include <thread>
|
||||
|
||||
#include "core/aql_profile.hpp"
|
||||
#include "core/logger.h"
|
||||
#include "core/pm4_factory.h"
|
||||
|
||||
#define PTHREAD_CALL(call) \
|
||||
do { \
|
||||
int err = call; \
|
||||
if (err != 0) { \
|
||||
errno = err; \
|
||||
perror(#call); \
|
||||
abort(); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
namespace spm_kfd_namespace {
|
||||
|
||||
int get_gpu_node_id(uint32_t gpu_ind) {
|
||||
int gpu_node = -1;
|
||||
uint32_t index = 0;
|
||||
|
||||
// find a valid gpu node from /sys/class/kfd/kfd/topology/nodes
|
||||
std::string path = "/sys/class/kfd/kfd/topology/nodes";
|
||||
DIR* dir;
|
||||
struct dirent* ent;
|
||||
|
||||
if ((dir = opendir(path.c_str())) != NULL) {
|
||||
while ((ent = readdir(dir)) != NULL) {
|
||||
std::string dir = ent->d_name;
|
||||
|
||||
if (dir.find_first_not_of("0123456789") == std::string::npos) {
|
||||
std::string file = path + "/" + ent->d_name + "/gpu_id";
|
||||
std::ifstream infile(file);
|
||||
int id;
|
||||
|
||||
infile >> id;
|
||||
if ((id != 0) && (index == gpu_ind)) {
|
||||
++index;
|
||||
gpu_node = atoi(ent->d_name);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
closedir(dir);
|
||||
}
|
||||
|
||||
if (gpu_node == -1) {
|
||||
printf("get_gpu_node_id`error: GPU[%d] not found\n", gpu_ind);
|
||||
fflush(stdout);
|
||||
abort();
|
||||
}
|
||||
|
||||
return gpu_node;
|
||||
}
|
||||
|
||||
int get_gpu_node_id(hsa_agent_t agent) {
|
||||
const uint32_t gpu_ind = HsaRsrcFactory::Instance().GetAgentInfo(agent)->dev_index;
|
||||
return get_gpu_node_id(gpu_ind);
|
||||
}
|
||||
|
||||
struct state_t {
|
||||
bool thread_stop;
|
||||
int node_id;
|
||||
uint32_t buf_size;
|
||||
uint32_t timeout;
|
||||
uint32_t data_size;
|
||||
void* kfd_buf;
|
||||
void* prod_buf;
|
||||
void* cons_buf;
|
||||
bool data_loss;
|
||||
bool ready;
|
||||
pthread_mutex_t work_mutex;
|
||||
pthread_cond_t work_cond;
|
||||
hsa_agent_t agent;
|
||||
};
|
||||
|
||||
void producer_fun(state_t* state) {
|
||||
uint32_t timeout = 0;
|
||||
hsa_status_t status = HSA_STATUS_SUCCESS;
|
||||
// hsa_amd_spm_set_dest_buffer(state->agent, state->buf_size, &timeout, &(state->data_size),
|
||||
// state->kfd_buf, &(state->data_loss));
|
||||
if (status != HSA_STATUS_SUCCESS) {
|
||||
printf("hsa SPM Set DestBuffer init error\n");
|
||||
fflush(stdout);
|
||||
abort();
|
||||
}
|
||||
|
||||
do {
|
||||
timeout = state->timeout;
|
||||
status = HSA_STATUS_SUCCESS;
|
||||
// hsa_amd_spm_set_dest_buffer(state->agent, state->buf_size, &timeout, &(state->data_size),
|
||||
// state->prod_buf, &(state->data_loss));
|
||||
if (status != HSA_STATUS_SUCCESS) {
|
||||
printf("hsa SPM Set DestBuffer error\n");
|
||||
fflush(stdout);
|
||||
abort();
|
||||
}
|
||||
|
||||
PTHREAD_CALL(pthread_mutex_lock(&(state->work_mutex)));
|
||||
void* tmp = state->prod_buf;
|
||||
state->prod_buf = state->cons_buf;
|
||||
state->cons_buf = state->kfd_buf;
|
||||
state->kfd_buf = tmp;
|
||||
state->ready = true;
|
||||
PTHREAD_CALL(pthread_cond_signal(&(state->work_cond)));
|
||||
PTHREAD_CALL(pthread_mutex_unlock(&(state->work_mutex)));
|
||||
} while (!state->thread_stop);
|
||||
|
||||
status = HSA_STATUS_SUCCESS;
|
||||
// hsa_amd_spm_set_dest_buffer(state->agent, 0, &timeout, &(state->data_size), NULL,
|
||||
// &(state->data_loss));
|
||||
if (status != HSA_STATUS_SUCCESS) {
|
||||
printf("hsa SPM Set DestBuffer stop error\n");
|
||||
fflush(stdout);
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
void consumer_fun(state_t* state, hsa_ven_amd_aqlprofile_data_callback_t callback, void* data) {
|
||||
const uint32_t sample_id = 0;
|
||||
PTHREAD_CALL(pthread_mutex_lock(&(state->work_mutex)));
|
||||
do {
|
||||
while (state->ready == false) {
|
||||
PTHREAD_CALL(pthread_cond_wait(&(state->work_cond), &(state->work_mutex)));
|
||||
}
|
||||
state->ready = false;
|
||||
|
||||
hsa_ven_amd_aqlprofile_info_data_t sample_info;
|
||||
sample_info.sample_id = sample_id;
|
||||
sample_info.trace_data.ptr = state->cons_buf;
|
||||
sample_info.trace_data.size = state->data_size;
|
||||
|
||||
hsa_status_t status = callback(HSA_VEN_AMD_AQLPROFILE_INFO_TRACE_DATA, &sample_info, data);
|
||||
if (status == HSA_STATUS_INFO_BREAK) {
|
||||
status = HSA_STATUS_SUCCESS;
|
||||
state->thread_stop = true;
|
||||
break;
|
||||
} else if (status != HSA_STATUS_SUCCESS) {
|
||||
printf("SPM consumer callback failed\n");
|
||||
abort();
|
||||
}
|
||||
} while (1);
|
||||
PTHREAD_CALL(pthread_mutex_unlock(&(state->work_mutex)));
|
||||
}
|
||||
|
||||
void mananger_fun(const hsa_ven_amd_aqlprofile_profile_t* profile,
|
||||
hsa_ven_amd_aqlprofile_data_callback_t callback, void* data) {
|
||||
state_t obj{};
|
||||
const int gpu_node_id = get_gpu_node_id(profile->agent);
|
||||
char* buf_ptr = (char*)(profile->output_buffer.ptr);
|
||||
// SPM data buffer size 256 byte aligned
|
||||
const uint32_t buf_size = (profile->output_buffer.size / 3) & ~(uint32_t(256) - 1);
|
||||
|
||||
obj.timeout = 1000000; // 1sec
|
||||
obj.node_id = gpu_node_id;
|
||||
obj.buf_size = buf_size;
|
||||
obj.kfd_buf = buf_ptr;
|
||||
obj.prod_buf = buf_ptr + buf_size;
|
||||
obj.cons_buf = buf_ptr + 2 * buf_size;
|
||||
obj.agent = profile->agent;
|
||||
|
||||
PTHREAD_CALL(pthread_mutex_init(&(obj.work_mutex), NULL));
|
||||
PTHREAD_CALL(pthread_cond_init(&(obj.work_cond), NULL));
|
||||
|
||||
hsa_status_t status = HSA_STATUS_SUCCESS; // hsa_amd_spm_acquire(profile->agent);
|
||||
if (status != HSA_STATUS_SUCCESS) {
|
||||
printf("hsa SPM Acquire error\n");
|
||||
fflush(stdout);
|
||||
abort();
|
||||
}
|
||||
|
||||
// spm threads
|
||||
std::thread producer(producer_fun, &obj);
|
||||
std::thread consumer(consumer_fun, &obj, callback, data);
|
||||
|
||||
producer.join();
|
||||
consumer.join();
|
||||
|
||||
status = HSA_STATUS_SUCCESS; // hsa_amd_spm_release(profile->agent);
|
||||
if (status != HSA_STATUS_SUCCESS) {
|
||||
printf("hsa SPM Release error\n");
|
||||
fflush(stdout);
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
typedef std::mutex spm_mutex_t;
|
||||
spm_mutex_t spm_mutex;
|
||||
|
||||
// Getting SPM data using driver API
|
||||
hsa_status_t spm_iterate_data(const hsa_ven_amd_aqlprofile_profile_t* profile,
|
||||
hsa_ven_amd_aqlprofile_data_callback_t callback, void* data) {
|
||||
std::lock_guard<spm_mutex_t> lck(spm_mutex);
|
||||
static std::thread* t = NULL;
|
||||
|
||||
if (t == NULL) {
|
||||
// spm manager thread
|
||||
t = new std::thread(mananger_fun, profile, callback, data);
|
||||
} else {
|
||||
t->join();
|
||||
}
|
||||
|
||||
return HSA_STATUS_SUCCESS;
|
||||
}
|
||||
|
||||
} // namespace spm_kfd_namespace
|
||||
|
||||
@@ -80,13 +80,17 @@ struct CounterRegInfo {
|
||||
Register register_addr_lo;
|
||||
// counter register address high
|
||||
Register register_addr_hi;
|
||||
// counter select1 register address (for SPM)
|
||||
Register select1_addr;
|
||||
};
|
||||
|
||||
struct BlockDelayInfo {
|
||||
Register reg;
|
||||
uint32_t val;
|
||||
const uint32_t* val; // Layout: val[SA][SE][instance]
|
||||
};
|
||||
|
||||
#define BLOCK_DELAY_NONE { REG_32B_NULL, nullptr }
|
||||
|
||||
struct counter_des_t;
|
||||
|
||||
// GPU Block info definition
|
||||
@@ -108,7 +112,7 @@ struct GpuBlockInfo {
|
||||
// Block attributes mask
|
||||
uint32_t attr;
|
||||
// Block delay info
|
||||
const BlockDelayInfo* delay_info;
|
||||
BlockDelayInfo delay_info;
|
||||
// SPM block id
|
||||
uint32_t spm_block_id;
|
||||
};
|
||||
|
||||
@@ -330,7 +330,7 @@ class Gfx10CmdBuilder : public CmdBuilder {
|
||||
}
|
||||
|
||||
void BuildNopPacket(CmdBuffer* cmdbuf, uint32_t num_dwords) {
|
||||
uint32_t header = MakePacket3Header(PACKET3_NOP, num_dwords);
|
||||
uint32_t header = MakePacket3Header(PACKET3_NOP, num_dwords * sizeof(uint32_t));
|
||||
APPEND_COMMAND_WRAPPER(cmdbuf, header);
|
||||
if (num_dwords > 1) {
|
||||
std::vector<uint32_t> data_block((num_dwords - 1), 0);
|
||||
|
||||
@@ -304,7 +304,7 @@ class Gfx11CmdBuilder : public CmdBuilder {
|
||||
}
|
||||
|
||||
void BuildNopPacket(CmdBuffer* cmdbuf, uint32_t num_dwords) {
|
||||
uint32_t header = MakePacket3Header(PACKET3_NOP, num_dwords);
|
||||
uint32_t header = MakePacket3Header(PACKET3_NOP, num_dwords * sizeof(uint32_t));
|
||||
APPEND_COMMAND_WRAPPER(cmdbuf, header);
|
||||
if (num_dwords > 1) {
|
||||
std::vector<uint32_t> data_block((num_dwords - 1), 0);
|
||||
|
||||
@@ -325,7 +325,7 @@ class Gfx9CmdBuilder : public CmdBuilder {
|
||||
}
|
||||
|
||||
void BuildNopPacket(CmdBuffer* cmdbuf, uint32_t num_dwords) {
|
||||
uint32_t header = MakePacket3Header(PACKET3_NOP, num_dwords);
|
||||
uint32_t header = MakePacket3Header(PACKET3_NOP, num_dwords * sizeof(uint32_t));
|
||||
APPEND_COMMAND_WRAPPER(cmdbuf, header);
|
||||
if (num_dwords > 1) {
|
||||
std::vector<uint32_t> data_block((num_dwords - 1), 0);
|
||||
|
||||
@@ -104,19 +104,6 @@ class GpuSpmBuilder : public SpmBuilder, protected Primitives {
|
||||
// 3. Program the RLC_PERFMON_SEGMENT_SIZE register.
|
||||
builder.BuildWriteUConfigRegPacket(cmd_buffer, Primitives::RLC_SPM_PERFMON_CNTL__ADDR,
|
||||
Primitives::rlc_spm_perfmon_cntl_value(sampling_rate));
|
||||
if (!config->spm_kfd_mode) {
|
||||
builder.BuildWriteUConfigRegPacket(cmd_buffer, Primitives::RLC_SPM_PERFMON_RING_BASE_LO__ADDR,
|
||||
buffer_ptr);
|
||||
builder.BuildWriteUConfigRegPacket(cmd_buffer, Primitives::RLC_SPM_PERFMON_RING_BASE_HI__ADDR,
|
||||
buffer_ptr >> 32);
|
||||
builder.BuildWriteUConfigRegPacket(cmd_buffer, Primitives::RLC_SPM_PERFMON_RING_SIZE__ADDR,
|
||||
buffer_size);
|
||||
}
|
||||
|
||||
// Setting VMID
|
||||
if (!config->spm_kfd_mode)
|
||||
builder.BuildWriteUConfigRegPacket(cmd_buffer, Primitives::RLC_SPM_MC_CNTL__ADDR,
|
||||
Primitives::rlc_spm_mc_cntl_value());
|
||||
|
||||
// Iterate through the list of blocks to create PM4 packets to read counter values
|
||||
// Below pair.first is the block id of a counter event and pair.second is the index into
|
||||
@@ -272,17 +259,16 @@ class GpuSpmBuilder : public SpmBuilder, protected Primitives {
|
||||
for (size_t j = 0; j < block_info->instance_count; ++j) {
|
||||
builder.BuildWriteUConfigRegPacket(cmd_buffer, Primitives::GRBM_GFX_INDEX_ADDR,
|
||||
Primitives::grbm_inst_se_sh_index_value(j, 0, 0));
|
||||
builder.BuildWriteUConfigRegPacket(cmd_buffer, block_info->delay_info[j].reg,
|
||||
builder.BuildWriteUConfigRegPacket(cmd_buffer, block_info->delay_info.reg,
|
||||
Primitives::get_spm_global_delay(counter_des, j));
|
||||
}
|
||||
} else {
|
||||
for (size_t i = 0; i < config->spm_se_number_total; ++i) {
|
||||
for (size_t i = 0; i < config->se_number; ++i) {
|
||||
for (size_t j = 0; j < block_info->instance_count; ++j) {
|
||||
int delay_index = i * block_info->instance_count + j;
|
||||
builder.BuildWriteUConfigRegPacket(cmd_buffer, Primitives::GRBM_GFX_INDEX_ADDR,
|
||||
Primitives::grbm_inst_se_index_value(j, i));
|
||||
builder.BuildWriteUConfigRegPacket(cmd_buffer,
|
||||
block_info->delay_info[delay_index].reg,
|
||||
block_info->delay_info.reg,
|
||||
Primitives::get_spm_se_delay(counter_des, i, j));
|
||||
}
|
||||
}
|
||||
@@ -341,7 +327,7 @@ class GpuSpmBuilder : public SpmBuilder, protected Primitives {
|
||||
builder.BuildWriteUConfigRegPacket(
|
||||
cmd_buffer, Primitives::RLC_SPM_PERFMON_SEGMENT_SIZE__ADDR,
|
||||
Primitives::rlc_spm_perfmon_segment_size_value(global_count, se_count));
|
||||
if (config->mi100) {
|
||||
if (config->spm_has_core1) {
|
||||
builder.BuildWriteUConfigRegPacket(
|
||||
cmd_buffer, Primitives::RLC_SPM_PERFMON_SEGMENT_SIZE_CORE1__ADDR,
|
||||
Primitives::rlc_spm_perfmon_segment_size_core1_value(se_count));
|
||||
|
||||
@@ -42,18 +42,20 @@ struct TraceConfig {
|
||||
uint32_t perfMASK = ~0u;
|
||||
uint32_t perfCTRL = 0;
|
||||
std::vector<std::pair<size_t, size_t>> perfcounters{};
|
||||
// GC configurations used by both TT and SPM
|
||||
uint32_t se_number = 0;
|
||||
uint32_t sa_number = 0;
|
||||
uint32_t xcc_number = 0;
|
||||
// SPM mode
|
||||
bool spm_sq_32bit_mode = true;
|
||||
bool spm_kfd_mode = true;
|
||||
bool mi100 = false;
|
||||
bool spm_has_core1 = false;
|
||||
uint32_t spm_sample_delay_max = 0;
|
||||
|
||||
void* control_buffer_ptr = nullptr;
|
||||
uint32_t control_buffer_size = 0;
|
||||
void* data_buffer_ptr = nullptr;
|
||||
uint32_t data_buffer_size = 0;
|
||||
|
||||
// SE number for tracing
|
||||
uint32_t spm_se_number_total = 0;
|
||||
// concurrent kernels mode
|
||||
uint32_t concurrent = 0;
|
||||
// SE mask for tracing; note -> replicated for all XCCs
|
||||
|
||||
+19
-276
@@ -35,84 +35,12 @@
|
||||
#include "pgen/test_pgen_sqtt.h"
|
||||
#include "simple_convolution/simple_convolution.h"
|
||||
|
||||
const int argv_pmc_size = 32;
|
||||
unsigned argc_pmc = 0;
|
||||
char* argv_arr = NULL;
|
||||
char** argv_pmc = NULL;
|
||||
|
||||
typedef struct {
|
||||
uint32_t size; // size of buffer in bytes
|
||||
uint32_t timeout;
|
||||
uint32_t len; // len of streamed data in spm buffer
|
||||
void* addr; // address of spm buffer
|
||||
bool data_loss; // OUT
|
||||
} spm_buffer_params_t;
|
||||
|
||||
int gpu_node_id = -1;
|
||||
spm_buffer_params_t spm_buffer_params[2];
|
||||
std::atomic<uint32_t> spm_buffer_idx{0}; // current spm buffer in use for spm samples
|
||||
std::atomic<bool> spm_check_data{
|
||||
true}; // request to check spm data in spm_buffer at spm_buffer_idx
|
||||
std::atomic<bool> test_done{false}; // is GPU kernel finished?
|
||||
|
||||
int get_gpu_node_id() {
|
||||
int gpu_node = -1;
|
||||
|
||||
#if 0
|
||||
// find a valid gpu node from /sys/class/kfd/kfd/topology/nodes
|
||||
std::string path = "/sys/class/kfd/kfd/topology/nodes";
|
||||
DIR *dir;
|
||||
struct dirent *ent;
|
||||
|
||||
if ((dir = opendir(path.c_str())) != NULL) {
|
||||
while ((ent = readdir(dir)) != NULL) {
|
||||
std::string dir = ent->d_name;
|
||||
|
||||
if (dir.find_first_not_of("0123456789") == std::string::npos) {
|
||||
std::string file = path + "/" + ent->d_name + "/gpu_id";
|
||||
std::ifstream infile(file);
|
||||
int id;
|
||||
|
||||
infile >> id;
|
||||
if (id != 0) {
|
||||
gpu_node = atoi(ent->d_name);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
closedir(dir);
|
||||
}
|
||||
|
||||
HsaSystemProperties m_SystemProperties;
|
||||
memset(&m_SystemProperties, 0, sizeof(m_SystemProperties));
|
||||
|
||||
HSAKMT_STATUS status = hsaKmtAcquireSystemProperties(&m_SystemProperties);
|
||||
if (status != HSAKMT_STATUS_SUCCESS) {
|
||||
std::cerr << "Error in hsaKmtAcquireSystemProperties" << std::endl;
|
||||
return 1;
|
||||
}
|
||||
|
||||
// tranverse all CPU and GPU nodes and break when a GPU node is found
|
||||
for (unsigned i = 0; i < m_SystemProperties.NumNodes; ++i) {
|
||||
HsaNodeProperties nodeProperties;
|
||||
memset(&nodeProperties, 0, sizeof(HsaNodeProperties));
|
||||
|
||||
status = hsaKmtGetNodeProperties(i, &nodeProperties);
|
||||
if (status != HSAKMT_STATUS_SUCCESS) {
|
||||
std::cerr << "Error in hsaKmtAcquireSystemProperties" << std::endl;
|
||||
break;
|
||||
} else if (nodeProperties.NumFComputeCores) {
|
||||
gpu_node = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
printf("GPU node id(%d)\n", gpu_node);
|
||||
return gpu_node;
|
||||
}
|
||||
|
||||
char** pmc_argv(unsigned argc, const hsa_ven_amd_aqlprofile_event_t* events) {
|
||||
const int argv_pmc_size = 32;
|
||||
static unsigned argc_pmc = 0;
|
||||
static char* argv_arr = NULL;
|
||||
static char** argv_pmc = NULL;
|
||||
|
||||
if (argc > argc_pmc) {
|
||||
argc_pmc = argc;
|
||||
argv_arr = reinterpret_cast<char*>(realloc(argv_arr, argc_pmc * argv_pmc_size));
|
||||
@@ -129,52 +57,6 @@ char** pmc_argv(unsigned argc, const hsa_ven_amd_aqlprofile_event_t* events) {
|
||||
return argv_pmc;
|
||||
}
|
||||
|
||||
typedef char** pf_pmc_argv(unsigned argc, const hsa_ven_amd_aqlprofile_event_t* events);
|
||||
|
||||
void thread_kernel(bool* ret_val, pf_pmc_argv pmc_argv, int events_count,
|
||||
const hsa_ven_amd_aqlprofile_event_t* events) {
|
||||
*ret_val =
|
||||
RunKernel<simple_convolution, TestPGenSpm>(events_count, pmc_argv(events_count, events));
|
||||
test_done = true;
|
||||
}
|
||||
|
||||
void thread_spm_buffer_setup() {
|
||||
#if ENABLE_SPM
|
||||
while (!test_done) {
|
||||
auto idx = (spm_buffer_idx.load() + 1) & 0x1;
|
||||
std::cout << "thread_spm_buffer_setup: " << idx << std::endl;
|
||||
hsa_status_t status =
|
||||
hsa_amd_spm_set_dest_buffer(gpu_node_id, spm_buffer_params[idx].size,
|
||||
&spm_buffer_params[idx].timeout, &spm_buffer_params[idx].len,
|
||||
spm_buffer_params[idx].addr, &spm_buffer_params[idx].data_loss);
|
||||
if (status != HSA_STATUS_SUCCESS) {
|
||||
std::cerr << "Error in initial spm setup of buffer 0" << std::endl;
|
||||
return;
|
||||
}
|
||||
// inform data saving thread there is spm data to save
|
||||
if (spm_buffer_params[idx].len != 0) spm_check_data = true;
|
||||
}
|
||||
#endif
|
||||
|
||||
std::cout << "Exiting thread_spm_buffer_setup ..." << std::endl;
|
||||
}
|
||||
|
||||
void thread_spm_data_save(FILE* file) {
|
||||
while (!test_done) {
|
||||
if (spm_check_data) {
|
||||
auto buffer_idx = spm_buffer_idx.load();
|
||||
auto idx = buffer_idx & 0x1;
|
||||
std::cout << "thread_spm_data_save " << idx << " with " << spm_buffer_params[idx].len
|
||||
<< " bytes" << std::endl;
|
||||
fwrite(spm_buffer_params[idx].addr, 1, spm_buffer_params[idx].len, file);
|
||||
|
||||
spm_buffer_idx = buffer_idx + 1;
|
||||
spm_check_data = false;
|
||||
}
|
||||
}
|
||||
std::cout << "Exiting thread_spm_data_save ..." << std::endl;
|
||||
}
|
||||
|
||||
int main(int argc, char* argv[]) {
|
||||
bool ret_val = false;
|
||||
const bool pmc_enable = (getenv("AQLPROFILE_PMC") != NULL);
|
||||
@@ -185,8 +67,6 @@ int main(int argc, char* argv[]) {
|
||||
const bool scan_enable = (getenv("AQLPROFILE_SCAN") != NULL);
|
||||
const bool trace_enable = (getenv("AQLPROFILE_TRACE") != NULL);
|
||||
const bool spm_enable = (getenv("AQLPROFILE_SPM") != NULL);
|
||||
[[maybe_unused]] const bool spm_kfd_mode = (getenv("AQLPROFILE_SPM_KFD_MODE") != NULL);
|
||||
// int gpu_node_id = -1;
|
||||
int scan_step = 1;
|
||||
const char* step_env = getenv("AQLPROFILE_SCAN_STEP");
|
||||
if (step_env != NULL) {
|
||||
@@ -199,6 +79,10 @@ int main(int argc, char* argv[]) {
|
||||
scan_step = step;
|
||||
}
|
||||
|
||||
const char* spm_loop_env = getenv("AQLPROFILE_SPM_LOOPS");
|
||||
int spm_loops = spm_loop_env ? atoi(spm_loop_env) : 1;
|
||||
if (!spm_loops) spm_loops = 1;
|
||||
|
||||
if (!trace_enable) {
|
||||
std::clog.rdbuf(NULL);
|
||||
}
|
||||
@@ -206,43 +90,6 @@ int main(int argc, char* argv[]) {
|
||||
std::cerr.rdbuf(NULL);
|
||||
}
|
||||
|
||||
//{
|
||||
// hsa_status_t status = hsa_init();
|
||||
// CHECK_STATUS("Error in hsa_init", status);
|
||||
//}
|
||||
|
||||
if (spm_enable) {
|
||||
#if ENABLE_SPM
|
||||
{
|
||||
hsa_status_t status = hsa_init();
|
||||
CHECK_STATUS("Error in hsa_init", status);
|
||||
}
|
||||
gpu_node_id = get_gpu_node_id();
|
||||
if (gpu_node_id == -1) {
|
||||
std::cerr << "Error in get_gpu_node_id()" << std::endl;
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (spm_kfd_mode) {
|
||||
hsa_status_t status = hsa_amd_spm_acquire(gpu_node_id);
|
||||
if (status != HSA_STATUS_SUCCESS) {
|
||||
std::cerr << "Error in acquiring SPM for NodeId " << gpu_node_id << std::endl;
|
||||
return 1;
|
||||
}
|
||||
} else {
|
||||
#if SPM_DEBUG_TRAP
|
||||
HSAKMT_STATUS status = hsaKmtEnableDebugTrap(gpu_node_id, INVALID_QUEUEID);
|
||||
#else
|
||||
HSAKMT_STATUS status = HSAKMT_STATUS_ERROR;
|
||||
#endif
|
||||
if (status != HSAKMT_STATUS_SUCCESS) {
|
||||
std::cerr << "Error in enabling debug trap for NodeId " << gpu_node_id << std::endl;
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
TestHsa::HsaInstantiate();
|
||||
const hsa_ven_amd_aqlprofile_event_t* events_arr;
|
||||
|
||||
@@ -449,126 +296,22 @@ int main(int argc, char* argv[]) {
|
||||
} else if (pcsmp_enable && TestHsa::HsaAgentName().substr(0, 4) != "gfx1") {
|
||||
ret_val = RunKernel<simple_convolution, TestPGenPcsmp>(argc, argv);
|
||||
} else if (spm_enable) {
|
||||
#ifdef ENABLE_SPM
|
||||
int events_count = 0;
|
||||
const hsa_ven_amd_aqlprofile_event_t events_spm[] = {
|
||||
// {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQ, 0, 0 /*NONE*/},
|
||||
// {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQ, 0, 2 /*CYCLES*/},
|
||||
// {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQ, 0, 3 /*BUSY_CYCLES*/},
|
||||
{HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQ, 0, 2 /*CYCLES*/},
|
||||
{HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQ, 0, 4 /*WAVES*/},
|
||||
// {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQ, 0, 14 /*ITEMS*/},
|
||||
// {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQ, 0, 47 /*WAVE_READY*/},
|
||||
// {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SPI, 0, 47 /*CSN_WINDOW_VALID*/},
|
||||
// {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TA, 0, 1 /*SH_FIFO_BUSY*/},
|
||||
// {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TD, 0, 1 /*TD_BUSY*/},
|
||||
// {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCC, 2, 3 /*REQ*/},
|
||||
// {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCC, 2, 22 /*WRITEBACK*/},
|
||||
// {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCC, 2, 1 /*CYCLE*/},
|
||||
// {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_TCP, 1, 2 /*CORE_REG_SCLK_VLD*/},
|
||||
// {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPC, 0, 0 /*ALWAYS_COUNT*/},
|
||||
// {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPF, 0, 0 /*ALWAYS_COUNT*/},
|
||||
// {HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_GDS, 0, 0 /*DS_ADDR_CONFL*/},
|
||||
{HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SQ, 0, 14 /*ITEMS*/},
|
||||
{HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SPI, 0, 48 /*CSN_BUSY*/},
|
||||
{HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SPI, 0, 49 /*CSN_NUM_THREADGROUPS*/},
|
||||
{HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SPI, 0, 51 /*CSN_EVENT_WAVE*/},
|
||||
{HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_SPI, 0, 47 /*CSN_WINDOW_VALID*/},
|
||||
{HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPC, 0, 0 /*ALWAYS_COUNT*/},
|
||||
{HSA_VEN_AMD_AQLPROFILE_BLOCK_NAME_CPC, 0, 8 /*SEL_ME1_STALL_WAIT_ON_RCIU_READ*/},
|
||||
};
|
||||
events_count = sizeof(events_spm) / sizeof(hsa_ven_amd_aqlprofile_event_t);
|
||||
|
||||
if (spm_kfd_mode) {
|
||||
// open a binary file for spm samples
|
||||
const std::string spm_sample_file = "example.txt";
|
||||
FILE* file = fopen(spm_sample_file.c_str(), "wb");
|
||||
if (file == NULL) {
|
||||
std::cerr << "Error opening file " << spm_sample_file << " for spm sampling!" << std::endl;
|
||||
return 1;
|
||||
}
|
||||
|
||||
// set up 2 spm sample data buffers
|
||||
const uint32_t timeout = 10000;
|
||||
const uint32_t spm_buffer_size = 0x2000000;
|
||||
spm_buffer_params[0].size = spm_buffer_size;
|
||||
spm_buffer_params[0].timeout = timeout;
|
||||
spm_buffer_params[0].len = 0;
|
||||
spm_buffer_params[0].addr = malloc(spm_buffer_size);
|
||||
if (spm_buffer_params[0].addr == NULL) {
|
||||
std::cerr << "Malloc(size) for spm buffer 0 Failed." << std::endl;
|
||||
return 1;
|
||||
}
|
||||
spm_buffer_params[0].data_loss = false;
|
||||
|
||||
spm_buffer_params[1].size = spm_buffer_size;
|
||||
spm_buffer_params[1].timeout = timeout;
|
||||
spm_buffer_params[1].len = 0;
|
||||
spm_buffer_params[1].addr = malloc(spm_buffer_size);
|
||||
if (spm_buffer_params[1].addr == NULL) {
|
||||
std::cerr << "Malloc(size) for spm buffer 1 Failed." << std::endl;
|
||||
return 1;
|
||||
}
|
||||
spm_buffer_params[1].data_loss = false;
|
||||
|
||||
// non-blocking set up the first spm buffer for use before GPU kernel started
|
||||
std::cout << "spm_buffer_setup 0 ..." << std::endl;
|
||||
hsa_status_t status = hsa_amd_spm_set_dest_buffer(
|
||||
gpu_node_id, spm_buffer_params[0].size, &spm_buffer_params[0].timeout,
|
||||
&spm_buffer_params[0].len, spm_buffer_params[0].addr, &spm_buffer_params[0].data_loss);
|
||||
if (status != HSA_STATUS_SUCCESS) {
|
||||
std::cerr << "Error in initial spm setup of buffer 0" << std::endl;
|
||||
return 1;
|
||||
}
|
||||
|
||||
// spm threads
|
||||
std::thread k_thread(thread_kernel, &ret_val, pmc_argv, events_count, events_spm);
|
||||
std::thread buffer_setup(thread_spm_buffer_setup);
|
||||
std::thread data_save(thread_spm_data_save, file);
|
||||
|
||||
k_thread.join();
|
||||
buffer_setup.join();
|
||||
data_save.join();
|
||||
|
||||
// my_anaylyze(spm_buffer_params[0].addr, spm_buffer_params[0].size,
|
||||
// spm_buffer_params[0].len); my_anaylyze(spm_buffer_params[1].addr,
|
||||
// spm_buffer_params[1].size, spm_buffer_params[1].len);
|
||||
|
||||
// free allocated spm buffers
|
||||
free(spm_buffer_params[0].addr);
|
||||
free(spm_buffer_params[1].addr);
|
||||
|
||||
std::cout << "data in buff0: " << spm_buffer_params[0].len << " bytes" << std::endl;
|
||||
std::cout << "data in buff1: " << spm_buffer_params[1].len << " bytes" << std::endl;
|
||||
|
||||
status = hsa_amd_spm_release(gpu_node_id);
|
||||
if (status != HSA_STATUS_SUCCESS) {
|
||||
std::cerr << "Error in releasing SPM for NodeId " << gpu_node_id << std::endl;
|
||||
return 1;
|
||||
}
|
||||
|
||||
// close spm sample binary file
|
||||
fclose(file);
|
||||
} else {
|
||||
ret_val = RunKernel<simple_convolution, TestPGenSpm>(events_count,
|
||||
pmc_argv(events_count, events_spm));
|
||||
#if SPM_DEBUG_TRAP
|
||||
HSAKMT_STATUS status = hsaKmtDisableDebugTrap(gpu_node_id);
|
||||
#else
|
||||
hsa_status_t status = HSA_STATUS_ERROR;
|
||||
#endif
|
||||
if (status != HSA_STATUS_SUCCESS) {
|
||||
std::cerr << "Error in disabling debug trap for NodeId " << gpu_node_id << std::endl;
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
// SPM data analysis: need to change command dependent on binary vs text sample files
|
||||
// The 'da_16b.py' script is checking the first SPM counter data to match expected value
|
||||
// provided by the option '-e'
|
||||
std::string command = "python3 da_16b.py -e 16 spm_dump_0.txt";
|
||||
|
||||
int command_status = system(command.c_str());
|
||||
|
||||
if (command_status == -1)
|
||||
std::cerr << "Cannot run \"" << command << "\"" << std::endl;
|
||||
else if (command_status == 0)
|
||||
std::cout << "SPM test passed!" << std::endl;
|
||||
else
|
||||
std::cerr << "SPM test failed!" << std::endl;
|
||||
#endif
|
||||
ret_val = RunKernel<simple_convolution, TestPGenSpm>(
|
||||
events_count, pmc_argv(events_count, events_spm), spm_loops);
|
||||
} else {
|
||||
ret_val = RunKernel<simple_convolution, TestAql>(argc, argv);
|
||||
}
|
||||
|
||||
@@ -33,14 +33,30 @@
|
||||
#include "pgen/test_pgen.h"
|
||||
#include "util/test_assert.h"
|
||||
|
||||
typedef std::vector<hsa_ven_amd_aqlprofile_info_data_t> callback_data_t;
|
||||
// C++11's solution for std::format()
|
||||
template <typename... Args>
|
||||
std::string string_format(const std::string& format, Args... args) {
|
||||
int size_s = std::snprintf(nullptr, 0, format.c_str(), args...) + 1; // Extra space for '\0'
|
||||
if (size_s <= 0) {
|
||||
throw std::runtime_error("Error during formatting.");
|
||||
}
|
||||
auto size = static_cast<size_t>(size_s);
|
||||
std::unique_ptr<char[]> buf(new char[size]);
|
||||
std::snprintf(buf.get(), size, format.c_str(), args...);
|
||||
return std::string(buf.get(), buf.get() + size - 1); // We don't want the '\0' inside
|
||||
}
|
||||
|
||||
hsa_status_t TestPGenSpmCallback(hsa_ven_amd_aqlprofile_info_type_t info_type,
|
||||
hsa_ven_amd_aqlprofile_info_data_t* info_data,
|
||||
void* callback_data) {
|
||||
hsa_status_t status = HSA_STATUS_SUCCESS;
|
||||
reinterpret_cast<callback_data_t*>(callback_data)->push_back(*info_data);
|
||||
return status;
|
||||
std::clog << string_format("SPM Callback: Data = %p Size = %zu\n", info_data->trace_data.ptr,
|
||||
info_data->trace_data.size);
|
||||
if (callback_data) {
|
||||
auto streams_ = (std::ofstream*)callback_data;
|
||||
streams_[info_data->sample_id].write((const char*)info_data->trace_data.ptr,
|
||||
info_data->trace_data.size);
|
||||
} return status;
|
||||
}
|
||||
|
||||
// Class implements SPM profiling
|
||||
@@ -121,8 +137,9 @@ class TestPGenSpm : public TestPGen {
|
||||
&profile_, HSA_VEN_AMD_AQLPROFILE_INFO_COMMAND_BUFFER_SIZE, &command_buffer_size);
|
||||
TEST_ASSERT(status == HSA_STATUS_SUCCESS);
|
||||
|
||||
num_xcc_ = GetAgentInfo()->xcc_num ? GetAgentInfo()->xcc_num : 1;
|
||||
output_buffer_alignment = buffer_alignment_;
|
||||
output_buffer_size = buffer_size_;
|
||||
output_buffer_size = buffer_size_ * num_xcc_;
|
||||
|
||||
// Application is allocating the command buffer
|
||||
// AllocateSystem(command_buffer_alignment, command_buffer_size,
|
||||
@@ -153,6 +170,13 @@ class TestPGenSpm : public TestPGen {
|
||||
status = api_->hsa_ven_amd_aqlprofile_stop(&profile_, PostPacket());
|
||||
TEST_ASSERT(status == HSA_STATUS_SUCCESS);
|
||||
|
||||
for (int i = 0; i < num_xcc_; i++) {
|
||||
std::ostringstream oss;
|
||||
oss << "spm_buffer_" << i << ".bin";
|
||||
streams_[i].open(oss.str(), std::ofstream::binary | std::ofstream::out);
|
||||
}
|
||||
api_->hsa_ven_amd_aqlprofile_iterate_data(&profile_, TestPGenSpmCallback, streams_);
|
||||
|
||||
return (status == HSA_STATUS_SUCCESS);
|
||||
}
|
||||
|
||||
@@ -161,46 +185,26 @@ class TestPGenSpm : public TestPGen {
|
||||
|
||||
bool DumpData() {
|
||||
std::clog << "TestPGenSpm::DumpData :" << std::endl;
|
||||
|
||||
callback_data_t data;
|
||||
api_->hsa_ven_amd_aqlprofile_iterate_data(&profile_, TestPGenSpmCallback, &data);
|
||||
for (callback_data_t::iterator it = data.begin(); it != data.end(); ++it) {
|
||||
std::cout << "sample(" << std::dec << it->sample_id << ") size(" << std::dec
|
||||
<< it->trace_data.size << ") ptr(" << std::hex << it->trace_data.ptr << ")"
|
||||
<< std::endl;
|
||||
|
||||
void* sys_buf = GetRsrcFactory()->AllocateSysMemory(GetAgentInfo(), it->trace_data.size);
|
||||
TEST_ASSERT(sys_buf != NULL);
|
||||
if (sys_buf == NULL) return false;
|
||||
|
||||
hsa_status_t status = hsa_memory_copy(sys_buf, it->trace_data.ptr, it->trace_data.size);
|
||||
TEST_ASSERT(status == HSA_STATUS_SUCCESS);
|
||||
if (status != HSA_STATUS_SUCCESS) return false;
|
||||
|
||||
std::string file_name;
|
||||
file_name.append("spm_dump_");
|
||||
file_name.append(std::to_string(it->sample_id));
|
||||
file_name.append(".txt");
|
||||
std::ofstream out_file;
|
||||
out_file.open(file_name);
|
||||
|
||||
// Write the buffer in terms of shorts (16 bits)
|
||||
uint16_t* trace_data = reinterpret_cast<uint16_t*>(sys_buf);
|
||||
for (unsigned i = 0; i < (it->trace_data.size / sizeof(uint16_t)); ++i) {
|
||||
out_file << std::setw(4) << std::setfill('0') << std::hex << trace_data[i] << "\n";
|
||||
}
|
||||
|
||||
out_file.close();
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool Cleanup() {
|
||||
api_->hsa_ven_amd_aqlprofile_iterate_data(&profile_, TestPGenSpmCallback, NULL);
|
||||
for (int i; i < num_xcc_; i++) {
|
||||
if (streams_[i].is_open()) {
|
||||
streams_[i].close();
|
||||
}
|
||||
}
|
||||
return TestAql::Cleanup();
|
||||
}
|
||||
|
||||
static const uint32_t buffer_alignment_ = 0x1000; // 4K
|
||||
static const uint32_t buffer_size_ = 0x2000000; // 32M
|
||||
static const uint32_t spm_sample_rate_ = 10000; // default SPM sample rate
|
||||
|
||||
hsa_ven_amd_aqlprofile_profile_t profile_;
|
||||
std::ofstream streams_[8];
|
||||
uint32_t num_xcc_;
|
||||
};
|
||||
|
||||
#endif // TEST_PGEN_TEST_PGEN_SPM_H_
|
||||
|
||||
Reference in New Issue
Block a user