P4 to Git Change 1363842 by asalmanp@asalmanp-opencl-stg on 2017/01/19 11:35:19

SWDEV-107075 - [OCL][VG10] Conformance RQ Mipmaps tests are failing. Adding a temporary workaround for Vega10 to disable sDMA transfers for MemToImage and ImageToMem for 1Darray image format for now and use Kernles instead until the failures can be root-caused and fixed.
	GPU_DISABLE_SDMA_IMG_MEM_IMG environment variable was also added to quickly enable back the sDMA for testing and continuing the current failure investigation.

	ReviewBoardURL = http://ocltc.amd.com/reviews/r/12194/

Affected files ...

... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palresource.cpp#22 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palsettings.cpp#14 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palsettings.hpp#8 edit
... //depot/stg/opencl/drivers/opencl/runtime/utils/flags.hpp#265 edit


[ROCm/clr commit: 7403de545e]

projects/clr/rocclr/runtime/device/pal/palresource.cpp

@@ -1258,18 +1258,22 @@ Resource::partialMemCopyTo(
     calSize[2] = size[2];
 
     uint64_t gpuMemoryOffset, gpuMemoryRowPitch, imageOffsetx;
+    bool img1Darray = false;
 
     if (desc().buffer_ && !dstResource.desc().buffer_) {
         imageOffsetx = calDstOrigin[0] % dstResource.elementSize();
         gpuMemoryOffset = calSrcOrigin[0] + offset();
         gpuMemoryRowPitch = (calSrcOrigin[1]) ? calSrcOrigin[1] :
             calSize[0] * dstResource.elementSize();
+        img1Darray = (dstResource.desc().topology_ == CL_MEM_OBJECT_IMAGE1D_ARRAY);
     }
     else if (!desc().buffer_ && dstResource.desc().buffer_) {
         imageOffsetx = calSrcOrigin[0] % elementSize();
         gpuMemoryOffset = calDstOrigin[0] + dstResource.offset();
         gpuMemoryRowPitch = (calDstOrigin[1]) ? calDstOrigin[1] :
             calSize[0] * elementSize();
+        img1Darray = (desc().topology_ == CL_MEM_OBJECT_IMAGE1D_ARRAY);
+
     }
 
     if ((desc().buffer_ && !dstResource.desc().buffer_) ||
@@ -1281,7 +1285,8 @@ Resource::partialMemCopyTo(
             // another DRM restriciton... SI has 4 pixels
             (gpuMemoryOffset % 4 != 0) ||
             (dev().settings().sdamPageFaultWar_ &&
-            (imageOffsetx != 0))) {
+            (imageOffsetx != 0)) ||
+            (dev().settings().disableSdmaMemoryToImage_ && img1Darray)) {
             return false;
         }
 

projects/clr/rocclr/runtime/device/pal/palsettings.cpp

@@ -137,6 +137,9 @@ Settings::Settings()
 
     // Disable SDMA workaround by default
     sdamPageFaultWar_ = false;
+
+    // Disable SDMA copy for Image to Mem and Mem to Image by default
+    disableSdmaMemoryToImage_ = false;
 }
 
 bool
@@ -176,6 +179,11 @@ Settings::create(
         switch (palProp.gfxLevel) {
         case Pal::GfxIpLevel::GfxIp9:
             aiPlus_ = true;
+            if (!apuSystem_)
+                // This is a temporary workaround to disable sDMA for MemToImage and
+                // ImageToMem copies and needs be removed later once we have a fix
+                // for Conf. images(mipmaps) 1Darray failures on Vega10
+                disableSdmaMemoryToImage_ = GPU_DISABLE_SDMA_MEMORY_TO_IMAGE;
             break;
         default:
             assert(0 && "Unknown GfxIP type!");

projects/clr/rocclr/runtime/device/pal/palsettings.hpp

@@ -66,8 +66,9 @@ public:
             uint    apuSystem_: 1;          //!< Device is APU system with shared memory
             uint    useDeviceQueue_: 1;     //!< Submit to separate device queue
             uint    singleFpDenorm_: 1;     //!< Support Single FP Denorm
-            uint    sdamPageFaultWar_: 1;   //!< SDAM page fault workaround
-            uint    reserved_: 9;
+            uint    sdamPageFaultWar_: 1;   //!< SDMA page fault workaround
+            uint    disableSdmaMemoryToImage_ : 1;//!< Disable sDMA copy for Memory to Image
+            uint    reserved_: 8;
         };
         uint    value_;
     };

projects/clr/rocclr/runtime/utils/flags.hpp

@@ -202,7 +202,9 @@ release_on_stg(cstring, GPU_WAVE_LIMIT_TRACE, "",                             \
 release(bool, OCL_CODE_CACHE_ENABLE, false,                                   \
         "1 = Enable compiler code cache")                                     \
 release(bool, OCL_CODE_CACHE_RESET, false,                                    \
-        "1 =  Reset the compiler code cache storage")
+        "1 =  Reset the compiler code cache storage")                         \
+release(bool, GPU_DISABLE_SDMA_MEMORY_TO_IMAGE, true,                         \
+        "0 = Enable sDMA for Memory to Image and Image to Memory copies")
 
 
 namespace amd {