SWDEV-463865 - changed device,roc and pal namespaces to be nested under amd

Change-Id: Icad342843c039c634e249a13a7aa31400730b1dd
2024-06-06 18:40:49 +01:00
parent 1590b39f9e
commit 775dc204aa
83 changed files with 187 additions and 185 deletions
@@ -25,7 +25,7 @@

 #include <cmath>

-namespace device {
+namespace amd::device {

 HostBlitManager::HostBlitManager(VirtualDevice& vDev, Setup setup)
    : BlitManager(setup), vDev_(vDev), dev_(vDev.device()) {}
@@ -766,4 +766,4 @@ void HostBlitManager::FillBufferInfo::PackInfo(const device::Memory& memory, siz
  }
 }

-}  // namespace gpu
+}  // namespace amd::device
@@ -30,7 +30,7 @@
 */

 //! GPU Blit Manager Implementation
-namespace device {
+namespace amd::device {

 //! Blit Manager Abstraction class
 class BlitManager : public amd::HeapObject {
@@ -448,6 +448,6 @@ class HostBlitManager : public device::BlitManager {
  HostBlitManager& operator=(const HostBlitManager&);
 };

-/*@}*/} // namespace device
+/*@}*/} // namespace amd::device

 #endif /*BLIT_HPP_*/
@@ -18,7 +18,7 @@
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 THE SOFTWARE. */

-namespace device {
+namespace amd::device {

 #define BLIT_KERNELS(...) #__VA_ARGS__

@@ -257,4 +257,4 @@ const char* BlitImageSourceCode = BLIT_KERNELS(

 );

-}  // namespace device
+}  // namespace amd::device
@@ -34,7 +34,7 @@ extern amd::AppProfile* rocCreateAppProfile();
 #endif

 #if defined(WITH_PAL_DEVICE)
-// namespace pal {
+// namespace amd::pal {
 extern bool PalDeviceLoad();
 extern void PalDeviceUnload();
 //}
@@ -73,7 +73,7 @@ constexpr char hsaIsaNamePrefix[] = "amdgcn-amd-amdhsa--";

 } // namespace

-namespace device {
+namespace amd::device {
 extern const char* BlitLinearSourceCode;
 extern const char* BlitImageSourceCode;

@@ -1041,7 +1041,7 @@ bool Device::IpcDetach(void* dev_ptr) const {

 }  // namespace amd

-namespace device {
+namespace amd::device {

 Settings::Settings() : value_(0) {
  assert((ClExtTotal < (8 * sizeof(extensions_))) && "Too many extensions!");
@@ -1505,4 +1505,4 @@ bool ClBinary::isSPIRV() const {
  return false;
 }

-}  // namespace device
+}  // namespace amd::device
@@ -244,7 +244,7 @@ inline void WriteAqlArgAt(unsigned char* dst, //!< The write pointer to the buff
  *(reinterpret_cast<T*>(dst + offset)) = src;
 }

-namespace device {
+namespace amd::device {
 class ClBinary;
 class BlitManager;
 class Program;
@@ -1331,7 +1331,7 @@ class VirtualDevice : public amd::HeapObject {
  uint index_;              //!< The virtual device unique index
 };

-}  // namespace device
+}  // namespace amd::device

 namespace amd {

@@ -38,7 +38,7 @@
 #include "hsailctx.hpp"
 #endif

-namespace device {
+namespace amd::device {

 // ================================================================================================
 static constexpr clk_value_type_t ClkValueMapType[6][6] = {
@@ -1644,4 +1644,4 @@ void Kernel::InitPrintf(const aclPrintfFmt* aclPrintf) {
  }
 }
 #endif // defined(WITH_COMPILER_LIB)
-}
+} // namespace amd::device
@@ -349,7 +349,7 @@ namespace amd {
  }  // hsa
 }  // amd

-namespace device {
+namespace amd::device {

 class Program;

@@ -601,4 +601,4 @@ class Kernel : public amd::HeapObject {
 #if defined(USE_COMGR_LIBRARY)
 amd_comgr_status_t getMetaBuf(const amd_comgr_metadata_node_t meta, std::string* str);
 #endif // defined(USE_COMGR_LIBRARY)
-} // namespace device
+} // namespace amd::device
@@ -53,7 +53,7 @@
 #include "hsailctx.hpp"
 #endif

-namespace device {
+namespace amd::device {

 // TODO: Can this be unified with the copies in:
 // runtime/device/pal/palprogram.cpp, runtime/device/gpu/gpuprogram.cpp,
@@ -3006,4 +3006,4 @@ bool Program::runInitFiniKernel(kernel_kind_t kind) const {
 bool Program::runInitKernels() { return runInitFiniKernel(kernel_kind_t::InitKernel); }

 bool Program::runFiniKernels() { return runInitFiniKernel(kernel_kind_t::FiniKernel); }
-} /* namespace device*/
+} /* namespace amd::device*/
@@ -54,7 +54,7 @@ namespace option {
 }  // option
 }

-namespace device {
+namespace amd::device {
 class ClBinary;
 class Kernel;

@@ -504,4 +504,4 @@ class ComgrBinaryData {

 #endif

-} // namespace device
+} // namespace amd::device
@@ -41,7 +41,7 @@ void __asan_report_nonself_error(uint64_t *callstack, uint32_t n_callstack, uint
    bool is_abort, const char* name, int64_t vma_adjust, int fd,
    uint64_t file_extent_size, uint64_t file_extent_start = 0);

-namespace {
+namespace amd{
 void handleSanitizerService(Payload* packt_payload, uint64_t activemask,
        const amd::Device* gpu_device, device::UriLocator* uri_locator) {
  // An address results in invalid access in each active lane
@@ -107,4 +107,4 @@ void handleSanitizerService(Payload* packt_payload, uint64_t activemask,
      /*thread key*/"amdgpu", loadAddrAdjust, uri_fd, size, offset);
 #endif
 }
-} //end anonymous namespace
+} // namespace amd
@@ -26,7 +26,7 @@ namespace amd {
  class Device;
 };

-namespace device {
+namespace amd::device {

 // Light abstraction over HSA/PAL signals
 class Signal: public amd::HeapObject {
@@ -24,7 +24,7 @@
 #include "os/os.hpp"
 #include <string>
 #include <utility>
-namespace device{
+namespace amd::device{
 // Interface for HSA/PAL Uri Locators
 class UriLocator {
  public:
@@ -38,6 +38,6 @@ class UriLocator {
  virtual  std::pair<uint64_t, uint64_t> decodeUriAndGetFd(UriInfo& uri,
      amd::Os::FileDesc* uri_fd) = 0;
 };
-} //namespace device
+} //namespace amd::device
 #endif
 #endif
@@ -23,7 +23,7 @@
 #include "device/appprofile.hpp"
 #include "device/pal/palappprofile.hpp"

-namespace pal {
+namespace amd::pal {

 AppProfile::AppProfile()
    : amd::AppProfile(), enableHighPerformanceState_(true), reportAsOCL12Device_(false) {
@@ -32,4 +32,4 @@ AppProfile::AppProfile()

  propertyDataMap_.insert({"OCL12Device", PropertyData(DataType_Boolean, &reportAsOCL12Device_)});
 }
-}  // namespace pal
+}  // namespace amd::pal
@@ -23,7 +23,7 @@
 #include <string>
 #include <map>

-namespace pal {
+namespace amd::pal {

 class AppProfile : public amd::AppProfile {
 public:
@@ -37,4 +37,4 @@ class AppProfile : public amd::AppProfile {
  bool enableHighPerformanceState_;
  bool reportAsOCL12Device_;
 };
-}  // namespace pal
+}  // namespace amd::pal
@@ -26,7 +26,7 @@
 #include "utils/debug.hpp"
 #include <algorithm>

-namespace pal {
+namespace amd::pal {

 DmaBlitManager::DmaBlitManager(VirtualGPU& gpu, Setup setup)
    : HostBlitManager(gpu, setup),
@@ -2703,4 +2703,4 @@ Memory* KernelBlitManager::createView(const Memory& parent, const cl_image_forma
  return gpuImage;
 }

-}  // namespace pal
+}  // namespace amd::pal
@@ -31,7 +31,7 @@
 */

 //! PAL Blit Manager Implementation
-namespace pal {
+namespace amd::pal {

 class Device;
 class Kernel;
@@ -543,5 +543,5 @@ static const char* BlitName[KernelBlitManager::BlitTotal] = {
    "__amd_rocclr_streamOpsWait", "__amd_rocclr_initHeap"
 };

-/*@}*/  // namespace pal
-}  // namespace pal
+/*@}*/  // namespace amd::pal
+}  // namespace amd::pal
@@ -18,7 +18,7 @@
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 THE SOFTWARE. */

-namespace pal {
+namespace amd::pal {

 #define RUNTIME_KERNEL(...) #__VA_ARGS__

@@ -443,4 +443,4 @@ const char* TrapHandlerCode = RUNTIME_KERNEL(
 \n//.endr
 \n.endif
 \n);
-}  // namespace pal
+}  // namespace amd::pal
@@ -23,7 +23,7 @@
 #include "device/pal/paldevice.hpp"
 #include "device/pal/palsettings.hpp"

-namespace pal {
+namespace amd::pal {

 // ================================================================================================
 ManagedBuffer::ManagedBuffer(VirtualGPU& gpu, uint32_t size)
@@ -170,4 +170,4 @@ Memory& XferBuffer::Acquire(uint32_t size) {
  return buffer_view_;
 }

-}  // namespace pal
+}  // namespace amd::pal
@@ -22,8 +22,8 @@

 #include "device/pal/palmemory.hpp"

-//! \namespace pal PAL Resource Implementation
-namespace pal {
+//! \namespace amd::pal PAL Resource Implementation
+namespace amd::pal {

 //! Managed buffer (staging or constant)
 class ManagedBuffer : public amd::EmbeddedObject {
@@ -177,5 +177,5 @@ class XferBuffer : public amd::EmbeddedObject {
  ManagedBuffer& mbuf_;  //!< Managed buffer on GPU
  uint32_t size_;        //!< Mx staging buffer size
 };
-/*@}*/  // namespace pal
-}  // namespace pal
+/*@}*/  // namespace amd::pal
+}  // namespace amd::pal
@@ -22,7 +22,7 @@
 #include "device/pal/palvirtual.hpp"
 #include <array>

-namespace pal {
+namespace amd::pal {

 static constexpr std::array<PCIndexSelect, 50> blockIdToIndexSelect = {{
    PCIndexSelect::None,                     // CPF
@@ -805,4 +805,4 @@ uint64_t PerfCounter::getInfo(uint64_t infoType) const {
  return 0;
 }

-}  // namespace pal
+}  // namespace amd::pal
@@ -25,7 +25,7 @@
 #include "device/pal/paldevice.hpp"
 #include "palPerfExperiment.h"

-namespace pal {
+namespace amd::pal {

 enum class PCIndexSelect : uint {
  None = 0,                        ///< no index
@@ -147,4 +147,4 @@ class PerfCounter : public device::PerfCounter {
  std::vector<int> index_;       //!< Counter index in the PAL container
 };

-}  // namespace pal
+}  // namespace amd::pal
@@ -77,7 +77,7 @@ struct GpuEvent {

 //! PAL Device Implementation

-namespace pal {
+namespace amd::pal {

 //! Maximum number of the supported global atomic counters
 static constexpr uint MaxAtomicCounters = 8;
@@ -490,4 +490,4 @@ static constexpr MemoryFormat MemoryFormatMap[] = {
     {Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X,
      Pal::ChannelSwizzle::X}}};

-}  // namespace pal
+}  // namespace amd::pal
@@ -149,7 +149,7 @@ static std::tuple<Pal::GfxIpLevel, Pal::AsicRevision, const char*> findPal(uint3

 }  // namespace

-namespace device {
+namespace amd::device {
 extern const char* HipExtraSourceCode;
 extern const char* HipExtraSourceCodeNoGWS;
 }
@@ -158,16 +158,16 @@ bool PalDeviceLoad() {
  bool ret = false;

  // Create online devices
-  ret |= pal::Device::init();
+  ret |= amd::pal::Device::init();
  // Create offline GPU devices
-  ret |= pal::NullDevice::init();
+  ret |= amd::pal::NullDevice::init();

  return ret;
 }

-void PalDeviceUnload() { pal::Device::tearDown(); }
+void PalDeviceUnload() { amd::pal::Device::tearDown(); }

-namespace pal {
+namespace amd::pal {

 Util::GenericAllocator NullDevice::allocator_;
 char* Device::platformObj_;
@@ -2777,4 +2777,4 @@ void Device::DestroyExtSemaphore(void* extSemaphore) {
  amd::Os::alignedFree(extSemaphore);
 }

-}  // namespace pal
+}  // namespace amd::pal
@@ -54,7 +54,7 @@
 */

 //! PAL Device Implementation
-namespace pal {
+namespace amd::pal {

 //! A nil device object
 class NullDevice : public amd::Device {
@@ -738,5 +738,5 @@ class Device : public NullDevice {
  amd::Program* trap_handler_ = nullptr;  //!< Trap handler program for debugger setup
 };

-/*@}*/  // namespace pal
-}  // namespace pal
+/*@}*/  // namespace amd::pal
+}  // namespace amd::pal
@@ -21,9 +21,9 @@
 #include "paldevice.hpp"

 #if defined(ATI_OS_LINUX)
-namespace pal {
+namespace amd::pal {
 bool Device::associateD3D10Device(void* d3d10Device) { return false; }
-}  // namespace pal
+}  // namespace amd::pal
 #else  // !ATI_OS_WIN

 #include <D3D10_1.h>
@@ -38,7 +38,7 @@ bool Device::associateD3D10Device(void* d3d10Device) { return false; }
 **************************************************************************************************************/
 #include "DxxOpenCLInteropExt.h"

-namespace pal {
+namespace amd::pal {

 static bool queryD3D10DeviceGPUMask(ID3D10Device* pd3d10Device, UINT* pd3d10DeviceGPUMask) {
  IAmdDxExt* pExt = nullptr;
@@ -146,6 +146,6 @@ bool Device::associateD3D10Device(void* d3d10Device) {
  return canInteroperate;
 }

-}  // namespace pal
+}  // namespace amd::pal

 #endif  // !ATI_OS_WIN
@@ -21,9 +21,9 @@
 #include "paldevice.hpp"

 #if defined(ATI_OS_LINUX)
-namespace pal {
+namespace amd::pal {
 bool Device::associateD3D11Device(void* d3d11Device) { return false; }
-}  // namespace pal
+}  // namespace amd::pal
 #else  // !ATI_OS_LINUX

 #include <D3D11.h>
@@ -38,7 +38,7 @@ bool Device::associateD3D11Device(void* d3d11Device) { return false; }
 **************************************************************************************************************/
 #include "DxxOpenCLInteropExt.h"

-namespace pal {
+namespace amd::pal {

 static bool queryD3D11DeviceGPUMask(ID3D11Device* pd3d11Device, UINT* pd3d11DeviceGPUMask) {
  IAmdDxExt* pExt = nullptr;
@@ -147,6 +147,6 @@ bool Device::associateD3D11Device(void* d3d11Device) {
  return canInteroperate;
 }

-}  // namespace pal
+}  // namespace amd::pal

 #endif  // !ATI_OS_LINUX
@@ -21,9 +21,9 @@
 #include "paldevice.hpp"

 #if defined(ATI_OS_LINUX)
-namespace pal {
+namespace amd::pal {
 bool Device::associateD3D9Device(void* d3d9Device) { return false; }
-}  // namespace pal
+}  // namespace amd::pal
 #else  // !ATI_OS_LINUX

 #include <d3d9.h>
@@ -39,7 +39,7 @@ bool Device::associateD3D9Device(void* d3d9Device) { return false; }
 **************************************************************************************************************/
 #include "DxxOpenCLInteropExt.h"

-namespace pal {
+namespace amd::pal {

 bool Device::associateD3D9Device(void* d3d9Device) {
  D3DCAPS9 pCaps;
@@ -64,5 +64,5 @@ bool Device::associateD3D9Device(void* d3d9Device) {
  return canInteroperate;
 }

-}  // namespace pal
+}  // namespace amd::pal
 #endif  // !ATI_OS_WIN
@@ -93,7 +93,7 @@ static PFNWGLGETCONTEXTGPUINFOAMD wglGetContextGPUInfoAMD = nullptr;
 bool gGlFuncInit = false;
 #endif

-namespace pal {
+namespace amd::pal {

 //
 /// GSL Surface Formats as per defined in cmSurfFmtEnum enum in
@@ -961,4 +961,4 @@ bool Device::resGLFree(void* GLplatformContext, void* mbResHandle, uint type) co
 #endif
 }

-}  // namespace pal
+}  // namespace amd::pal
@@ -41,7 +41,7 @@
 #include "protocols/rgpServer.h"
 #include "protocols/driverControlServer.h"

-namespace pal {
+namespace amd::pal {
 // ================================================================================================
 RgpCaptureMgr::RgpCaptureMgr(Pal::IPlatform* platform, const Device& device)
    : device_(device),
@@ -969,6 +969,6 @@ void RgpCaptureMgr::WriteComputeBindMarker(const VirtualGPU* gpu, uint64_t api_h
  WriteMarker(gpu, &marker, sizeof(marker));
 }

-}  // namespace pal
+}  // namespace amd::pal

 #endif // PAL_GPUOPEN_OCL
@@ -37,7 +37,7 @@
 #include "palQueue.h"
 #include "palUtil.h"

-namespace pal {
+namespace amd::pal {
 class Settings;
 class Device;
 class VirtualGPU;
@@ -88,7 +88,7 @@ class HandlerServer;

 }  // namespace DevDriver

-namespace pal {
+namespace amd::pal {
 // ================================================================================================
 // RgpSqttMarkerIdentifier - Identifiers for RGP SQ thread-tracing markers (Table 1)
 enum RgpSqttMarkerIdentifier : uint32_t {
@@ -429,9 +429,9 @@ inline bool RgpCaptureMgr::IsQueueTimingActive() const {
          (trace_.status_ == TraceStatus::Running || trace_.status_ == TraceStatus::Preparing ||
           trace_.status_ == TraceStatus::WaitingForSqtt));
 }
-}  // namespace pal
+}  // namespace amd::pal
 #else // PAL_GPUOPEN_OCL
-namespace pal {
+namespace amd::pal {
 class RgpCaptureMgr {
 public:
  static RgpCaptureMgr* Create(Pal::IPlatform* platform, const Device& device) { return nullptr; }
@@ -450,5 +450,5 @@ class RgpCaptureMgr {
    return true;
  }
 };
-}  // namespace pal
+}  // namespace amd::pal
 #endif // PAL_GPUOPEN_OCL
@@ -34,7 +34,7 @@
 #include <ctime>
 #include <algorithm>

-namespace pal {
+namespace amd::pal {

 void HSAILKernel::setWorkGroupInfo(const uint32_t privateSegmentSize,
                                   const uint32_t groupSegmentSize, const uint16_t numSGPRs,
@@ -570,4 +570,4 @@ bool LightningKernel::postLoad() {
 }
 #endif  // defined(USE_COMGR_LIBRARY)

-}  // namespace pal
+}  // namespace amd::pal
@@ -45,8 +45,8 @@ class Metadata;
 }  // namespace hsa
 }  // namespace amd

-//! \namespace pal PAL Device Implementation
-namespace pal {
+//! \namespace amd::pal PAL Device Implementation
+namespace amd::pal {

 class VirtualGPU;
 class Device;
@@ -154,5 +154,5 @@ class LightningKernel : public HSAILKernel {
 #endif
 };

-/*@}*/  // namespace pal
-}  // namespace pal
+/*@}*/  // namespace amd::pal
+}  // namespace amd::pal
@@ -41,7 +41,7 @@
 #include <sstream>
 #include <iostream>

-namespace pal {
+namespace amd::pal {

 Memory::Memory(const Device& gpuDev, amd::Memory& owner, size_t size)
    : device::Memory(owner), Resource(gpuDev, size), pinnedMemory_(nullptr), parent_(nullptr) {
@@ -1203,4 +1203,4 @@ bool Image::ValidateMemory(Resource::MemoryType memType) {
  return true;
 }

-}  // namespace pal
+}  // namespace amd::pal
@@ -27,12 +27,12 @@
 /*! \addtogroup GPU
 *  @{
 */
-namespace device {
+namespace amd::device {
 class Memory;
 }

 //! PAL Device Implementation
-namespace pal {
+namespace amd::pal {

 class Device;
 class Heap;
@@ -274,4 +274,4 @@ class Image : public pal::Memory {
  Image* copyImageBuffer_;
 };

-}  // namespace pal
+}  // namespace amd::pal
@@ -38,7 +38,7 @@ bool populateFormatStringHashMap(
    std::map<uint64_t, std::string> &strMap);
 } // namespace amd

-namespace pal {
+namespace amd::pal {

 PrintfDbg::PrintfDbg(Device& device, FILE* file)
    : dbgBuffer_(nullptr),
@@ -732,4 +732,4 @@ bool PrintfDbgHSA::output(VirtualGPU& gpu, bool printfEnabled,
  return true;
 }

-}  // namespace pal
+}  // namespace amd::pal
@@ -48,7 +48,7 @@
 #endif  // copysign

 //! GPU Device Implementation
-namespace pal {
+namespace amd::pal {

 class Kernel;
 class VirtualGPU;
@@ -178,5 +178,5 @@ class PrintfDbgHSA : public PrintfDbg {
  PrintfDbgHSA& operator=(const PrintfDbgHSA&);
 };

-/*@}*/  // namespace pal
-}  // namespace pal
+/*@}*/  // namespace amd::pal
+}  // namespace amd::pal
@@ -35,7 +35,7 @@
 #include <iterator>
 #include <sstream>

-namespace pal {
+namespace amd::pal {

 Segment::Segment() : gpuAccess_(nullptr), cpuAccess_(nullptr), cpuMem_(nullptr) {}

@@ -700,7 +700,7 @@ hsa_status_t PALHSALoaderContext::SamplerDestroy(hsa_agent_t agent,

 static hsa_status_t GetKernelNamesCallback(hsa_executable_t hExec, hsa_executable_symbol_t hSymbol,
                                           void* data) {
-  auto symbol = Symbol::Object(hSymbol);
+  auto symbol = amd::hsa::loader::Symbol::Object(hSymbol);
  auto symbolNameList = reinterpret_cast<std::vector<std::string>*>(data);

  hsa_symbol_kind_t type;
@@ -836,4 +836,4 @@ uint64_t LightningProgram::GetTrapHandlerAddress() const {
  return address;
 }

-}  // namespace pal
+}  // namespace amd::pal
@@ -36,8 +36,8 @@ class Context;
 }  // namespace hsa
 }  // namespace amd

-//! \namespace pal PAL Device Implementation
-namespace pal {
+//! \namespace amd::pal PAL Device Implementation
+namespace amd::pal {

 /*! \addtogroup pal PAL Device Implementation
 *  @{
@@ -79,7 +79,7 @@ class Segment : public amd::HeapObject {
  address cpuMem_;     //!< CPU memory for segment without GPU direct access (backing store)
 };

-class PALHSALoaderContext final : public Context {
+class PALHSALoaderContext final : public hsa::loader::Context {
 public:
  PALHSALoaderContext(HSAILProgram* program) : program_(program) {}

@@ -282,5 +282,5 @@ class LightningProgram : public HSAILProgram {
  virtual bool createBinary(amd::option::Options* options) override;
 };

-/*@}*/  // namespace pal
-}  // namespace pal
+/*@}*/  // namespace amd::pal
+}  // namespace amd::pal
@@ -43,7 +43,7 @@
 #include <iostream>
 #include <cmath>

-namespace pal {
+namespace amd::pal {

 // ================================================================================================
 Pal::Result GpuMemoryReference::MakeResident() const {
@@ -2382,4 +2382,4 @@ void ResourceCache::removeLast() {
  entry.second->release();
 }

-}  // namespace pal
+}  // namespace amd::pal
@@ -28,8 +28,8 @@
 #include <atomic>
 #include <unordered_map>

-//! \namespace pal PAL Resource Implementation
-namespace pal {
+//! \namespace amd::pal PAL Resource Implementation
+namespace amd::pal {

 class Device;
 class VirtualGPU;
@@ -644,5 +644,5 @@ class ResourceCache : public amd::HeapObject {
  FineUncachedMemorySubAllocator mem_sub_alloc_fine_uncached_; //!< Allocator for suballocations in Fine uncached SVM
 };

-/*@}*/  // namespace pal
-}  // namespace pal
+/*@}*/  // namespace amd::pal
+}  // namespace amd::pal
@@ -22,7 +22,7 @@

 #include "hsa.h"

-namespace pal {
+namespace amd::pal {

 //! AmdAqlWrap slot state
 enum AqlWrapState {
@@ -56,7 +56,7 @@ struct AmdAqlWrap {
  uint32_t enqueue_flags;  //!< [LWO/SRO] Contains the flags for the kernel execution start
  uint32_t command_id;     //!< [LWO/SRO] The unique command ID
  uint32_t child_counter;  //!< [LRW/SRW] Counter that determine the launches of child kernels.
-                           // It’s incremented on the
+                           // It's incremented on the
  // start and decremented on the finish. The parent kernel can be considered as
  // done when the value is 0 and the state is DONE
  uint64_t completion;   //!< [LWO/SRO] CL event for the current execution (clk_event_t)
@@ -64,7 +64,7 @@ struct AmdAqlWrap {
  uint64_t wait_list;  //!< [LRO/SRO] Pointer to an array of clk_event_t objects (64 bytes default)
  uint32_t wait_num;   //!< [LWO/SRO] The number of cl_event_wait objects
  uint32_t reserved[5];              //!< For the future usage
-  hsa_kernel_dispatch_packet_t aql;  //!< [LWO/SRO] AQL packet – 64 bytes AQL packet
+  hsa_kernel_dispatch_packet_t aql;  //!< [LWO/SRO] AQL packet - 64 bytes AQL packet
 };

 struct AmdEvent {
@@ -90,4 +90,4 @@ struct SchedulerParam {
  uint32_t reserved[2];     //!< Reserved
 };

-}  // namespace pal
+}  // namespace amd::pal
@@ -31,7 +31,7 @@
 #include "VersionHelpers.h"
 #endif

-namespace pal {
+namespace amd::pal {

 Settings::Settings() {
  // Initialize the GPU device default settings
@@ -506,4 +506,4 @@ void Settings::override() {
  }
 }

-}  // namespace pal
+}  // namespace amd::pal
@@ -29,7 +29,7 @@
 */

 //! PAL Device Implementation
-namespace pal {
+namespace amd::pal {

 //! Device settings
 class Settings : public device::Settings {
@@ -142,5 +142,5 @@ class Settings : public device::Settings {
  using KernelArgImpl = device::Settings::KernelArgImpl;
 };

-/*@}*/  // namespace pal
-}  // namespace pal
+/*@}*/  // namespace amd::pal
+}  // namespace amd::pal
@@ -25,7 +25,7 @@

 #include <functional>

-namespace pal {
+namespace amd::pal {

 Signal::~Signal() {
  dev_->GlbCtx().svmFree(amdSignal_);
@@ -26,7 +26,7 @@

 #include "palEvent.h"

-namespace pal {
+namespace amd::pal {

 class Device;

@@ -21,7 +21,7 @@
 #include "device/pal/palthreadtrace.hpp"
 #include "device/pal/palvirtual.hpp"

-namespace pal {
+namespace amd::pal {

 PalThreadTraceReference* PalThreadTraceReference::Create(VirtualGPU& gpu) {
  Pal::Result result;
@@ -179,4 +179,4 @@ bool ThreadTrace::info(uint infoType, uint* info, uint infoSize) const {
  return true;
 }

-}  // namespace pal
+}  // namespace amd::pal
@@ -26,7 +26,7 @@
 #include "palPerfExperiment.h"

 #include <vector>
-namespace pal {
+namespace amd::pal {

 class VirtualGPU;

@@ -119,4 +119,4 @@ class ThreadTrace : public device::ThreadTrace {
  std::vector<amd::Memory*> memObj_;  //!< ThreadTrace memory objects
 };

-}  // namespace pal
+}  // namespace amd::pal
@@ -25,7 +25,7 @@
 #include "device/pal/palvirtual.hpp"
 #include "device/pal/palcounters.hpp"

-namespace pal {
+namespace amd::pal {

 TimeStamp::TimeStamp(const VirtualGPU& gpu, Pal::IGpuMemory* iMem, uint memOffset, address cpuAddr)
    : gpu_(gpu), iMem_(iMem), memOffset_(memOffset) {
@@ -118,4 +118,4 @@ TimeStamp* TimeStampCache::allocTimeStamp() {
  return ts;
 }

-}  // namespace pal
+}  // namespace amd::pal
@@ -28,7 +28,7 @@
 */

 //! PAL Device Implementation
-namespace pal {
+namespace amd::pal {

 class Device;
 class VirtualGPU;
@@ -130,5 +130,5 @@ class TimeStampCache : public amd::HeapObject {
  uint tsOffset_;                    //!< Active offset in the current mem object
 };

-/*@}*/  // namespace pal
-}  // namespace pal
+/*@}*/  // namespace amd::pal
+}  // namespace amd::pal
@@ -50,7 +50,7 @@
 #include "platform/interop_d3d11.hpp"
 #endif  // _WIN32

-namespace pal {
+namespace amd::pal {

 uint32_t VirtualGPU::Queue::AllocedQueues(const VirtualGPU& gpu, Pal::EngineType type) {
  uint32_t allocedQueues = 0;
@@ -3803,4 +3803,4 @@ void* VirtualGPU::getOrCreateHostcallBuffer() {
  return hostcallBuffer_;
 }

-}  // namespace pal
+}  // namespace amd::pal
@@ -41,7 +41,7 @@
 */

 //! PAL Device Implementation
-namespace pal {
+namespace amd::pal {

 class Device;
 class Kernel;
@@ -765,5 +765,5 @@ template <bool avoidBarrierSubmit> uint VirtualGPU::Queue::submit(bool forceFlus
  return id;
 }

-/*@}*/  // namespace pal
-}  // namespace pal
+/*@}*/  // namespace amd::pal
+}  // namespace amd::pal
@@ -28,7 +28,7 @@
 #include <algorithm>

 amd::AppProfile* rocCreateAppProfile() {
-  amd::AppProfile* appProfile = new roc::AppProfile;
+  amd::AppProfile* appProfile = new amd::roc::AppProfile;

  if ((appProfile == nullptr) || !appProfile->init()) {
    DevLogPrintfError("App Profile init failed, appProfile: 0x%x \n",
@@ -39,7 +39,7 @@ amd::AppProfile* rocCreateAppProfile() {
  return appProfile;
 }

-namespace roc {
+namespace amd::roc {

 bool AppProfile::ParseApplicationProfile() {
  std::string appName("Explorer");
@@ -22,7 +22,7 @@

 #ifndef WITHOUT_HSA_BACKEND

-namespace roc {
+namespace amd::roc {

 class AppProfile : public amd::AppProfile {
 public:
@@ -27,7 +27,7 @@
 #include "utils/debug.hpp"
 #include <algorithm>

-namespace roc {
+namespace amd::roc {
 DmaBlitManager::DmaBlitManager(VirtualGPU& gpu, Setup setup)
    : HostBlitManager(gpu, setup),
      MinSizeForPinnedTransfer(dev().settings().pinnedMinXferSize_),
@@ -2812,4 +2812,4 @@ bool KernelBlitManager::RunGwsInit(
  return result;
 }

-}  // namespace roc
+}  // namespace amd::roc
@@ -33,7 +33,7 @@
 */

 //! ROC Blit Manager Implementation
-namespace roc {
+namespace amd::roc {

 class Device;
 class Kernel;
@@ -678,4 +678,4 @@ inline void KernelBlitManager::setArgument(amd::Kernel* kernel, size_t index,
 }


-/*@}*/} // namespace roc
+/*@}*/} // namespace amd::roc
@@ -18,7 +18,7 @@
 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 THE SOFTWARE. */

-namespace roc {
+namespace amd::roc {

 #define BLIT_KERNEL(...) #__VA_ARGS__

@@ -31,4 +31,4 @@ const char* SchedulerSourceCode = BLIT_KERNEL(
  }
 );

-}  // namespace roc
+}  // namespace amd::roc
@@ -22,7 +22,7 @@
 #include "device/rocm/rocvirtual.hpp"
 #include <array>

-namespace roc {
+namespace amd::roc {

 hsa_status_t PerfCounterCallback(
  hsa_ven_amd_aqlprofile_info_type_t  info_type,
@@ -622,5 +622,5 @@ PerfCounterProfile::~PerfCounterProfile() {
  }
 }

-}  // namespace roc
+}  // namespace amd::roc

@@ -26,7 +26,7 @@
 #include "device/rocm/rocdevice.hpp"
 #include "hsa/hsa_ven_amd_aqlprofile.h"

-namespace roc {
+namespace amd::roc {

 class VirtualGPU;
 class PerfCounterProfile;
@@ -187,7 +187,7 @@ class PerfCounterProfile : public amd::ReferenceCountedObject {

 };

-}  // namespace roc
+}  // namespace amd::roc

 #endif  // ROCCOUNTERS_HPP_

@@ -22,7 +22,7 @@

 #ifndef WITHOUT_HSA_BACKEND

-namespace roc {
+namespace amd::roc {

 //! Alignment restriction for the pinned memory
 static constexpr size_t PinnedMemoryAlignment = 4 * Ki;
@@ -43,6 +43,6 @@ enum HwQueueEngine : uint32_t {
  External  = 4
 };

-} // namespace roc
+} // namespace amd::roc

 #endif
@@ -115,12 +115,12 @@ bool getValueFromIsaMeta(amd_comgr_metadata_node_t& isaMeta, const char* key,

 } // namespace

-namespace device {
+namespace amd::device {
 extern const char* HipExtraSourceCode;
 extern const char* HipExtraSourceCodeNoGWS;
-} // namespace device
+} // namespace amd::device

-namespace roc {
+namespace amd::roc {
 bool roc::Device::isHsaInitialized_ = false;
 std::vector<hsa_agent_t> roc::Device::gpu_agents_;
 std::vector<AgentInfo> roc::Device::cpu_agents_;
@@ -3596,5 +3596,5 @@ device::UriLocator* Device::createUriLocator() const {
 }
 #endif
 #endif
-} // namespace roc
+} // namespace amd::roc
 #endif  // WITHOUT_HSA_BACKEND
@@ -55,7 +55,7 @@
 */

 //! HSA Device Implementation
-namespace roc {
+namespace amd::roc {

 /**
 * @brief List of environment variables that could be used to
@@ -688,7 +688,7 @@ class Device : public NullDevice {
 #endif
 #endif
 };                                // class roc::Device
-}  // namespace roc
+}  // namespace amd::roc

 /**
 * @}
@@ -29,7 +29,7 @@
 #include <dlfcn.h>
 #endif

-namespace roc {
+namespace amd::roc {

 namespace MesaInterop {

@@ -36,7 +36,7 @@ typedef __GLXcontextRec* GLXContext;
 #include "device/rocm/rocregisters.hpp"
 #include "hsa/hsa_ext_amd.h"

-namespace roc {
+namespace amd::roc {

 // Specific typed container for version 1
 typedef struct metadata_amd_ci_vi_s {
@@ -25,7 +25,7 @@

 #ifndef WITHOUT_HSA_BACKEND

-namespace roc {
+namespace amd::roc {

 Kernel::Kernel(std::string name, Program* prog, const uint64_t& kernelCodeHandle,
               const uint32_t workgroupGroupSegmentByteSize,
@@ -205,5 +205,5 @@ bool LightningKernel::postLoad() {
 }
 #endif  // defined(USE_COMGR_LIBRARY)

-}  // namespace roc
+}  // namespace amd::roc
 #endif  // WITHOUT_HSA_BACKEND
@@ -27,7 +27,7 @@

 #ifndef WITHOUT_HSA_BACKEND

-namespace roc {
+namespace amd::roc {

 #define MAX_INFO_STRING_LEN 0x40

@@ -84,6 +84,6 @@ class LightningKernel : public roc::Kernel {
  bool postLoad();
 };

-}  // namespace roc
+}  // namespace amd::roc

 #endif  // WITHOUT_HSA_BACKEND
@@ -38,7 +38,7 @@
 #include "platform/interop_gl.hpp"
 #include "platform/external_memory.hpp"

-namespace roc {
+namespace amd::roc {

 // ======================================= roc::Memory ============================================
 Memory::Memory(const roc::Device& dev, amd::Memory& owner)
@@ -28,7 +28,7 @@
 #include "device/rocm/rocdevice.hpp"
 #include "device/rocm/rocglinterop.hpp"

-namespace roc {
+namespace amd::roc {
 class Memory : public device::Memory {
 public:
  enum MEMORY_KIND {
@@ -39,7 +39,7 @@ bool populateFormatStringHashMap(
    std::map<uint64_t, std::string> &strMap);
 } // namespace amd

-namespace roc {
+namespace amd::roc {

 PrintfDbg::PrintfDbg(Device& device, FILE* file)
    : dbgBuffer_(nullptr), dbgBuffer_size_(0), dbgFile_(file), gpuDevice_(device) {}
@@ -42,7 +42,7 @@
 #endif  // copysign

 //! GPU Device Implementation
-namespace roc {
+namespace amd::roc {

 class Kernel;
 class VirtualGPU;
@@ -120,4 +120,4 @@ class PrintfDbg : public amd::HeapObject {
  PrintfDbg& operator=(const PrintfDbg&);
 };

-/*@}*/} // namespace roc
+/*@}*/} // namespace amd::roc
@@ -35,7 +35,7 @@
 #include <iostream>
 #include <iterator>

-namespace roc {
+namespace amd::roc {

 static inline const char* hsa_strerror(hsa_status_t status) {
  const char* str = nullptr;
@@ -343,6 +343,6 @@ bool LightningProgram::setKernels(void* binary, size_t binSize,
  return true;
 }

-}  // namespace roc
+}  // namespace amd::roc

 #endif  // WITHOUT_HSA_BACKEND
@@ -28,8 +28,8 @@
 #include <iostream>
 #include "rocdevice.hpp"

-//! \namespace roc HSA Device Implementation
-namespace roc {
+//! \namespace amd::roc HSA Device Implementation
+namespace amd::roc {

 class HSAILProgram;
 class LightningProgram;
@@ -125,6 +125,6 @@ private:
                  std::string uri = std::string()) override final;
 };

-/*@}*/} // namespace roc
+/*@}*/} // namespace amd::roc

 #endif /*WITHOUT_HSA_BACKEND*/
@@ -29,7 +29,7 @@
 #error "LITTLEENDIAN_CPU and BIGENDIAN_CPU are mutually exclusive"
 #endif

-namespace roc {
+namespace amd::roc {

 enum SQ_RSRC_IMG_TYPES {
  SQ_RSRC_IMG_1D = 0x08,
@@ -20,7 +20,7 @@

 #pragma once

-namespace roc {
+namespace amd::roc {

 //! AmdAqlWrap slot state
 enum AqlWrapState {
@@ -26,7 +26,7 @@
 #include "rocsettings.hpp"
 #include "device/rocm/rocglinterop.hpp"

-namespace roc {
+namespace amd::roc {

 // ================================================================================================
 Settings::Settings() {
@@ -285,6 +285,6 @@ void Settings::setKernelArgImpl(const amd::Isa& isa, bool isXgmi, bool hasValidH
    kernel_arg_impl_ = kernelArgImpl & (HIP_FORCE_DEV_KERNARG ? 0xF : 0x0);
  }
 }
-}  // namespace roc
+}  // namespace amd::roc

 #endif  // WITHOUT_HSA_BACKEND
@@ -27,7 +27,7 @@
 */

 //! HSA OCL STUB Implementation
-namespace roc {
+namespace amd::roc {

 //! Device settings
 class Settings : public device::Settings {
@@ -101,6 +101,6 @@ class Settings : public device::Settings {
  void setKernelArgImpl(const amd::Isa& isa, bool isXgmi, bool hasValidHDPFlush);
 };

-/*@}*/} // namespace roc
+/*@}*/} // namespace amd::roc

 #endif /*WITHOUT_HSA_BACKEND*/
@@ -22,7 +22,7 @@
 #include "utils/flags.hpp"
 #include "utils/debug.hpp"
 #include "rocsignal.hpp"
-namespace roc {
+namespace amd::roc {

 Signal::~Signal() {
  hsa_signal_destroy(signal_);
@@ -24,7 +24,7 @@

 #include "hsa/hsa.h"

-namespace roc {
+namespace amd::roc {

 class Signal: public device::Signal {
 private:
@@ -23,7 +23,7 @@
 #include "rocurilocator.hpp"
 #include <sstream>

-namespace roc {
+namespace amd::roc {
 hsa_status_t UriLocator::createUriRangeTable() {
  auto execCb = [] (hsa_executable_t exec,
    void *data) -> hsa_status_t {
@@ -178,6 +178,6 @@ UriLocator::UriInfo UriLocator::lookUpUri(uint64_t device_pc) {

  return errorstate;
 }
-} //namespace roc
+} //namespace amd::roc
 #endif
 #endif
@@ -25,7 +25,7 @@
 #include "hsa/hsa_ven_amd_loader.h"

 #include <vector>
-namespace roc {
+namespace amd::roc {
 class UriLocator : public device::UriLocator {
  bool init_ = false;
  struct UriRange {
@@ -73,7 +73,7 @@
 */
 #define HSA_SAMPLER_OBJECT_ALIGNMENT 16

-namespace roc {
+namespace amd::roc {
 // (HSA_FENCE_SCOPE_AGENT << HSA_PACKET_HEADER_ACQUIRE_FENCE_SCOPE) invalidates I, K and L1
 // (HSA_FENCE_SCOPE_SYSTEM << HSA_PACKET_HEADER_RELEASE_FENCE_SCOPE) invalidates L1, L2 and flushes
 // L2
@@ -31,7 +31,7 @@
 #include "hsa/hsa_ven_amd_aqlprofile.h"
 #include "rocsched.hpp"

-namespace roc {
+namespace amd::roc {
 class Device;
 class Memory;
 struct ProfilingSignal;
@@ -31,6 +31,8 @@
 #include <vector>
 #include <utility>

+namespace device = amd::device;
+
 //! \cond ignore
 namespace amd {

@@ -46,10 +46,10 @@
 #define ROCCLR_MEM_PHYMEM               (1u << 25)
 #define ROCCLR_MEM_HSA_CONTIGUOUS       (1u << 24)

-namespace device {
+namespace amd::device {
 class Memory;
 class VirtualDevice;
-}  // namespace device
+}  // namespace amd::device

 namespace amd {