Honor ReadOnly bit in HsaMemFlags
Change-Id: I456cde81384bf0f4bf055711d94b731179706d28
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
[ROCm/ROCR-Runtime commit: 4d0697bf65]
This commit is contained in:
@@ -710,7 +710,6 @@ static vm_object_t *fmm_allocate_memory_in_device(uint32_t gpu_id, void *mem,
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args.flags = flags |
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KFD_IOC_ALLOC_MEM_FLAGS_NONPAGED |
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KFD_IOC_ALLOC_MEM_FLAGS_EXECUTE_ACCESS |
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KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE;
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args.va_addr = (uint64_t)mem;
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if (!topology_is_dgpu(get_device_id_by_gpu_id(gpu_id)) &&
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@@ -862,6 +861,22 @@ static void fmm_release_scratch(uint32_t gpu_id)
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gpu_mem[gpu_mem_id].scratch_physical.limit = NULL;
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}
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static uint32_t fmm_translate_hsa_to_ioc_flags(HsaMemFlags flags)
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{
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uint32_t ioc_flags = 0;
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if (flags.ui32.AQLQueueMemory)
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ioc_flags |= KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM;
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if (flags.ui32.ReadOnly)
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ioc_flags |= KFD_IOC_ALLOC_MEM_FLAGS_READONLY;
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/* TODO: Since, ROCr interfaces doesn't allow caller to set page
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* permissions, mark all user allocations with exec permission.
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* Check for flags.ui32.ExecuteAccess once ROCr is ready.
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*/
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ioc_flags |= KFD_IOC_ALLOC_MEM_FLAGS_EXECUTE_ACCESS;
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return ioc_flags;
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}
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#define SCRATCH_ALIGN 0x10000
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void *fmm_allocate_scratch(uint32_t gpu_id, uint64_t MemorySizeInBytes)
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{
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@@ -992,13 +1007,13 @@ void *fmm_allocate_device(uint32_t gpu_id, uint64_t MemorySizeInBytes, HsaMemFla
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if (flags.ui32.HostAccess)
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ioc_flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC;
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ioc_flags |= fmm_translate_hsa_to_ioc_flags(flags);
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if (topology_is_dgpu(get_device_id_by_gpu_id(gpu_id))) {
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aperture = &svm.dgpu_aperture;
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offset = 0;
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if (flags.ui32.AQLQueueMemory) {
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if (flags.ui32.AQLQueueMemory)
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size = MemorySizeInBytes * 2;
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ioc_flags |= KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM;
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}
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} else {
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aperture = &gpu_mem[gpu_mem_id].gpuvm_aperture;
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offset = GPUVM_APP_OFFSET;
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@@ -1138,10 +1153,9 @@ static void *fmm_allocate_host_gpu(uint32_t node_id, uint64_t MemorySizeInBytes,
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aperture = &svm.dgpu_alt_aperture; /* coherent */
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ioc_flags |= KFD_IOC_ALLOC_MEM_FLAGS_COHERENT;
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}
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if (flags.ui32.AQLQueueMemory) {
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ioc_flags |= fmm_translate_hsa_to_ioc_flags(flags);
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if (flags.ui32.AQLQueueMemory)
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size = MemorySizeInBytes * 2;
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ioc_flags |= KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM;
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}
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/* Paged memory is allocated as a userptr mapping, non-paged
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* memory is allocated from KFD
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@@ -2354,7 +2368,8 @@ static HSAKMT_STATUS fmm_register_user_memory(void *addr, HSAuint64 size, vm_obj
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/* Allocate BO, userptr address is passed in mmap_offset */
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svm_addr = __fmm_allocate_device(gpu_id, aligned_size, aperture, 0,
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&aligned_addr, KFD_IOC_ALLOC_MEM_FLAGS_USERPTR, &obj);
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&aligned_addr, KFD_IOC_ALLOC_MEM_FLAGS_USERPTR |
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KFD_IOC_ALLOC_MEM_FLAGS_EXECUTE_ACCESS, &obj);
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if (!svm_addr)
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return HSAKMT_STATUS_ERROR;
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