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SWDEV-457337 - Fix header alignment

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Change-Id: I9f25f6c4f0d00c76b66d13162f30be11368f5b59
Signed-off-by: Dalibor Stanisavljevic <Dalibor.Stanisavljevic@amd.com>
This commit is contained in:
Dalibor Stanisavljevic
2024-04-24 11:16:06 +02:00
parent 1cee1baac2
commit 7b2463abe0
24 changed files with 983 additions and 976 deletions
Download Patch File Download Diff File Expand all files Collapse all files
README.md
+6 -6
View File
@@ -154,11 +154,11 @@ int main() {
// For each device of the socket, get name and temperature.
for (uint32_t j=0; j < device_count; j++) {
// Get device type. Since the amdsmi is initialized with
// AMD_SMI_INIT_AMD_GPUS, the processor_type must be AMD_GPU.
// AMD_SMI_INIT_AMD_GPUS, the processor_type must be AMDSMI_PROCESSOR_TYPE_AMD_GPU.
processor_type_t processor_type;
ret = amdsmi_get_processor_type(processor_handles[j], &processor_type);
if (processor_type != AMD_GPU) {
std::cout << "Expect AMD_GPU device type!\n";
if (processor_type != AMDSMI_PROCESSOR_TYPE_AMD_GPU) {
std::cout << "Expect AMDSMI_PROCESSOR_TYPE_AMD_GPU device type!\n";
return 1;
}
@@ -170,7 +170,7 @@ int main() {
// Get temperature
int64_t val_i64 = 0;
ret = amdsmi_get_temp_metric(processor_handles[j], TEMPERATURE_TYPE_EDGE,
ret = amdsmi_get_temp_metric(processor_handles[j], AMDSMI_TEMPERATURE_TYPE_EDGE,
AMDSMI_TEMP_CURRENT, &val_i64);
std::cout << "\t\tTemperature: " << val_i64 << "C" << std::endl;
}
@@ -212,8 +212,8 @@ int main(int argc, char **argv) {
for (uint32_t i = 0; i < socket_count; i++) {
uint32_t cpu_count = 0;
// Set processor type as AMD_CPU
processor_type_t processor_type = AMD_CPU;
// Set processor type as AMDSMI_PROCESSOR_TYPE_AMD_CPU
processor_type_t processor_type = AMDSMI_PROCESSOR_TYPE_AMD_CPU;
ret = amdsmi_get_processor_handles_by_type(sockets[i], processor_type, nullptr, &cpu_count);
// Allocate the memory for the cpus
amdsmi_cli/amdsmi_commands.py
+4 -4
View File
@@ -691,7 +691,7 @@ class AMDSMICommands():
# Get vram type string
vram_type_enum = vram_info['vram_type']
if vram_type_enum == amdsmi_interface.amdsmi_wrapper.VRAM_TYPE_GDDR6:
if vram_type_enum == amdsmi_interface.amdsmi_wrapper.AMDSMI_VRAM_TYPE_GDDR6:
vram_type = "GDDR6"
else:
vram_type = amdsmi_interface.amdsmi_wrapper.amdsmi_vram_type_t__enumvalues[vram_type_enum]
@@ -712,13 +712,13 @@ class AMDSMICommands():
vram_info_dict['vendor'] = vram_vendor
# Populate vram size with unit
vram_info_dict['size'] = vram_info['vram_size_mb']
vram_info_dict['size'] = vram_info['vram_size']
vram_size_unit = "MB"
if self.logger.is_human_readable_format():
vram_info_dict['size'] = f"{vram_info['vram_size_mb']} {vram_size_unit}"
vram_info_dict['size'] = f"{vram_info['vram_size']} {vram_size_unit}"
if self.logger.is_json_format():
vram_info_dict['size'] = {"value" : vram_info['vram_size_mb'],
vram_info_dict['size'] = {"value" : vram_info['vram_size'],
"unit" : vram_size_unit}
except amdsmi_exception.AmdSmiLibraryException as e:
example/amd_smi_drm_example.cc
+169 -169
View File
@@ -71,146 +71,146 @@
void getFWNameFromId(int id, char *name)
{
switch (id) {
case FW_ID_SMU:
strcpy(name, "SMU");
break;
case FW_ID_CP_CE:
strcpy(name, "CP_CE");
break;
case FW_ID_CP_PFP:
strcpy(name, "CP_PFP");
break;
case FW_ID_CP_ME:
strcpy(name, "CP_ME");
break;
case FW_ID_CP_MEC_JT1:
strcpy(name, "CP_MEC_JT1");
break;
case FW_ID_CP_MEC_JT2:
strcpy(name, "CP_MEC_JT2");
break;
case FW_ID_CP_MEC1:
strcpy(name, "CP_MEC1");
break;
case FW_ID_CP_MEC2:
strcpy(name, "CP_MEC2");
break;
case FW_ID_RLC:
strcpy(name, "RLC");
break;
case FW_ID_SDMA0:
strcpy(name, "SDMA0");
break;
case FW_ID_SDMA1:
strcpy(name, "SDMA1");
break;
case FW_ID_SDMA2:
strcpy(name, "SDMA2");
break;
case FW_ID_SDMA3:
strcpy(name, "SDMA3");
break;
case FW_ID_SDMA4:
strcpy(name, "SDMA4");
break;
case FW_ID_SDMA5:
strcpy(name, "SDMA5");
break;
case FW_ID_SDMA6:
strcpy(name, "SDMA6");
break;
case FW_ID_SDMA7:
strcpy(name, "SDMA7");
break;
case FW_ID_VCN:
strcpy(name, "VCN");
break;
case FW_ID_UVD:
strcpy(name, "UVD");
break;
case FW_ID_VCE:
strcpy(name, "VCE");
break;
case FW_ID_ISP:
strcpy(name, "ISP");
break;
case FW_ID_DMCU_ERAM:
strcpy(name, "DMCU_ERAM");
break;
case FW_ID_DMCU_ISR:
strcpy(name, "DMCU_ISR");
break;
case FW_ID_RLC_RESTORE_LIST_GPM_MEM:
strcpy(name, "RLC_RESTORE_LIST_GPM_MEM");
break;
case FW_ID_RLC_RESTORE_LIST_SRM_MEM:
strcpy(name, "RLC_RESTORE_LIST_SRM_MEM");
break;
case FW_ID_RLC_RESTORE_LIST_CNTL:
strcpy(name, "RLC_RESTORE_LIST_CNTL");
break;
case FW_ID_RLC_V:
strcpy(name, "RLC_V");
break;
case FW_ID_MMSCH:
strcpy(name, "MMSCH");
break;
case FW_ID_PSP_SYSDRV:
strcpy(name, "PSP_SYSDRV");
break;
case FW_ID_PSP_SOSDRV:
strcpy(name, "PSP_SOSDRV");
break;
case FW_ID_PSP_TOC:
strcpy(name, "PSP_TOC");
break;
case FW_ID_PSP_KEYDB:
strcpy(name, "PSP_KEYDB");
break;
case FW_ID_DFC:
strcpy(name, "DFC");
break;
case FW_ID_PSP_SPL:
strcpy(name, "PSP_SPL");
break;
case FW_ID_DRV_CAP:
strcpy(name, "DRV_CAP");
break;
case FW_ID_MC:
strcpy(name, "MC");
break;
case FW_ID_PSP_BL:
strcpy(name, "PSP_BL");
break;
case FW_ID_CP_PM4:
strcpy(name, "CP_PM4");
break;
case FW_ID_ASD:
strcpy(name, "ID_ASD");
break;
case FW_ID_TA_RAS:
strcpy(name, "ID_TA_RAS");
break;
case FW_ID_TA_XGMI:
strcpy(name, "ID_TA_XGMI");
break;
case FW_ID_RLC_SRLG:
strcpy(name, "ID_RLC_SRLG");
break;
case FW_ID_RLC_SRLS:
strcpy(name, "ID_RLC_SRLS");
break;
case FW_ID_PM:
strcpy(name, "ID_PM");
break;
case FW_ID_DMCU:
strcpy(name, "ID_DMCU");
break;
default:
strcpy(name, "");
break;
}
switch (id) {
case AMDSMI_FW_ID_SMU:
strcpy(name, "SMU");
break;
case AMDSMI_FW_ID_CP_CE:
strcpy(name, "CP_CE");
break;
case AMDSMI_FW_ID_CP_PFP:
strcpy(name, "CP_PFP");
break;
case AMDSMI_FW_ID_CP_ME:
strcpy(name, "CP_ME");
break;
case AMDSMI_FW_ID_CP_MEC_JT1:
strcpy(name, "CP_MEC_JT1");
break;
case AMDSMI_FW_ID_CP_MEC_JT2:
strcpy(name, "CP_MEC_JT2");
break;
case AMDSMI_FW_ID_CP_MEC1:
strcpy(name, "CP_MEC1");
break;
case AMDSMI_FW_ID_CP_MEC2:
strcpy(name, "CP_MEC2");
break;
case AMDSMI_FW_ID_RLC:
strcpy(name, "RLC");
break;
case AMDSMI_FW_ID_SDMA0:
strcpy(name, "SDMA0");
break;
case AMDSMI_FW_ID_SDMA1:
strcpy(name, "SDMA1");
break;
case AMDSMI_FW_ID_SDMA2:
strcpy(name, "SDMA2");
break;
case AMDSMI_FW_ID_SDMA3:
strcpy(name, "SDMA3");
break;
case AMDSMI_FW_ID_SDMA4:
strcpy(name, "SDMA4");
break;
case AMDSMI_FW_ID_SDMA5:
strcpy(name, "SDMA5");
break;
case AMDSMI_FW_ID_SDMA6:
strcpy(name, "SDMA6");
break;
case AMDSMI_FW_ID_SDMA7:
strcpy(name, "SDMA7");
break;
case AMDSMI_FW_ID_VCN:
strcpy(name, "VCN");
break;
case AMDSMI_FW_ID_UVD:
strcpy(name, "UVD");
break;
case AMDSMI_FW_ID_VCE:
strcpy(name, "VCE");
break;
case AMDSMI_FW_ID_ISP:
strcpy(name, "ISP");
break;
case AMDSMI_FW_ID_DMCU_ERAM:
strcpy(name, "DMCU_ERAM");
break;
case AMDSMI_FW_ID_DMCU_ISR:
strcpy(name, "DMCU_ISR");
break;
case AMDSMI_FW_ID_RLC_RESTORE_LIST_GPM_MEM:
strcpy(name, "RLC_RESTORE_LIST_GPM_MEM");
break;
case AMDSMI_FW_ID_RLC_RESTORE_LIST_SRM_MEM:
strcpy(name, "RLC_RESTORE_LIST_SRM_MEM");
break;
case AMDSMI_FW_ID_RLC_RESTORE_LIST_CNTL:
strcpy(name, "RLC_RESTORE_LIST_CNTL");
break;
case AMDSMI_FW_ID_RLC_V:
strcpy(name, "RLC_V");
break;
case AMDSMI_FW_ID_MMSCH:
strcpy(name, "MMSCH");
break;
case AMDSMI_FW_ID_PSP_SYSDRV:
strcpy(name, "PSP_SYSDRV");
break;
case AMDSMI_FW_ID_PSP_SOSDRV:
strcpy(name, "PSP_SOSDRV");
break;
case AMDSMI_FW_ID_PSP_TOC:
strcpy(name, "PSP_TOC");
break;
case AMDSMI_FW_ID_PSP_KEYDB:
strcpy(name, "PSP_KEYDB");
break;
case AMDSMI_FW_ID_DFC:
strcpy(name, "DFC");
break;
case AMDSMI_FW_ID_PSP_SPL:
strcpy(name, "PSP_SPL");
break;
case AMDSMI_FW_ID_DRV_CAP:
strcpy(name, "DRV_CAP");
break;
case AMDSMI_FW_ID_MC:
strcpy(name, "MC");
break;
case AMDSMI_FW_ID_PSP_BL:
strcpy(name, "PSP_BL");
break;
case AMDSMI_FW_ID_CP_PM4:
strcpy(name, "CP_PM4");
break;
case AMDSMI_FW_ID_ASD:
strcpy(name, "ID_ASD");
break;
case AMDSMI_FW_ID_TA_RAS:
strcpy(name, "ID_TA_RAS");
break;
case AMDSMI_FW_ID_TA_XGMI:
strcpy(name, "ID_TA_XGMI");
break;
case AMDSMI_FW_ID_RLC_SRLG:
strcpy(name, "ID_RLC_SRLG");
break;
case AMDSMI_FW_ID_RLC_SRLS:
strcpy(name, "ID_RLC_SRLS");
break;
case AMDSMI_FW_ID_PM:
strcpy(name, "ID_PM");
break;
case AMDSMI_FW_ID_DMCU:
strcpy(name, "ID_DMCU");
break;
default:
strcpy(name, "");
break;
}
}
template <typename T>
@@ -267,12 +267,12 @@ int main() {
// For each device of the socket, get name and temperature.
for (uint32_t j = 0; j < device_count; j++) {
// Get device type. Since the amdsmi is initialized with
// AMD_SMI_INIT_AMD_GPUS, the processor_type must be AMD_GPU.
// AMD_SMI_INIT_AMD_GPUS, the processor_type must be AMDSMI_PROCESSOR_TYPE_AMD_GPU.
processor_type_t processor_type = {};
ret = amdsmi_get_processor_type(processor_handles[j], &processor_type);
CHK_AMDSMI_RET(ret)
if (processor_type != AMD_GPU) {
std::cout << "Expect AMD_GPU device type!\n";
if (processor_type != AMDSMI_PROCESSOR_TYPE_AMD_GPU) {
std::cout << "Expect AMDSMI_PROCESSOR_TYPE_AMD_GPU device type!\n";
return AMDSMI_STATUS_NOT_SUPPORTED;
}
@@ -282,10 +282,10 @@ int main() {
CHK_AMDSMI_RET(ret)
printf(" Output of amdsmi_get_gpu_device_bdf:\n");
printf("\tDevice[%d] BDF %04lx:%02x:%02x.%d\n\n", i,
bdf.fields.domain_number,
bdf.fields.bus_number,
bdf.fields.device_number,
bdf.fields.function_number);
bdf.domain_number,
bdf.bus_number,
bdf.device_number,
bdf.function_number);
// Get handle from BDF
amdsmi_processor_handle dev_handle;
@@ -383,20 +383,20 @@ int main() {
// Get GFX clock measurements
amdsmi_clk_info_t gfx_clk_values = {};
ret = amdsmi_get_clock_info(processor_handles[j], CLK_TYPE_GFX,
ret = amdsmi_get_clock_info(processor_handles[j], AMDSMI_CLK_TYPE_GFX,
&gfx_clk_values);
CHK_AMDSMI_RET(ret)
printf(" Output of amdsmi_get_clock_info:\n");
printf("\tGPU GFX Max Clock: %d\n", gfx_clk_values.max_clk);
printf("\tGPU GFX Current Clock: %d\n", gfx_clk_values.cur_clk);
printf("\tGPU GFX Current Clock: %d\n", gfx_clk_values.clk);
// Get MEM clock measurements
amdsmi_clk_info_t mem_clk_values = {};
ret = amdsmi_get_clock_info(processor_handles[j], CLK_TYPE_MEM,
ret = amdsmi_get_clock_info(processor_handles[j], AMDSMI_CLK_TYPE_MEM,
&mem_clk_values);
CHK_AMDSMI_RET(ret)
printf("\tGPU MEM Max Clock: %d\n", mem_clk_values.max_clk);
printf("\tGPU MEM Current Clock: %d\n\n", mem_clk_values.cur_clk);
printf("\tGPU MEM Current Clock: %d\n\n", mem_clk_values.clk);
// Get PCIe status
amdsmi_pcie_info_t pcie_info = {};
@@ -422,7 +422,7 @@ int main() {
// Get VRAM temperature limit
int64_t temperature = 0;
ret = amdsmi_get_temp_metric(
processor_handles[j], TEMPERATURE_TYPE_VRAM,
processor_handles[j], AMDSMI_TEMPERATURE_TYPE_VRAM,
AMDSMI_TEMP_CRITICAL, &temperature);
CHK_AMDSMI_RET(ret)
printf(" Output of amdsmi_get_temp_metric:\n");
@@ -430,7 +430,7 @@ int main() {
// Get GFX temperature limit
ret = amdsmi_get_temp_metric(
processor_handles[j], TEMPERATURE_TYPE_EDGE,
processor_handles[j], AMDSMI_TEMPERATURE_TYPE_EDGE,
AMDSMI_TEMP_CRITICAL, &temperature);
if (ret != amdsmi_status_t::AMDSMI_STATUS_NOT_SUPPORTED) {
CHK_AMDSMI_RET(ret)
@@ -440,10 +440,10 @@ int main() {
// Get temperature measurements
// amdsmi_temperature_t edge_temp, hotspot_temp, vram_temp,
// plx_temp;
int64_t temp_measurements[TEMPERATURE_TYPE__MAX + 1];
int64_t temp_measurements[AMDSMI_TEMPERATURE_TYPE__MAX + 1];
amdsmi_temperature_type_t temp_types[4] = {
TEMPERATURE_TYPE_EDGE, TEMPERATURE_TYPE_HOTSPOT,
TEMPERATURE_TYPE_VRAM, TEMPERATURE_TYPE_PLX};
AMDSMI_TEMPERATURE_TYPE_EDGE, AMDSMI_TEMPERATURE_TYPE_HOTSPOT,
AMDSMI_TEMPERATURE_TYPE_VRAM, AMDSMI_TEMPERATURE_TYPE_PLX};
for (const auto &temp_type : temp_types) {
ret = amdsmi_get_temp_metric(
processor_handles[j], temp_type,
@@ -455,13 +455,13 @@ int main() {
}
printf(" Output of amdsmi_get_temp_metric:\n");
printf("\tGPU Edge temp measurement: %ld\n",
temp_measurements[TEMPERATURE_TYPE_EDGE]);
temp_measurements[AMDSMI_TEMPERATURE_TYPE_EDGE]);
printf("\tGPU Hotspot temp measurement: %ld\n",
temp_measurements[TEMPERATURE_TYPE_HOTSPOT]);
temp_measurements[AMDSMI_TEMPERATURE_TYPE_HOTSPOT]);
printf("\tGPU VRAM temp measurement: %ld\n",
temp_measurements[TEMPERATURE_TYPE_VRAM]);
temp_measurements[AMDSMI_TEMPERATURE_TYPE_VRAM]);
printf("\tGPU PLX temp measurement: %ld\n\n",
temp_measurements[TEMPERATURE_TYPE_PLX]);
temp_measurements[AMDSMI_TEMPERATURE_TYPE_PLX]);
// Get RAS features enabled
char block_names[14][10] = {"UMC", "SDMA", "GFX", "MMHUB",
@@ -542,10 +542,10 @@ int main() {
uint64_t gfx = 0, enc = 0;
char bdf_str[20];
sprintf(bdf_str, "%04lx:%02x:%02x.%d",
bdf.fields.domain_number,
bdf.fields.bus_number,
bdf.fields.device_number,
bdf.fields.function_number);
bdf.domain_number,
bdf.bus_number,
bdf.device_number,
bdf.function_number);
int num = 0;
ret = amdsmi_get_gpu_process_list(processor_handles[j], &num_process, process_info_list);
std::cout << "Allocation size for process list: " << num_process << "\n";
@@ -635,7 +635,7 @@ int main() {
// Get temperature
int64_t val_i64 = 0;
ret = amdsmi_get_temp_metric(processor_handles[j], TEMPERATURE_TYPE_EDGE,
ret = amdsmi_get_temp_metric(processor_handles[j], AMDSMI_TEMPERATURE_TYPE_EDGE,
AMDSMI_TEMP_CURRENT, &val_i64);
if (ret != amdsmi_status_t::AMDSMI_STATUS_NOT_SUPPORTED) {
CHK_AMDSMI_RET(ret)
@@ -674,10 +674,10 @@ int main() {
CHK_AMDSMI_RET(ret)
printf(" Output of amdsmi_get_gpu_metrics_info:\n");
printf("\tDevice[%d] BDF %04lx:%02x:%02x.%d\n\n", i,
bdf.fields.domain_number,
bdf.fields.bus_number,
bdf.fields.device_number,
bdf.fields.function_number);
bdf.domain_number,
bdf.bus_number,
bdf.device_number,
bdf.function_number);
std::cout << "\t**.common_header.format_revision : "
<< print_unsigned_int(gpu_metrics.common_header.format_revision) << "\n";
example/amd_smi_nodrm_example.cc
+30 -30
View File
@@ -113,12 +113,12 @@ int main() {
// For each device of the socket, get name and temperature.
for (uint32_t j = 0; j < device_count; j++) {
// Get device type. Since the amdsmi is initialized with
// AMD_SMI_INIT_AMD_GPUS, the processor_type must be AMD_GPU.
// AMD_SMI_INIT_AMD_GPUS, the processor_type must be AMDSMI_PROCESSOR_TYPE_AMD_GPU.
processor_type_t processor_type = {};
ret = amdsmi_get_processor_type(processor_handles[j], &processor_type);
CHK_AMDSMI_RET(ret)
if (processor_type != AMD_GPU) {
std::cout << "Expect AMD_GPU device type!\n";
if (processor_type != AMDSMI_PROCESSOR_TYPE_AMD_GPU) {
std::cout << "Expect AMDSMI_PROCESSOR_TYPE_AMD_GPU device type!\n";
return AMDSMI_STATUS_NOT_SUPPORTED;
}
@@ -137,10 +137,10 @@ int main() {
CHK_AMDSMI_RET(ret)
printf(" Output of amdsmi_get_gpu_device_bdf:\n");
printf("\tDevice[%d] BDF %04lx:%02x:%02x.%d\n\n", i,
bdf.fields.domain_number,
bdf.fields.bus_number,
bdf.fields.device_number,
bdf.fields.function_number);
bdf.domain_number,
bdf.bus_number,
bdf.device_number,
bdf.function_number);
amdsmi_asic_info_t asic_info = {};
ret = amdsmi_get_gpu_asic_info(processor_handles[j], &asic_info);
@@ -183,63 +183,63 @@ int main() {
printf(" Output of amdsmi_get_fw_info:\n");
printf("\tFirmware version: %d\n", fw_information.num_fw_info);
printf("\tSMU: %ld\n",
fw_information.fw_info_list[amdsmi_fw_block_t::FW_ID_SMU]
fw_information.fw_info_list[amdsmi_fw_block_t::AMDSMI_FW_ID_SMU]
.fw_version);
printf("\tPM: %ld\n",
fw_information.fw_info_list[amdsmi_fw_block_t::FW_ID_PM]
fw_information.fw_info_list[amdsmi_fw_block_t::AMDSMI_FW_ID_PM]
.fw_version);
printf("\tVCN: %ld\n",
fw_information.fw_info_list[amdsmi_fw_block_t::FW_ID_VCN]
fw_information.fw_info_list[amdsmi_fw_block_t::AMDSMI_FW_ID_VCN]
.fw_version);
printf("\tCP_ME: %ld\n",
fw_information.fw_info_list[amdsmi_fw_block_t::FW_ID_CP_ME]
fw_information.fw_info_list[amdsmi_fw_block_t::AMDSMI_FW_ID_CP_ME]
.fw_version);
printf("\tCP_PFP: %ld\n",
fw_information.fw_info_list[amdsmi_fw_block_t::FW_ID_CP_PFP]
fw_information.fw_info_list[amdsmi_fw_block_t::AMDSMI_FW_ID_CP_PFP]
.fw_version);
printf("\tCP_CE: %ld\n",
fw_information.fw_info_list[amdsmi_fw_block_t::FW_ID_CP_CE]
fw_information.fw_info_list[amdsmi_fw_block_t::AMDSMI_FW_ID_CP_CE]
.fw_version);
printf("\tRLC: %ld\n",
fw_information.fw_info_list[amdsmi_fw_block_t::FW_ID_RLC]
fw_information.fw_info_list[amdsmi_fw_block_t::AMDSMI_FW_ID_RLC]
.fw_version);
printf("\tCP_MEC1: %ld\n",
fw_information.fw_info_list[amdsmi_fw_block_t::FW_ID_CP_MEC1]
fw_information.fw_info_list[amdsmi_fw_block_t::AMDSMI_FW_ID_CP_MEC1]
.fw_version);
printf("\tCP_MEC2: %ld\n",
fw_information.fw_info_list[amdsmi_fw_block_t::FW_ID_CP_MEC2]
fw_information.fw_info_list[amdsmi_fw_block_t::AMDSMI_FW_ID_CP_MEC2]
.fw_version);
printf("\tSDMA0: %ld\n",
fw_information.fw_info_list[amdsmi_fw_block_t::FW_ID_SDMA0]
fw_information.fw_info_list[amdsmi_fw_block_t::AMDSMI_FW_ID_SDMA0]
.fw_version);
printf("\tMC: %ld\n",
fw_information.fw_info_list[amdsmi_fw_block_t::FW_ID_MC]
fw_information.fw_info_list[amdsmi_fw_block_t::AMDSMI_FW_ID_MC]
.fw_version);
printf("\tRLC RESTORE LIST CNTL: %ld\n",
fw_information
.fw_info_list
[amdsmi_fw_block_t::FW_ID_RLC_RESTORE_LIST_CNTL]
[amdsmi_fw_block_t::AMDSMI_FW_ID_RLC_RESTORE_LIST_CNTL]
.fw_version);
printf("\tRLC RESTORE LIST GPM MEM: %ld\n",
fw_information
.fw_info_list
[amdsmi_fw_block_t::FW_ID_RLC_RESTORE_LIST_GPM_MEM]
[amdsmi_fw_block_t::AMDSMI_FW_ID_RLC_RESTORE_LIST_GPM_MEM]
.fw_version);
printf("\tRLC RESTORE LIST SRM MEM: %ld\n",
fw_information
.fw_info_list
[amdsmi_fw_block_t::FW_ID_RLC_RESTORE_LIST_SRM_MEM]
[amdsmi_fw_block_t::AMDSMI_FW_ID_RLC_RESTORE_LIST_SRM_MEM]
.fw_version);
printf(
"\tPSP SOSDRV: %ld\n\n",
fw_information.fw_info_list[amdsmi_fw_block_t::FW_ID_PSP_SOSDRV]
fw_information.fw_info_list[amdsmi_fw_block_t::AMDSMI_FW_ID_PSP_SOSDRV]
.fw_version);
// Get temperature measurements
int64_t temp_measurements[TEMPERATURE_TYPE__MAX + 1];
int64_t temp_measurements[AMDSMI_TEMPERATURE_TYPE__MAX + 1];
amdsmi_temperature_type_t temp_types[4] = {
TEMPERATURE_TYPE_EDGE, TEMPERATURE_TYPE_HOTSPOT,
TEMPERATURE_TYPE_VRAM, TEMPERATURE_TYPE_PLX};
AMDSMI_TEMPERATURE_TYPE_EDGE, AMDSMI_TEMPERATURE_TYPE_HOTSPOT,
AMDSMI_TEMPERATURE_TYPE_VRAM, AMDSMI_TEMPERATURE_TYPE_PLX};
for (const auto &temp_type : temp_types) {
ret = amdsmi_get_temp_metric(
processor_handles[j], temp_type,
@@ -249,13 +249,13 @@ int main() {
}
printf(" Output of amdsmi_get_temp_metric:\n");
printf("\tGPU Edge temp measurement: %ld\n",
temp_measurements[TEMPERATURE_TYPE_EDGE]);
temp_measurements[AMDSMI_TEMPERATURE_TYPE_EDGE]);
printf("\tGPU Hotspot temp measurement: %ld\n",
temp_measurements[TEMPERATURE_TYPE_HOTSPOT]);
temp_measurements[AMDSMI_TEMPERATURE_TYPE_HOTSPOT]);
printf("\tGPU VRAM temp measurement: %ld\n",
temp_measurements[TEMPERATURE_TYPE_VRAM]);
temp_measurements[AMDSMI_TEMPERATURE_TYPE_VRAM]);
printf("\tGPU PLX temp measurement: %ld\n\n",
temp_measurements[TEMPERATURE_TYPE_PLX]);
temp_measurements[AMDSMI_TEMPERATURE_TYPE_PLX]);
// Get bad pages
char bad_page_status_names[3][15] = {"RESERVED", "PENDING",
@@ -310,7 +310,7 @@ int main() {
// Get temperature
int64_t val_i64 = 0;
ret = amdsmi_get_temp_metric(processor_handles[j], TEMPERATURE_TYPE_EDGE,
ret = amdsmi_get_temp_metric(processor_handles[j], AMDSMI_TEMPERATURE_TYPE_EDGE,
AMDSMI_TEMP_CURRENT, &val_i64);
CHK_AMDSMI_RET(ret)
printf(" Output of amdsmi_get_temp_metric:\n");
example/amdsmi_esmi_intg_example.cc
+4 -4
View File
@@ -104,8 +104,8 @@ int main(int argc, char **argv) {
uint32_t cpu_count = 0;
uint32_t core_count = 0;
// Set processor type as AMD_CPU
processor_type_t processor_type = AMD_CPU;
// Set processor type as AMDSMI_PROCESSOR_TYPE_AMD_CPU
processor_type_t processor_type = AMDSMI_PROCESSOR_TYPE_AMD_CPU;
ret = amdsmi_get_processor_handles_by_type(sockets[i], processor_type, nullptr, &cpu_count);
CHK_AMDSMI_RET(ret)
@@ -116,8 +116,8 @@ int main(int argc, char **argv) {
ret = amdsmi_get_processor_handles_by_type(sockets[i], processor_type, &plist[0], &cpu_count);
CHK_AMDSMI_RET(ret)
// Set processor type as AMD_CPU_CORE
processor_type = AMD_CPU_CORE;
// Set processor type as AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE
processor_type = AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE;
ret = amdsmi_get_processor_handles_by_type(sockets[i], processor_type, nullptr, &core_count);
CHK_AMDSMI_RET(ret)
include/amd_smi/amdsmi.h
+148 -146
View File
@@ -171,8 +171,8 @@ typedef enum {
} amdsmi_mm_ip_t;
typedef enum {
CONTAINER_LXC,
CONTAINER_DOCKER,
AMDSMI_CONTAINER_LXC,
AMDSMI_CONTAINER_DOCKER,
} amdsmi_container_types_t;
//! opaque handler point to underlying implementation
@@ -184,18 +184,18 @@ typedef void *amdsmi_cpusocket_handle;
/**
* @brief Processor types detectable by AMD SMI
* AMD_CPU - CPU Socket is a physical component that holds the CPU.
* AMD_CPU_CORE - CPU Cores are number of individual processing units within the CPU.
* AMD_APU - Combination of AMD_CPU and integrated GPU on single die
* AMDSMI_PROCESSOR_TYPE_AMD_CPU - CPU Socket is a physical component that holds the CPU.
* AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE - CPU Cores are number of individual processing units within the CPU.
* AMDSMI_PROCESSOR_TYPE_AMD_APU - Combination of AMDSMI_PROCESSOR_TYPE_AMD_CPU and integrated GPU on single die
*/
typedef enum {
UNKNOWN = 0,
AMD_GPU,
AMD_CPU,
NON_AMD_GPU,
NON_AMD_CPU,
AMD_CPU_CORE,
AMD_APU
AMDSMI_PROCESSOR_TYPE_UNKNOWN = 0,
AMDSMI_PROCESSOR_TYPE_AMD_GPU,
AMDSMI_PROCESSOR_TYPE_AMD_CPU,
AMDSMI_PROCESSOR_TYPE_NON_AMD_GPU,
AMDSMI_PROCESSOR_TYPE_NON_AMD_CPU,
AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE,
AMDSMI_PROCESSOR_TYPE_AMD_APU
} processor_type_t;
/**
@@ -256,23 +256,23 @@ typedef enum {
} amdsmi_status_t;
/**
* Clock types
* @brief Clock types
*/
typedef enum {
CLK_TYPE_SYS = 0x0, //!< System clock
CLK_TYPE_FIRST = CLK_TYPE_SYS,
CLK_TYPE_GFX = CLK_TYPE_SYS,
CLK_TYPE_DF, //!< Data Fabric clock (for ASICs
//!< running on a separate clock)
CLK_TYPE_DCEF, //!< Display Controller Engine clock
CLK_TYPE_SOC,
CLK_TYPE_MEM,
CLK_TYPE_PCIE,
CLK_TYPE_VCLK0,
CLK_TYPE_VCLK1,
CLK_TYPE_DCLK0,
CLK_TYPE_DCLK1,
CLK_TYPE__MAX = CLK_TYPE_DCLK1
AMDSMI_CLK_TYPE_SYS = 0x0, //!< System clock
AMDSMI_CLK_TYPE_FIRST = AMDSMI_CLK_TYPE_SYS,
AMDSMI_CLK_TYPE_GFX = AMDSMI_CLK_TYPE_SYS,
AMDSMI_CLK_TYPE_DF, //!< Data Fabric clock (for ASICs
//!< running on a separate clock)
AMDSMI_CLK_TYPE_DCEF, //!< Display Controller Engine clock
AMDSMI_CLK_TYPE_SOC,
AMDSMI_CLK_TYPE_MEM,
AMDSMI_CLK_TYPE_PCIE,
AMDSMI_CLK_TYPE_VCLK0,
AMDSMI_CLK_TYPE_VCLK1,
AMDSMI_CLK_TYPE_DCLK0,
AMDSMI_CLK_TYPE_DCLK1,
AMDSMI_CLK_TYPE__MAX = AMDSMI_CLK_TYPE_DCLK1
} amdsmi_clk_type_t;
/**
@@ -280,16 +280,16 @@ typedef enum {
* various compute partitioning settings.
*/
typedef enum {
COMPUTE_PARTITION_INVALID = 0,
COMPUTE_PARTITION_CPX, //!< Core mode (CPX)- Per-chip XCC with
AMDSMI_COMPUTE_PARTITION_INVALID = 0,
AMDSMI_COMPUTE_PARTITION_CPX, //!< Core mode (CPX)- Per-chip XCC with
//!< shared memory
COMPUTE_PARTITION_SPX, //!< Single GPU mode (SPX)- All XCCs work
AMDSMI_COMPUTE_PARTITION_SPX, //!< Single GPU mode (SPX)- All XCCs work
//!< together with shared memory
COMPUTE_PARTITION_DPX, //!< Dual GPU mode (DPX)- Half XCCs work
AMDSMI_COMPUTE_PARTITION_DPX, //!< Dual GPU mode (DPX)- Half XCCs work
//!< together with shared memory
COMPUTE_PARTITION_TPX, //!< Triple GPU mode (TPX)- One-third XCCs
AMDSMI_COMPUTE_PARTITION_TPX, //!< Triple GPU mode (TPX)- One-third XCCs
//!< work together with shared memory
COMPUTE_PARTITION_QPX //!< Quad GPU mode (QPX)- Quarter XCCs
AMDSMI_COMPUTE_PARTITION_QPX //!< Quad GPU mode (QPX)- Quarter XCCs
//!< work together with shared memory
} amdsmi_compute_partition_type_t;
@@ -298,16 +298,16 @@ typedef enum {
* memory partition types.
*/
typedef enum {
MEMORY_PARTITION_UNKNOWN = 0,
MEMORY_PARTITION_NPS1, //!< NPS1 - All CCD & XCD data is interleaved
AMDSMI_MEMORY_PARTITION_UNKNOWN = 0,
AMDSMI_MEMORY_PARTITION_NPS1, //!< NPS1 - All CCD & XCD data is interleaved
//!< accross all 8 HBM stacks (all stacks/1).
MEMORY_PARTITION_NPS2, //!< NPS2 - 2 sets of CCDs or 4 XCD interleaved
AMDSMI_MEMORY_PARTITION_NPS2, //!< NPS2 - 2 sets of CCDs or 4 XCD interleaved
//!< accross the 4 HBM stacks per AID pair
//!< (8 stacks/2).
MEMORY_PARTITION_NPS4, //!< NPS4 - Each XCD data is interleaved accross
AMDSMI_MEMORY_PARTITION_NPS4, //!< NPS4 - Each XCD data is interleaved accross
//!< accross 2 (or single) HBM stacks
//!< (8 stacks/8 or 8 stacks/4).
MEMORY_PARTITION_NPS8, //!< NPS8 - Each XCD uses a single HBM stack
AMDSMI_MEMORY_PARTITION_NPS8, //!< NPS8 - Each XCD uses a single HBM stack
//!< (8 stacks/8). Or each XCD uses a single
//!< HBM stack & CCDs share 2 non-interleaved
//!< HBM stacks on its AID
@@ -319,17 +319,17 @@ typedef enum {
* temperature reading should be obtained.
*/
typedef enum {
TEMPERATURE_TYPE_EDGE,
TEMPERATURE_TYPE_FIRST = TEMPERATURE_TYPE_EDGE,
TEMPERATURE_TYPE_HOTSPOT,
TEMPERATURE_TYPE_JUNCTION = TEMPERATURE_TYPE_HOTSPOT,
TEMPERATURE_TYPE_VRAM,
TEMPERATURE_TYPE_HBM_0,
TEMPERATURE_TYPE_HBM_1,
TEMPERATURE_TYPE_HBM_2,
TEMPERATURE_TYPE_HBM_3,
TEMPERATURE_TYPE_PLX,
TEMPERATURE_TYPE__MAX = TEMPERATURE_TYPE_PLX
AMDSMI_TEMPERATURE_TYPE_EDGE,
AMDSMI_TEMPERATURE_TYPE_FIRST = AMDSMI_TEMPERATURE_TYPE_EDGE,
AMDSMI_TEMPERATURE_TYPE_HOTSPOT,
AMDSMI_TEMPERATURE_TYPE_JUNCTION = AMDSMI_TEMPERATURE_TYPE_HOTSPOT,
AMDSMI_TEMPERATURE_TYPE_VRAM,
AMDSMI_TEMPERATURE_TYPE_HBM_0,
AMDSMI_TEMPERATURE_TYPE_HBM_1,
AMDSMI_TEMPERATURE_TYPE_HBM_2,
AMDSMI_TEMPERATURE_TYPE_HBM_3,
AMDSMI_TEMPERATURE_TYPE_PLX,
AMDSMI_TEMPERATURE_TYPE__MAX = AMDSMI_TEMPERATURE_TYPE_PLX
} amdsmi_temperature_type_t;
/**
@@ -337,101 +337,101 @@ typedef enum {
* blocks.
*/
typedef enum {
FW_ID_SMU = 1,
FW_ID_FIRST = FW_ID_SMU,
FW_ID_CP_CE,
FW_ID_CP_PFP,
FW_ID_CP_ME,
FW_ID_CP_MEC_JT1,
FW_ID_CP_MEC_JT2,
FW_ID_CP_MEC1,
FW_ID_CP_MEC2,
FW_ID_RLC,
FW_ID_SDMA0,
FW_ID_SDMA1,
FW_ID_SDMA2,
FW_ID_SDMA3,
FW_ID_SDMA4,
FW_ID_SDMA5,
FW_ID_SDMA6,
FW_ID_SDMA7,
FW_ID_VCN,
FW_ID_UVD,
FW_ID_VCE,
FW_ID_ISP,
FW_ID_DMCU_ERAM, /*eRAM*/
FW_ID_DMCU_ISR, /*ISR*/
FW_ID_RLC_RESTORE_LIST_GPM_MEM,
FW_ID_RLC_RESTORE_LIST_SRM_MEM,
FW_ID_RLC_RESTORE_LIST_CNTL,
FW_ID_RLC_V,
FW_ID_MMSCH,
FW_ID_PSP_SYSDRV,
FW_ID_PSP_SOSDRV,
FW_ID_PSP_TOC,
FW_ID_PSP_KEYDB,
FW_ID_DFC,
FW_ID_PSP_SPL,
FW_ID_DRV_CAP,
FW_ID_MC,
FW_ID_PSP_BL,
FW_ID_CP_PM4,
FW_ID_RLC_P,
FW_ID_SEC_POLICY_STAGE2,
FW_ID_REG_ACCESS_WHITELIST,
FW_ID_IMU_DRAM,
FW_ID_IMU_IRAM,
FW_ID_SDMA_TH0,
FW_ID_SDMA_TH1,
FW_ID_CP_MES,
FW_ID_MES_KIQ,
FW_ID_MES_STACK,
FW_ID_MES_THREAD1,
FW_ID_MES_THREAD1_STACK,
FW_ID_RLX6,
FW_ID_RLX6_DRAM_BOOT,
FW_ID_RS64_ME,
FW_ID_RS64_ME_P0_DATA,
FW_ID_RS64_ME_P1_DATA,
FW_ID_RS64_PFP,
FW_ID_RS64_PFP_P0_DATA,
FW_ID_RS64_PFP_P1_DATA,
FW_ID_RS64_MEC,
FW_ID_RS64_MEC_P0_DATA,
FW_ID_RS64_MEC_P1_DATA,
FW_ID_RS64_MEC_P2_DATA,
FW_ID_RS64_MEC_P3_DATA,
FW_ID_PPTABLE,
FW_ID_PSP_SOC,
FW_ID_PSP_DBG,
FW_ID_PSP_INTF,
FW_ID_RLX6_CORE1,
FW_ID_RLX6_DRAM_BOOT_CORE1,
FW_ID_RLCV_LX7,
FW_ID_RLC_SAVE_RESTORE_LIST,
FW_ID_ASD,
FW_ID_TA_RAS,
FW_ID_TA_XGMI,
FW_ID_RLC_SRLG,
FW_ID_RLC_SRLS,
FW_ID_PM,
FW_ID_DMCU,
FW_ID__MAX
AMDSMI_FW_ID_SMU = 1,
AMDSMI_FW_ID_FIRST = AMDSMI_FW_ID_SMU,
AMDSMI_FW_ID_CP_CE,
AMDSMI_FW_ID_CP_PFP,
AMDSMI_FW_ID_CP_ME,
AMDSMI_FW_ID_CP_MEC_JT1,
AMDSMI_FW_ID_CP_MEC_JT2,
AMDSMI_FW_ID_CP_MEC1,
AMDSMI_FW_ID_CP_MEC2,
AMDSMI_FW_ID_RLC,
AMDSMI_FW_ID_SDMA0,
AMDSMI_FW_ID_SDMA1,
AMDSMI_FW_ID_SDMA2,
AMDSMI_FW_ID_SDMA3,
AMDSMI_FW_ID_SDMA4,
AMDSMI_FW_ID_SDMA5,
AMDSMI_FW_ID_SDMA6,
AMDSMI_FW_ID_SDMA7,
AMDSMI_FW_ID_VCN,
AMDSMI_FW_ID_UVD,
AMDSMI_FW_ID_VCE,
AMDSMI_FW_ID_ISP,
AMDSMI_FW_ID_DMCU_ERAM, /*eRAM*/
AMDSMI_FW_ID_DMCU_ISR, /*ISR*/
AMDSMI_FW_ID_RLC_RESTORE_LIST_GPM_MEM,
AMDSMI_FW_ID_RLC_RESTORE_LIST_SRM_MEM,
AMDSMI_FW_ID_RLC_RESTORE_LIST_CNTL,
AMDSMI_FW_ID_RLC_V,
AMDSMI_FW_ID_MMSCH,
AMDSMI_FW_ID_PSP_SYSDRV,
AMDSMI_FW_ID_PSP_SOSDRV,
AMDSMI_FW_ID_PSP_TOC,
AMDSMI_FW_ID_PSP_KEYDB,
AMDSMI_FW_ID_DFC,
AMDSMI_FW_ID_PSP_SPL,
AMDSMI_FW_ID_DRV_CAP,
AMDSMI_FW_ID_MC,
AMDSMI_FW_ID_PSP_BL,
AMDSMI_FW_ID_CP_PM4,
AMDSMI_FW_ID_RLC_P,
AMDSMI_FW_ID_SEC_POLICY_STAGE2,
AMDSMI_FW_ID_REG_ACCESS_WHITELIST,
AMDSMI_FW_ID_IMU_DRAM,
AMDSMI_FW_ID_IMU_IRAM,
AMDSMI_FW_ID_SDMA_TH0,
AMDSMI_FW_ID_SDMA_TH1,
AMDSMI_FW_ID_CP_MES,
AMDSMI_FW_ID_MES_KIQ,
AMDSMI_FW_ID_MES_STACK,
AMDSMI_FW_ID_MES_THREAD1,
AMDSMI_FW_ID_MES_THREAD1_STACK,
AMDSMI_FW_ID_RLX6,
AMDSMI_FW_ID_RLX6_DRAM_BOOT,
AMDSMI_FW_ID_RS64_ME,
AMDSMI_FW_ID_RS64_ME_P0_DATA,
AMDSMI_FW_ID_RS64_ME_P1_DATA,
AMDSMI_FW_ID_RS64_PFP,
AMDSMI_FW_ID_RS64_PFP_P0_DATA,
AMDSMI_FW_ID_RS64_PFP_P1_DATA,
AMDSMI_FW_ID_RS64_MEC,
AMDSMI_FW_ID_RS64_MEC_P0_DATA,
AMDSMI_FW_ID_RS64_MEC_P1_DATA,
AMDSMI_FW_ID_RS64_MEC_P2_DATA,
AMDSMI_FW_ID_RS64_MEC_P3_DATA,
AMDSMI_FW_ID_PPTABLE,
AMDSMI_FW_ID_PSP_SOC,
AMDSMI_FW_ID_PSP_DBG,
AMDSMI_FW_ID_PSP_INTF,
AMDSMI_FW_ID_RLX6_CORE1,
AMDSMI_FW_ID_RLX6_DRAM_BOOT_CORE1,
AMDSMI_FW_ID_RLCV_LX7,
AMDSMI_FW_ID_RLC_SAVE_RESTORE_LIST,
AMDSMI_FW_ID_ASD,
AMDSMI_FW_ID_TA_RAS,
AMDSMI_FW_ID_TA_XGMI,
AMDSMI_FW_ID_RLC_SRLG,
AMDSMI_FW_ID_RLC_SRLS,
AMDSMI_FW_ID_PM,
AMDSMI_FW_ID_DMCU,
AMDSMI_FW_ID__MAX
} amdsmi_fw_block_t;
typedef enum {
VRAM_TYPE_UNKNOWN = 0,
VRAM_TYPE_GDDR1 = 1,
VRAM_TYPE_DDR2 = 2,
VRAM_TYPE_GDDR3 = 3,
VRAM_TYPE_GDDR4 = 4,
VRAM_TYPE_GDDR5 = 5,
VRAM_TYPE_HBM = 6,
VRAM_TYPE_DDR3 = 7,
VRAM_TYPE_DDR4 = 8,
VRAM_TYPE_GDDR6 = 9,
VRAM_TYPE__MAX = VRAM_TYPE_GDDR6
AMDSMI_VRAM_TYPE_UNKNOWN = 0,
AMDSMI_VRAM_TYPE_GDDR1 = 1,
AMDSMI_VRAM_TYPE_DDR2 = 2,
AMDSMI_VRAM_TYPE_GDDR3 = 3,
AMDSMI_VRAM_TYPE_GDDR4 = 4,
AMDSMI_VRAM_TYPE_GDDR5 = 5,
AMDSMI_VRAM_TYPE_HBM = 6,
AMDSMI_VRAM_TYPE_DDR3 = 7,
AMDSMI_VRAM_TYPE_DDR4 = 8,
AMDSMI_VRAM_TYPE_GDDR6 = 9,
AMDSMI_VRAM_TYPE__MAX = AMDSMI_VRAM_TYPE_GDDR6
} amdsmi_vram_type_t;
typedef enum {
@@ -483,12 +483,12 @@ typedef struct {
} amdsmi_frequency_range_t;
typedef union {
struct fields_ {
struct {
uint64_t function_number : 3;
uint64_t device_number : 5;
uint64_t bus_number : 8;
uint64_t domain_number : 48;
} fields;
};
uint64_t as_uint;
} amdsmi_bdf_t;
@@ -568,7 +568,7 @@ typedef struct {
amdsmi_fw_block_t fw_id;
uint64_t fw_version;
uint64_t reserved[2];
} fw_info_list[FW_ID__MAX];
} fw_info_list[AMDSMI_FW_ID__MAX];
uint32_t reserved[7];
} amdsmi_fw_info_t;
@@ -608,7 +608,8 @@ typedef struct {
typedef struct {
amdsmi_vram_type_t vram_type;
amdsmi_vram_vendor_type_t vram_vendor;
uint64_t vram_size_mb;
uint64_t vram_size;
uint64_t reserved[6];
} amdsmi_vram_info_t;
@@ -638,10 +639,11 @@ typedef struct {
} amdsmi_power_info_t;
typedef struct {
uint32_t cur_clk;
uint32_t clk;
uint32_t min_clk;
uint32_t max_clk;
uint32_t sleep_clk;
uint8_t clk_locked;
uint8_t clk_deep_sleep;
uint32_t reserved[4];
} amdsmi_clk_info_t;
include/amd_smi/impl/amd_smi_gpu_device.h
+2 -2
View File
@@ -69,10 +69,10 @@ class AMDSmiGPUDevice: public AMDSmiProcessor {
public:
AMDSmiGPUDevice(uint32_t gpu_id, uint32_t fd, std::string path, amdsmi_bdf_t bdf, AMDSmiDrm& drm):
AMDSmiProcessor(AMD_GPU), gpu_id_(gpu_id), fd_(fd), path_(path), bdf_(bdf), drm_(drm) {}
AMDSmiProcessor(AMDSMI_PROCESSOR_TYPE_AMD_GPU), gpu_id_(gpu_id), fd_(fd), path_(path), bdf_(bdf), drm_(drm) {}
AMDSmiGPUDevice(uint32_t gpu_id, AMDSmiDrm& drm):
AMDSmiProcessor(AMD_GPU), gpu_id_(gpu_id), drm_(drm) {
AMDSmiProcessor(AMDSMI_PROCESSOR_TYPE_AMD_GPU), gpu_id_(gpu_id), drm_(drm) {
if (check_if_drm_is_supported()) this->get_drm_data();
}
~AMDSmiGPUDevice() {
include/amd_smi/impl/amd_smi_socket.h
+6 -6
View File
@@ -62,13 +62,13 @@ class AMDSmiSocket {
uint32_t get_socket_index() { return sindex_;}
void add_processor(AMDSmiProcessor* processor) {
switch (processor->get_processor_type()) {
case AMD_GPU:
case AMDSMI_PROCESSOR_TYPE_AMD_GPU:
processors_.push_back(processor);
break;
case AMD_CPU:
case AMDSMI_PROCESSOR_TYPE_AMD_CPU:
cpu_processors_.push_back(processor);
break;
case AMD_CPU_CORE:
case AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE:
cpu_core_processors_.push_back(processor);
break;
default:
@@ -78,11 +78,11 @@ class AMDSmiSocket {
std::vector<AMDSmiProcessor*>& get_processors() { return processors_;}
std::vector<AMDSmiProcessor*>& get_processors(processor_type_t type) {
switch (type) {
case AMD_GPU:
case AMDSMI_PROCESSOR_TYPE_AMD_GPU:
return processors_;
case AMD_CPU:
case AMDSMI_PROCESSOR_TYPE_AMD_CPU:
return cpu_processors_;
case AMD_CPU_CORE:
case AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE:
return cpu_core_processors_;
default:
return processors_;
py-interface/README.md
+9 -5
View File
@@ -461,7 +461,7 @@ Field | Description
---|---
`vram_type` | vram type
`vram_vendor` | vram vendor
`vram_size_mb` | vram size in mb
`vram_size` | vram size in mb
Exceptions that can be thrown by `amdsmi_get_gpu_vram_info` function:
@@ -481,7 +481,7 @@ try:
vram_info = amdsmi_get_gpu_vram_info(device)
print(vram_info['vram_type'])
print(vram_info['vram_vendor'])
print(vram_info['vram_size_mb'])
print(vram_info['vram_size'])
except AmdSmiException as e:
print(e)
```
@@ -769,9 +769,11 @@ Output: Dictionary with fields
Field | Description
---|---
`cur_clk` | Current clock for given clock type
`max_clk` | Maximum clock for given clock type
`clk` | Current clock for given clock type
`min_clk` | Minimum clock for given clock type
`max_clk` | Maximum clock for given clock type
`clk_locked` | flag only supported on GFX clock domain
`clk_deep_sleep` | clock deep sleep mode flag
Exceptions that can be thrown by `amdsmi_get_clock_info` function:
@@ -789,9 +791,11 @@ try:
else:
for device in devices:
clock_measure = amdsmi_get_clock_info(device, AmdSmiClkType.GFX)
print(clock_measure['cur_clk'])
print(clock_measure['clk'])
print(clock_measure['min_clk'])
print(clock_measure['max_clk'])
print(clock_measure['clk_locked'])
print(clock_measure['clk_deep_sleep'])
except AmdSmiException as e:
print(e)
```
py-interface/amdsmi_interface.py
+140 -139
View File
@@ -82,16 +82,16 @@ class AmdSmiInitFlags(IntEnum):
class AmdSmiContainerTypes(IntEnum):
LXC = amdsmi_wrapper.CONTAINER_LXC
DOCKER = amdsmi_wrapper.CONTAINER_DOCKER
LXC = amdsmi_wrapper.AMDSMI_CONTAINER_LXC
DOCKER = amdsmi_wrapper.AMDSMI_CONTAINER_DOCKER
class AmdSmiDeviceType(IntEnum):
UNKNOWN_DEVICE = amdsmi_wrapper.UNKNOWN
AMD_GPU_DEVICE = amdsmi_wrapper.AMD_GPU
AMD_CPU_DEVICE = amdsmi_wrapper.AMD_CPU
NON_AMD_GPU_DEVICE = amdsmi_wrapper.NON_AMD_GPU
NON_AMD_CPU_DEVICE = amdsmi_wrapper.NON_AMD_CPU
AMD_GPU_DEVICE = amdsmi_wrapper.AMDSMI_PROCESSOR_TYPE_AMD_GPU
AMD_CPU_DEVICE = amdsmi_wrapper.AMDSMI_PROCESSOR_TYPE_AMD_CPU
NON_AMD_GPU_DEVICE = amdsmi_wrapper.AMDSMI_PROCESSOR_TYPE_NON_AMD_GPU
NON_AMD_CPU_DEVICE = amdsmi_wrapper.AMDSMI_PROCESSOR_TYPE_NON_AMD_CPU
class AmdSmiMmIp(IntEnum):
@@ -101,109 +101,109 @@ class AmdSmiMmIp(IntEnum):
class AmdSmiFwBlock(IntEnum):
FW_ID_SMU = amdsmi_wrapper.FW_ID_SMU
FW_ID_CP_CE = amdsmi_wrapper.FW_ID_CP_CE
FW_ID_CP_PFP = amdsmi_wrapper.FW_ID_CP_PFP
FW_ID_CP_ME = amdsmi_wrapper.FW_ID_CP_ME
FW_ID_CP_MEC_JT1 = amdsmi_wrapper.FW_ID_CP_MEC_JT1
FW_ID_CP_MEC_JT2 = amdsmi_wrapper.FW_ID_CP_MEC_JT2
FW_ID_CP_MEC1 = amdsmi_wrapper.FW_ID_CP_MEC1
FW_ID_CP_MEC2 = amdsmi_wrapper.FW_ID_CP_MEC2
FW_ID_RLC = amdsmi_wrapper.FW_ID_RLC
FW_ID_SDMA0 = amdsmi_wrapper.FW_ID_SDMA0
FW_ID_SDMA1 = amdsmi_wrapper.FW_ID_SDMA1
FW_ID_SDMA2 = amdsmi_wrapper.FW_ID_SDMA2
FW_ID_SDMA3 = amdsmi_wrapper.FW_ID_SDMA3
FW_ID_SDMA4 = amdsmi_wrapper.FW_ID_SDMA4
FW_ID_SDMA5 = amdsmi_wrapper.FW_ID_SDMA5
FW_ID_SDMA6 = amdsmi_wrapper.FW_ID_SDMA6
FW_ID_SDMA7 = amdsmi_wrapper.FW_ID_SDMA7
FW_ID_VCN = amdsmi_wrapper.FW_ID_VCN
FW_ID_UVD = amdsmi_wrapper.FW_ID_UVD
FW_ID_VCE = amdsmi_wrapper.FW_ID_VCE
FW_ID_ISP = amdsmi_wrapper.FW_ID_ISP
FW_ID_DMCU_ERAM = amdsmi_wrapper.FW_ID_DMCU_ERAM
FW_ID_DMCU_ISR = amdsmi_wrapper.FW_ID_DMCU_ISR
FW_ID_RLC_RESTORE_LIST_GPM_MEM = amdsmi_wrapper.FW_ID_RLC_RESTORE_LIST_GPM_MEM
FW_ID_RLC_RESTORE_LIST_SRM_MEM = amdsmi_wrapper.FW_ID_RLC_RESTORE_LIST_SRM_MEM
FW_ID_RLC_RESTORE_LIST_CNTL = amdsmi_wrapper.FW_ID_RLC_RESTORE_LIST_CNTL
FW_ID_RLC_V = amdsmi_wrapper.FW_ID_RLC_V
FW_ID_MMSCH = amdsmi_wrapper.FW_ID_MMSCH
FW_ID_PSP_SYSDRV = amdsmi_wrapper.FW_ID_PSP_SYSDRV
FW_ID_PSP_SOSDRV = amdsmi_wrapper.FW_ID_PSP_SOSDRV
FW_ID_PSP_TOC = amdsmi_wrapper.FW_ID_PSP_TOC
FW_ID_PSP_KEYDB = amdsmi_wrapper.FW_ID_PSP_KEYDB
FW_ID_DFC = amdsmi_wrapper.FW_ID_DFC
FW_ID_PSP_SPL = amdsmi_wrapper.FW_ID_PSP_SPL
FW_ID_DRV_CAP = amdsmi_wrapper.FW_ID_DRV_CAP
FW_ID_MC = amdsmi_wrapper.FW_ID_MC
FW_ID_PSP_BL = amdsmi_wrapper.FW_ID_PSP_BL
FW_ID_CP_PM4 = amdsmi_wrapper.FW_ID_CP_PM4
FW_ID_RLC_P = amdsmi_wrapper.FW_ID_RLC_P
FW_ID_SEC_POLICY_STAGE2 = amdsmi_wrapper.FW_ID_SEC_POLICY_STAGE2
FW_ID_REG_ACCESS_WHITELIST = amdsmi_wrapper.FW_ID_REG_ACCESS_WHITELIST
FW_ID_IMU_DRAM = amdsmi_wrapper.FW_ID_IMU_DRAM
FW_ID_IMU_IRAM = amdsmi_wrapper.FW_ID_IMU_IRAM
FW_ID_SDMA_TH0 = amdsmi_wrapper.FW_ID_SDMA_TH0
FW_ID_SDMA_TH1 = amdsmi_wrapper.FW_ID_SDMA_TH1
FW_ID_CP_MES = amdsmi_wrapper.FW_ID_CP_MES
FW_ID_MES_STACK = amdsmi_wrapper.FW_ID_MES_STACK
FW_ID_MES_THREAD1 = amdsmi_wrapper.FW_ID_MES_THREAD1
FW_ID_MES_THREAD1_STACK = amdsmi_wrapper.FW_ID_MES_THREAD1_STACK
FW_ID_RLX6 = amdsmi_wrapper.FW_ID_RLX6
FW_ID_RLX6_DRAM_BOOT = amdsmi_wrapper.FW_ID_RLX6_DRAM_BOOT
FW_ID_RS64_ME = amdsmi_wrapper.FW_ID_RS64_ME
FW_ID_RS64_ME_P0_DATA = amdsmi_wrapper.FW_ID_RS64_ME_P0_DATA
FW_ID_RS64_ME_P1_DATA = amdsmi_wrapper.FW_ID_RS64_ME_P1_DATA
FW_ID_RS64_PFP = amdsmi_wrapper.FW_ID_RS64_PFP
FW_ID_RS64_PFP_P0_DATA = amdsmi_wrapper.FW_ID_RS64_PFP_P0_DATA
FW_ID_RS64_PFP_P1_DATA = amdsmi_wrapper.FW_ID_RS64_PFP_P1_DATA
FW_ID_RS64_MEC = amdsmi_wrapper.FW_ID_RS64_MEC
FW_ID_RS64_MEC_P0_DATA = amdsmi_wrapper.FW_ID_RS64_MEC_P0_DATA
FW_ID_RS64_MEC_P1_DATA = amdsmi_wrapper.FW_ID_RS64_MEC_P1_DATA
FW_ID_RS64_MEC_P2_DATA = amdsmi_wrapper.FW_ID_RS64_MEC_P2_DATA
FW_ID_RS64_MEC_P3_DATA = amdsmi_wrapper.FW_ID_RS64_MEC_P3_DATA
FW_ID_PPTABLE = amdsmi_wrapper.FW_ID_PPTABLE
FW_ID_PSP_SOC = amdsmi_wrapper.FW_ID_PSP_SOC
FW_ID_PSP_DBG = amdsmi_wrapper.FW_ID_PSP_DBG
FW_ID_PSP_INTF = amdsmi_wrapper.FW_ID_PSP_INTF
FW_ID_RLX6_CORE1 = amdsmi_wrapper.FW_ID_RLX6_CORE1
FW_ID_RLX6_DRAM_BOOT_CORE1 = amdsmi_wrapper.FW_ID_RLX6_DRAM_BOOT_CORE1
FW_ID_RLCV_LX7 = amdsmi_wrapper.FW_ID_RLCV_LX7
FW_ID_RLC_SAVE_RESTORE_LIST = amdsmi_wrapper.FW_ID_RLC_SAVE_RESTORE_LIST
FW_ID_ASD = amdsmi_wrapper.FW_ID_ASD
FW_ID_TA_RAS = amdsmi_wrapper.FW_ID_TA_RAS
FW_ID_TA_XGMI = amdsmi_wrapper.FW_ID_TA_XGMI
FW_ID_RLC_SRLG = amdsmi_wrapper.FW_ID_RLC_SRLG
FW_ID_RLC_SRLS = amdsmi_wrapper.FW_ID_RLC_SRLS
FW_ID_PM = amdsmi_wrapper.FW_ID_PM
FW_ID_DMCU = amdsmi_wrapper.FW_ID_DMCU
AMDSMI_FW_ID_SMU = amdsmi_wrapper.AMDSMI_FW_ID_SMU
AMDSMI_FW_ID_CP_CE = amdsmi_wrapper.AMDSMI_FW_ID_CP_CE
AMDSMI_FW_ID_CP_PFP = amdsmi_wrapper.AMDSMI_FW_ID_CP_PFP
AMDSMI_FW_ID_CP_ME = amdsmi_wrapper.AMDSMI_FW_ID_CP_ME
AMDSMI_FW_ID_CP_MEC_JT1 = amdsmi_wrapper.AMDSMI_FW_ID_CP_MEC_JT1
AMDSMI_FW_ID_CP_MEC_JT2 = amdsmi_wrapper.AMDSMI_FW_ID_CP_MEC_JT2
AMDSMI_FW_ID_CP_MEC1 = amdsmi_wrapper.AMDSMI_FW_ID_CP_MEC1
AMDSMI_FW_ID_CP_MEC2 = amdsmi_wrapper.AMDSMI_FW_ID_CP_MEC2
AMDSMI_FW_ID_RLC = amdsmi_wrapper.AMDSMI_FW_ID_RLC
AMDSMI_FW_ID_SDMA0 = amdsmi_wrapper.AMDSMI_FW_ID_SDMA0
AMDSMI_FW_ID_SDMA1 = amdsmi_wrapper.AMDSMI_FW_ID_SDMA1
AMDSMI_FW_ID_SDMA2 = amdsmi_wrapper.AMDSMI_FW_ID_SDMA2
AMDSMI_FW_ID_SDMA3 = amdsmi_wrapper.AMDSMI_FW_ID_SDMA3
AMDSMI_FW_ID_SDMA4 = amdsmi_wrapper.AMDSMI_FW_ID_SDMA4
AMDSMI_FW_ID_SDMA5 = amdsmi_wrapper.AMDSMI_FW_ID_SDMA5
AMDSMI_FW_ID_SDMA6 = amdsmi_wrapper.AMDSMI_FW_ID_SDMA6
AMDSMI_FW_ID_SDMA7 = amdsmi_wrapper.AMDSMI_FW_ID_SDMA7
AMDSMI_FW_ID_VCN = amdsmi_wrapper.AMDSMI_FW_ID_VCN
AMDSMI_FW_ID_UVD = amdsmi_wrapper.AMDSMI_FW_ID_UVD
AMDSMI_FW_ID_VCE = amdsmi_wrapper.AMDSMI_FW_ID_VCE
AMDSMI_ FW_ID_ISP = amdsmi_wrapper.AMDSMI_ FW_ID_ISP
AMDSMI_FW_ID_DMCU_ERAM = amdsmi_wrapper.AMDSMI_FW_ID_DMCU_ERAM
AMDSMI_FW_ID_DMCU_ISR = amdsmi_wrapper.AMDSMI_FW_ID_DMCU_ISR
AMDSMI_FW_ID_RLC_RESTORE_LIST_GPM_MEM = amdsmi_wrapper.AMDSMI_FW_ID_RLC_RESTORE_LIST_GPM_MEM
AMDSMI_FW_ID_RLC_RESTORE_LIST_SRM_MEM = amdsmi_wrapper.AMDSMI_FW_ID_RLC_RESTORE_LIST_SRM_MEM
AMDSMI_FW_ID_RLC_RESTORE_LIST_CNTL = amdsmi_wrapper.AMDSMI_FW_ID_RLC_RESTORE_LIST_CNTL
AMDSMI_FW_ID_RLC_V = amdsmi_wrapper.AMDSMI_FW_ID_RLC_V
AMDSMI_FW_ID_MMSCH = amdsmi_wrapper.AMDSMI_FW_ID_MMSCH
AMDSMI_FW_ID_PSP_SYSDRV = amdsmi_wrapper.AMDSMI_FW_ID_PSP_SYSDRV
AMDSMI_FW_ID_PSP_SOSDRV = amdsmi_wrapper.AMDSMI_FW_ID_PSP_SOSDRV
AMDSMI_FW_ID_PSP_TOC = amdsmi_wrapper.AMDSMI_FW_ID_PSP_TOC
AMDSMI_FW_ID_PSP_KEYDB = amdsmi_wrapper.AMDSMI_FW_ID_PSP_KEYDB
AMDSMI_FW_ID_DFC = amdsmi_wrapper.AMDSMI_FW_ID_DFC
AMDSMI_FW_ID_PSP_SPL = amdsmi_wrapper.AMDSMI_FW_ID_PSP_SPL
AMDSMI_FW_ID_DRV_CAP = amdsmi_wrapper.AMDSMI_FW_ID_DRV_CAP
AMDSMI_FW_ID_MC = amdsmi_wrapper.AMDSMI_FW_ID_MC
AMDSMI_FW_ID_PSP_BL = amdsmi_wrapper.AMDSMI_FW_ID_PSP_BL
AMDSMI_FW_ID_CP_PM4 = amdsmi_wrapper.AMDSMI_FW_ID_CP_PM4
AMDSMI_FW_ID_RLC_P = amdsmi_wrapper.AMDSMI_FW_ID_RLC_P
AMDSMI_FW_ID_SEC_POLICY_STAGE2 = amdsmi_wrapper.AMDSMI_FW_ID_SEC_POLICY_STAGE2
AMDSMI_FW_ID_REG_ACCESS_WHITELIST = amdsmi_wrapper.AMDSMI_FW_ID_REG_ACCESS_WHITELIST
AMDSMI_FW_ID_IMU_DRAM = amdsmi_wrapper.AMDSMI_FW_ID_IMU_DRAM
AMDSMI_FW_ID_IMU_IRAM = amdsmi_wrapper.AMDSMI_FW_ID_IMU_IRAM
AMDSMI_FW_ID_SDMA_TH0 = amdsmi_wrapper.AMDSMI_FW_ID_SDMA_TH0
AMDSMI_FW_ID_SDMA_TH1 = amdsmi_wrapper.AMDSMI_FW_ID_SDMA_TH1
AMDSMI_FW_ID_CP_MES = amdsmi_wrapper.AMDSMI_FW_ID_CP_MES
AMDSMI_FW_ID_MES_STACK = amdsmi_wrapper.AMDSMI_FW_ID_MES_STACK
AMDSMI_FW_ID_MES_THREAD1 = amdsmi_wrapper.AMDSMI_FW_ID_MES_THREAD1
AMDSMI_FW_ID_MES_THREAD1_STACK = amdsmi_wrapper.AMDSMI_FW_ID_MES_THREAD1_STACK
AMDSMI_FW_ID_RLX6 = amdsmi_wrapper.AMDSMI_FW_ID_RLX6
AMDSMI_FW_ID_RLX6_DRAM_BOOT = amdsmi_wrapper.AMDSMI_FW_ID_RLX6_DRAM_BOOT
AMDSMI_FW_ID_RS64_ME = amdsmi_wrapper.AMDSMI_FW_ID_RS64_ME
AMDSMI_FW_ID_RS64_ME_P0_DATA = amdsmi_wrapper.AMDSMI_FW_ID_RS64_ME_P0_DATA
AMDSMI_FW_ID_RS64_ME_P1_DATA = amdsmi_wrapper.AMDSMI_FW_ID_RS64_ME_P1_DATA
AMDSMI_FW_ID_RS64_PFP = amdsmi_wrapper.AMDSMI_FW_ID_RS64_PFP
AMDSMI_FW_ID_RS64_PFP_P0_DATA = amdsmi_wrapper.AMDSMI_FW_ID_RS64_PFP_P0_DATA
AMDSMI_FW_ID_RS64_PFP_P1_DATA = amdsmi_wrapper.AMDSMI_FW_ID_RS64_PFP_P1_DATA
AMDSMI_FW_ID_RS64_MEC = amdsmi_wrapper.AMDSMI_FW_ID_RS64_MEC
AMDSMI_FW_ID_RS64_MEC_P0_DATA = amdsmi_wrapper.AMDSMI_FW_ID_RS64_MEC_P0_DATA
AMDSMI_FW_ID_RS64_MEC_P1_DATA = amdsmi_wrapper.AMDSMI_FW_ID_RS64_MEC_P1_DATA
AMDSMI_FW_ID_RS64_MEC_P2_DATA = amdsmi_wrapper.AMDSMI_FW_ID_RS64_MEC_P2_DATA
AMDSMI_FW_ID_RS64_MEC_P3_DATA = amdsmi_wrapper.AMDSMI_FW_ID_RS64_MEC_P3_DATA
AMDSMI_FW_ID_PPTABLE = amdsmi_wrapper.AMDSMI_FW_ID_PPTABLE
AMDSMI_FW_ID_PSP_SOC = amdsmi_wrapper.AMDSMI_FW_ID_PSP_SOC
AMDSMI_FW_ID_PSP_DBG = amdsmi_wrapper.AMDSMI_FW_ID_PSP_DBG
AMDSMI_FW_ID_PSP_INTF = amdsmi_wrapper.AMDSMI_FW_ID_PSP_INTF
AMDSMI_FW_ID_RLX6_CORE1 = amdsmi_wrapper.AMDSMI_FW_ID_RLX6_CORE1
AMDSMI_FW_ID_RLX6_DRAM_BOOT_CORE1 = amdsmi_wrapper.AMDSMI_FW_ID_RLX6_DRAM_BOOT_CORE1
AMDSMI_FW_ID_RLCV_LX7 = amdsmi_wrapper.AMDSMI_FW_ID_RLCV_LX7
AMDSMI_FW_ID_RLC_SAVE_RESTORE_LIST = amdsmi_wrapper.AMDSMI_FW_ID_RLC_SAVE_RESTORE_LIST
AMDSMI_FW_ID_ASD = amdsmi_wrapper.AMDSMI_FW_ID_ASD
AMDSMI_FW_ID_TA_RAS = amdsmi_wrapper.AMDSMI_FW_ID_TA_RAS
AMDSMI_FW_ID_TA_XGMI = amdsmi_wrapper.AMDSMI_FW_ID_TA_XGMI
AMDSMI_FW_ID_RLC_SRLG = amdsmi_wrapper.AMDSMI_FW_ID_RLC_SRLG
AMDSMI_FW_ID_RLC_SRLS = amdsmi_wrapper.AMDSMI_FW_ID_RLC_SRLS
AMDSMI_FW_ID_PM = amdsmi_wrapper.AMDSMI_FW_ID_PM
AMDSMI_FW_ID_DMCU = amdsmi_wrapper.AMDSMI_FW_ID_DMCU
class AmdSmiClkType(IntEnum):
SYS = amdsmi_wrapper.CLK_TYPE_SYS
GFX = amdsmi_wrapper.CLK_TYPE_GFX
DF = amdsmi_wrapper.CLK_TYPE_DF
DCEF = amdsmi_wrapper.CLK_TYPE_DCEF
SOC = amdsmi_wrapper.CLK_TYPE_SOC
MEM = amdsmi_wrapper.CLK_TYPE_MEM
PCIE = amdsmi_wrapper.CLK_TYPE_PCIE
VCLK0 = amdsmi_wrapper.CLK_TYPE_VCLK0
VCLK1 = amdsmi_wrapper.CLK_TYPE_VCLK1
DCLK0 = amdsmi_wrapper.CLK_TYPE_DCLK0
DCLK1 = amdsmi_wrapper.CLK_TYPE_DCLK1
SYS = amdsmi_wrapper.AMDSMI_CLK_TYPE_SYS
GFX = amdsmi_wrapper.AMDSMI_CLK_TYPE_GFX
DF = amdsmi_wrapper.AMDSMI_CLK_TYPE_DF
DCEF = amdsmi_wrapper.AMDSMI_CLK_TYPE_DCEF
SOC = amdsmi_wrapper.AMDSMI_CLK_TYPE_SOC
MEM = amdsmi_wrapper.AMDSMI_CLK_TYPE_MEM
PCIE = amdsmi_wrapper.AMDSMI_CLK_TYPE_PCIE
VCLK0 = amdsmi_wrapper.AMDSMI_CLK_TYPE_VCLK0
VCLK1 = amdsmi_wrapper.AMDSMI_CLK_TYPE_VCLK1
DCLK0 = amdsmi_wrapper.AMDSMI_CLK_TYPE_DCLK0
DCLK1 = amdsmi_wrapper.AMDSMI_CLK_TYPE_DCLK1
class AmdSmiTemperatureType(IntEnum):
EDGE = amdsmi_wrapper.TEMPERATURE_TYPE_EDGE
HOTSPOT = amdsmi_wrapper.TEMPERATURE_TYPE_HOTSPOT
JUNCTION = amdsmi_wrapper.TEMPERATURE_TYPE_JUNCTION
VRAM = amdsmi_wrapper.TEMPERATURE_TYPE_VRAM
HBM_0 = amdsmi_wrapper.TEMPERATURE_TYPE_HBM_0
HBM_1 = amdsmi_wrapper.TEMPERATURE_TYPE_HBM_1
HBM_2 = amdsmi_wrapper.TEMPERATURE_TYPE_HBM_2
HBM_3 = amdsmi_wrapper.TEMPERATURE_TYPE_HBM_3
PLX = amdsmi_wrapper.TEMPERATURE_TYPE_PLX
EDGE = amdsmi_wrapper.AMDSMI_TEMPERATURE_TYPE_EDGE
HOTSPOT = amdsmi_wrapper.AMDSMI_TEMPERATURE_TYPE_HOTSPOT
JUNCTION = amdsmi_wrapper.AMDSMI_TEMPERATURE_TYPE_JUNCTION
VRAM = amdsmi_wrapper.AMDSMI_TEMPERATURE_TYPE_VRAM
HBM_0 = amdsmi_wrapper.AMDSMI_TEMPERATURE_TYPE_HBM_0
HBM_1 = amdsmi_wrapper.AMDSMI_TEMPERATURE_TYPE_HBM_1
HBM_2 = amdsmi_wrapper.AMDSMI_TEMPERATURE_TYPE_HBM_2
HBM_3 = amdsmi_wrapper.AMDSMI_TEMPERATURE_TYPE_HBM_3
PLX = amdsmi_wrapper.AMDSMI_TEMPERATURE_TYPE_PLX
class AmdSmiDevPerfLevel(IntEnum):
@@ -289,20 +289,20 @@ class AmdSmiVoltageType(IntEnum):
class AmdSmiComputePartitionType(IntEnum):
CPX = amdsmi_wrapper.COMPUTE_PARTITION_CPX
SPX = amdsmi_wrapper.COMPUTE_PARTITION_SPX
DPX = amdsmi_wrapper.COMPUTE_PARTITION_DPX
TPX = amdsmi_wrapper.COMPUTE_PARTITION_TPX
QPX = amdsmi_wrapper.COMPUTE_PARTITION_QPX
INVALID = amdsmi_wrapper.COMPUTE_PARTITION_INVALID
CPX = amdsmi_wrapper.AMDSMI_COMPUTE_PARTITION_CPX
SPX = amdsmi_wrapper.AMDSMI_COMPUTE_PARTITION_SPX
DPX = amdsmi_wrapper.AMDSMI_COMPUTE_PARTITION_DPX
TPX = amdsmi_wrapper.AMDSMI_COMPUTE_PARTITION_TPX
QPX = amdsmi_wrapper.AMDSMI_COMPUTE_PARTITION_QPX
INVALID = amdsmi_wrapper.AMDSMI_COMPUTE_PARTITION_INVALID
class AmdSmiMemoryPartitionType(IntEnum):
NPS1 = amdsmi_wrapper.MEMORY_PARTITION_NPS1
NPS2 = amdsmi_wrapper.MEMORY_PARTITION_NPS2
NPS4 = amdsmi_wrapper.MEMORY_PARTITION_NPS4
NPS8 = amdsmi_wrapper.MEMORY_PARTITION_NPS8
UNKNOWN = amdsmi_wrapper.MEMORY_PARTITION_UNKNOWN
NPS1 = amdsmi_wrapper.AMDSMI_MEMORY_PARTITION_NPS1
NPS2 = amdsmi_wrapper.AMDSMI_MEMORY_PARTITION_NPS2
NPS4 = amdsmi_wrapper.AMDSMI_MEMORY_PARTITION_NPS4
NPS8 = amdsmi_wrapper.AMDSMI_MEMORY_PARTITION_NPS8
UNKNOWN = amdsmi_wrapper.AMDSMI_MEMORY_PARTITION_UNKNOWN
class AmdSmiPowerProfilePresetMasks(IntEnum):
@@ -392,10 +392,10 @@ class AmdSmiUtilizationCounterType(IntEnum):
class AmdSmiProcessorType(IntEnum):
UNKNOWN = amdsmi_wrapper.UNKNOWN
AMD_GPU = amdsmi_wrapper.AMD_GPU
AMD_CPU = amdsmi_wrapper.AMD_CPU
NON_AMD_GPU = amdsmi_wrapper.NON_AMD_GPU
NON_AMD_CPU = amdsmi_wrapper.NON_AMD_CPU
AMDSMI_PROCESSOR_TYPE_AMD_GPU = amdsmi_wrapper.AMDSMI_PROCESSOR_TYPE_AMD_GPU
AMDSMI_PROCESSOR_TYPE_AMD_CPU = amdsmi_wrapper.AMDSMI_PROCESSOR_TYPE_AMD_CPU
AMDSMI_PROCESSOR_TYPE_NON_AMD_GPU = amdsmi_wrapper.AMDSMI_PROCESSOR_TYPE_NON_AMD_GPU
AMDSMI_PROCESSOR_TYPE_NON_AMD_CPU = amdsmi_wrapper.AMDSMI_PROCESSOR_TYPE_NON_AMD_CPU
class AmdSmiEventReader:
@@ -513,10 +513,10 @@ def _format_bdf(amdsmi_bdf: amdsmi_wrapper.amdsmi_bdf_t) -> str:
Returns:
`str`: String containing BDF data in a readable format.
"""
domain = hex(amdsmi_bdf.fields.domain_number)[2:].zfill(4)
bus = hex(amdsmi_bdf.fields.bus_number)[2:].zfill(2)
device = hex(amdsmi_bdf.fields.device_number)[2:].zfill(2)
function = hex(amdsmi_bdf.fields.function_number)[2:]
domain = hex(amdsmi_bdf.domain_number)[2:].zfill(4)
bus = hex(amdsmi_bdf.bus_number)[2:].zfill(2)
device = hex(amdsmi_bdf.device_number)[2:].zfill(2)
function = hex(amdsmi_bdf.function_number)[2:]
return domain + ":" + bus + ":" + device + "." + function
@@ -563,10 +563,10 @@ def _make_amdsmi_bdf_from_list(bdf):
if len(bdf) != 4:
return None
amdsmi_bdf = amdsmi_wrapper.amdsmi_bdf_t()
amdsmi_bdf.fields.function_number = bdf[3]
amdsmi_bdf.fields.device_number = bdf[2]
amdsmi_bdf.fields.bus_number = bdf[1]
amdsmi_bdf.fields.domain_number = bdf[0]
amdsmi_bdf.function_number = bdf[3]
amdsmi_bdf.device_number = bdf[2]
amdsmi_bdf.bus_number = bdf[1]
amdsmi_bdf.domain_number = bdf[0]
return amdsmi_bdf
def _padHexValue(value, length):
@@ -626,7 +626,7 @@ def amdsmi_get_cpusocket_handles() -> List[amdsmi_wrapper.amdsmi_socket_handle]:
"""
socket_handles = amdsmi_get_socket_handles()
cpu_handles = []
type = amdsmi_wrapper.AMD_CPU
type = amdsmi_wrapper.AMDSMI_PROCESSOR_TYPE_AMD_CPU
for socket in socket_handles:
cpu_count = ctypes.c_uint32()
null_ptr = ctypes.POINTER(amdsmi_wrapper.amdsmi_processor_handle)()
@@ -719,7 +719,7 @@ def amdsmi_get_processor_handles() -> List[amdsmi_wrapper.amdsmi_processor_handl
def amdsmi_get_cpucore_handles() -> List[amdsmi_wrapper.amdsmi_processor_handle]:
socket_handles = amdsmi_get_socket_handles()
core_handles = []
type = amdsmi_wrapper.AMD_CPU_CORE
type = amdsmi_wrapper.AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE
for socket in socket_handles:
core_count = ctypes.c_uint32()
@@ -1709,7 +1709,7 @@ def amdsmi_get_gpu_vram_info(
return {
"vram_type": vram_info.vram_type,
"vram_vendor": vram_info.vram_vendor,
"vram_size_mb": vram_info.vram_size_mb,
"vram_size": vram_info.vram_size,
}
@@ -1835,10 +1835,11 @@ def amdsmi_get_clock_info(
)
return {
"cur_clk": clock_measure.cur_clk,
"max_clk": clock_measure.max_clk,
"clk": clock_measure.clk,
"min_clk": clock_measure.min_clk,
"sleep_clk" : clock_measure.sleep_clk,
"max_clk": clock_measure.max_clk,
"clk_locked": clock_measure.clk_locked,
"clk_deep_sleep" : clock_measure.clk_deep_sleep,
}
@@ -2119,14 +2120,14 @@ def amdsmi_get_fw_info(
_check_res(amdsmi_wrapper.amdsmi_get_fw_info(
processor_handle, ctypes.byref(fw_info)))
hex_format_fw = [AmdSmiFwBlock.FW_ID_PSP_SOSDRV,
AmdSmiFwBlock.FW_ID_TA_RAS,
AmdSmiFwBlock.FW_ID_TA_XGMI,
AmdSmiFwBlock.FW_ID_UVD,
AmdSmiFwBlock.FW_ID_VCE,
AmdSmiFwBlock.FW_ID_VCN]
hex_format_fw = [AmdSmiFwBlock.AMDSMI_FW_ID_PSP_SOSDRV,
AmdSmiFwBlock.AMDSMI_FW_ID_TA_RAS,
AmdSmiFwBlock.AMDSMI_FW_ID_TA_XGMI,
AmdSmiFwBlock.AMDSMI_FW_ID_UVD,
AmdSmiFwBlock.AMDSMI_FW_ID_VCE,
AmdSmiFwBlock.AMDSMI_FW_ID_VCN]
dec_format_fw = [AmdSmiFwBlock.FW_ID_PM]
dec_format_fw = [AmdSmiFwBlock.AMDSMI_FW_ID_PM]
firmwares = []
for i in range(0, fw_info.num_fw_info):
py-interface/amdsmi_wrapper.py
+319 -319
View File
@@ -226,11 +226,11 @@ amdsmi_mm_ip_t = ctypes.c_uint32 # enum
# values for enumeration 'amdsmi_container_types_t'
amdsmi_container_types_t__enumvalues = {
0: 'CONTAINER_LXC',
1: 'CONTAINER_DOCKER',
0: 'AMDSMI_CONTAINER_LXC',
1: 'AMDSMI_CONTAINER_DOCKER',
}
CONTAINER_LXC = 0
CONTAINER_DOCKER = 1
AMDSMI_CONTAINER_LXC = 0
AMDSMI_CONTAINER_DOCKER = 1
amdsmi_container_types_t = ctypes.c_uint32 # enum
amdsmi_processor_handle = ctypes.POINTER(None)
amdsmi_socket_handle = ctypes.POINTER(None)
@@ -239,20 +239,20 @@ amdsmi_cpusocket_handle = ctypes.POINTER(None)
# values for enumeration 'processor_type_t'
processor_type_t__enumvalues = {
0: 'UNKNOWN',
1: 'AMD_GPU',
2: 'AMD_CPU',
3: 'NON_AMD_GPU',
4: 'NON_AMD_CPU',
5: 'AMD_CPU_CORE',
6: 'AMD_APU',
1: 'AMDSMI_PROCESSOR_TYPE_AMD_GPU',
2: 'AMDSMI_PROCESSOR_TYPE_AMD_CPU',
3: 'AMDSMI_PROCESSOR_TYPE_NON_AMD_GPU',
4: 'AMDSMI_PROCESSOR_TYPE_NON_AMD_CPU',
5: 'AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE',
6: 'AMDSMI_PROCESSOR_TYPE_AMD_APU',
}
UNKNOWN = 0
AMD_GPU = 1
AMD_CPU = 2
NON_AMD_GPU = 3
NON_AMD_CPU = 4
AMD_CPU_CORE = 5
AMD_APU = 6
AMDSMI_PROCESSOR_TYPE_AMD_GPU = 1
AMDSMI_PROCESSOR_TYPE_AMD_CPU = 2
AMDSMI_PROCESSOR_TYPE_NON_AMD_GPU = 3
AMDSMI_PROCESSOR_TYPE_NON_AMD_CPU = 4
AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE = 5
AMDSMI_PROCESSOR_TYPE_AMD_APU = 6
processor_type_t = ctypes.c_uint32 # enum
# values for enumeration 'amdsmi_status_t'
@@ -348,284 +348,284 @@ amdsmi_status_t = ctypes.c_uint32 # enum
# values for enumeration 'amdsmi_clk_type_t'
amdsmi_clk_type_t__enumvalues = {
0: 'CLK_TYPE_SYS',
0: 'CLK_TYPE_FIRST',
0: 'CLK_TYPE_GFX',
1: 'CLK_TYPE_DF',
2: 'CLK_TYPE_DCEF',
3: 'CLK_TYPE_SOC',
4: 'CLK_TYPE_MEM',
5: 'CLK_TYPE_PCIE',
6: 'CLK_TYPE_VCLK0',
7: 'CLK_TYPE_VCLK1',
8: 'CLK_TYPE_DCLK0',
9: 'CLK_TYPE_DCLK1',
9: 'CLK_TYPE__MAX',
0: 'AMDSMI_CLK_TYPE_SYS',
0: 'AMDSMI_CLK_TYPE_FIRST',
0: 'AMDSMI_CLK_TYPE_GFX',
1: 'AMDSMI_CLK_TYPE_DF',
2: 'AMDSMI_CLK_TYPE_DCEF',
3: 'AMDSMI_CLK_TYPE_SOC',
4: 'AMDSMI_CLK_TYPE_MEM',
5: 'AMDSMI_CLK_TYPE_PCIE',
6: 'AMDSMI_CLK_TYPE_VCLK0',
7: 'AMDSMI_CLK_TYPE_VCLK1',
8: 'AMDSMI_CLK_TYPE_DCLK0',
9: 'AMDSMI_CLK_TYPE_DCLK1',
9: 'AMDSMI_CLK_TYPE__MAX',
}
CLK_TYPE_SYS = 0
CLK_TYPE_FIRST = 0
CLK_TYPE_GFX = 0
CLK_TYPE_DF = 1
CLK_TYPE_DCEF = 2
CLK_TYPE_SOC = 3
CLK_TYPE_MEM = 4
CLK_TYPE_PCIE = 5
CLK_TYPE_VCLK0 = 6
CLK_TYPE_VCLK1 = 7
CLK_TYPE_DCLK0 = 8
CLK_TYPE_DCLK1 = 9
CLK_TYPE__MAX = 9
AMDSMI_CLK_TYPE_SYS = 0
AMDSMI_CLK_TYPE_FIRST = 0
AMDSMI_CLK_TYPE_GFX = 0
AMDSMI_CLK_TYPE_DF = 1
AMDSMI_CLK_TYPE_DCEF = 2
AMDSMI_CLK_TYPE_SOC = 3
AMDSMI_CLK_TYPE_MEM = 4
AMDSMI_CLK_TYPE_PCIE = 5
AMDSMI_CLK_TYPE_VCLK0 = 6
AMDSMI_CLK_TYPE_VCLK1 = 7
AMDSMI_CLK_TYPE_DCLK0 = 8
AMDSMI_CLK_TYPE_DCLK1 = 9
AMDSMI_CLK_TYPE__MAX = 9
amdsmi_clk_type_t = ctypes.c_uint32 # enum
# values for enumeration 'amdsmi_compute_partition_type_t'
amdsmi_compute_partition_type_t__enumvalues = {
0: 'COMPUTE_PARTITION_INVALID',
1: 'COMPUTE_PARTITION_CPX',
2: 'COMPUTE_PARTITION_SPX',
3: 'COMPUTE_PARTITION_DPX',
4: 'COMPUTE_PARTITION_TPX',
5: 'COMPUTE_PARTITION_QPX',
0: 'AMDSMI_COMPUTE_PARTITION_INVALID',
1: 'AMDSMI_COMPUTE_PARTITION_CPX',
2: 'AMDSMI_COMPUTE_PARTITION_SPX',
3: 'AMDSMI_COMPUTE_PARTITION_DPX',
4: 'AMDSMI_COMPUTE_PARTITION_TPX',
5: 'AMDSMI_COMPUTE_PARTITION_QPX',
}
COMPUTE_PARTITION_INVALID = 0
COMPUTE_PARTITION_CPX = 1
COMPUTE_PARTITION_SPX = 2
COMPUTE_PARTITION_DPX = 3
COMPUTE_PARTITION_TPX = 4
COMPUTE_PARTITION_QPX = 5
AMDSMI_COMPUTE_PARTITION_INVALID = 0
AMDSMI_COMPUTE_PARTITION_CPX = 1
AMDSMI_COMPUTE_PARTITION_SPX = 2
AMDSMI_COMPUTE_PARTITION_DPX = 3
AMDSMI_COMPUTE_PARTITION_TPX = 4
AMDSMI_COMPUTE_PARTITION_QPX = 5
amdsmi_compute_partition_type_t = ctypes.c_uint32 # enum
# values for enumeration 'amdsmi_memory_partition_type_t'
amdsmi_memory_partition_type_t__enumvalues = {
0: 'MEMORY_PARTITION_UNKNOWN',
1: 'MEMORY_PARTITION_NPS1',
2: 'MEMORY_PARTITION_NPS2',
3: 'MEMORY_PARTITION_NPS4',
4: 'MEMORY_PARTITION_NPS8',
0: 'AMDSMI_MEMORY_PARTITION_UNKNOWN',
1: 'AMDSMI_MEMORY_PARTITION_NPS1',
2: 'AMDSMI_MEMORY_PARTITION_NPS2',
3: 'AMDSMI_MEMORY_PARTITION_NPS4',
4: 'AMDSMI_MEMORY_PARTITION_NPS8',
}
MEMORY_PARTITION_UNKNOWN = 0
MEMORY_PARTITION_NPS1 = 1
MEMORY_PARTITION_NPS2 = 2
MEMORY_PARTITION_NPS4 = 3
MEMORY_PARTITION_NPS8 = 4
AMDSMI_MEMORY_PARTITION_UNKNOWN = 0
AMDSMI_MEMORY_PARTITION_NPS1 = 1
AMDSMI_MEMORY_PARTITION_NPS2 = 2
AMDSMI_MEMORY_PARTITION_NPS4 = 3
AMDSMI_MEMORY_PARTITION_NPS8 = 4
amdsmi_memory_partition_type_t = ctypes.c_uint32 # enum
# values for enumeration 'amdsmi_temperature_type_t'
amdsmi_temperature_type_t__enumvalues = {
0: 'TEMPERATURE_TYPE_EDGE',
0: 'TEMPERATURE_TYPE_FIRST',
1: 'TEMPERATURE_TYPE_HOTSPOT',
1: 'TEMPERATURE_TYPE_JUNCTION',
2: 'TEMPERATURE_TYPE_VRAM',
3: 'TEMPERATURE_TYPE_HBM_0',
4: 'TEMPERATURE_TYPE_HBM_1',
5: 'TEMPERATURE_TYPE_HBM_2',
6: 'TEMPERATURE_TYPE_HBM_3',
7: 'TEMPERATURE_TYPE_PLX',
7: 'TEMPERATURE_TYPE__MAX',
0: 'AMDSMI_TEMPERATURE_TYPE_EDGE',
0: 'AMDSMI_TEMPERATURE_TYPE_FIRST',
1: 'AMDSMI_TEMPERATURE_TYPE_HOTSPOT',
1: 'AMDSMI_TEMPERATURE_TYPE_JUNCTION',
2: 'AMDSMI_TEMPERATURE_TYPE_VRAM',
3: 'AMDSMI_TEMPERATURE_TYPE_HBM_0',
4: 'AMDSMI_TEMPERATURE_TYPE_HBM_1',
5: 'AMDSMI_TEMPERATURE_TYPE_HBM_2',
6: 'AMDSMI_TEMPERATURE_TYPE_HBM_3',
7: 'AMDSMI_TEMPERATURE_TYPE_PLX',
7: 'AMDSMI_TEMPERATURE_TYPE__MAX',
}
TEMPERATURE_TYPE_EDGE = 0
TEMPERATURE_TYPE_FIRST = 0
TEMPERATURE_TYPE_HOTSPOT = 1
TEMPERATURE_TYPE_JUNCTION = 1
TEMPERATURE_TYPE_VRAM = 2
TEMPERATURE_TYPE_HBM_0 = 3
TEMPERATURE_TYPE_HBM_1 = 4
TEMPERATURE_TYPE_HBM_2 = 5
TEMPERATURE_TYPE_HBM_3 = 6
TEMPERATURE_TYPE_PLX = 7
TEMPERATURE_TYPE__MAX = 7
AMDSMI_TEMPERATURE_TYPE_EDGE = 0
AMDSMI_TEMPERATURE_TYPE_FIRST = 0
AMDSMI_TEMPERATURE_TYPE_HOTSPOT = 1
AMDSMI_TEMPERATURE_TYPE_JUNCTION = 1
AMDSMI_TEMPERATURE_TYPE_VRAM = 2
AMDSMI_TEMPERATURE_TYPE_HBM_0 = 3
AMDSMI_TEMPERATURE_TYPE_HBM_1 = 4
AMDSMI_TEMPERATURE_TYPE_HBM_2 = 5
AMDSMI_TEMPERATURE_TYPE_HBM_3 = 6
AMDSMI_TEMPERATURE_TYPE_PLX = 7
AMDSMI_TEMPERATURE_TYPE__MAX = 7
amdsmi_temperature_type_t = ctypes.c_uint32 # enum
# values for enumeration 'amdsmi_fw_block_t'
amdsmi_fw_block_t__enumvalues = {
1: 'FW_ID_SMU',
1: 'FW_ID_FIRST',
2: 'FW_ID_CP_CE',
3: 'FW_ID_CP_PFP',
4: 'FW_ID_CP_ME',
5: 'FW_ID_CP_MEC_JT1',
6: 'FW_ID_CP_MEC_JT2',
7: 'FW_ID_CP_MEC1',
8: 'FW_ID_CP_MEC2',
9: 'FW_ID_RLC',
10: 'FW_ID_SDMA0',
11: 'FW_ID_SDMA1',
12: 'FW_ID_SDMA2',
13: 'FW_ID_SDMA3',
14: 'FW_ID_SDMA4',
15: 'FW_ID_SDMA5',
16: 'FW_ID_SDMA6',
17: 'FW_ID_SDMA7',
18: 'FW_ID_VCN',
19: 'FW_ID_UVD',
20: 'FW_ID_VCE',
21: 'FW_ID_ISP',
22: 'FW_ID_DMCU_ERAM',
23: 'FW_ID_DMCU_ISR',
24: 'FW_ID_RLC_RESTORE_LIST_GPM_MEM',
25: 'FW_ID_RLC_RESTORE_LIST_SRM_MEM',
26: 'FW_ID_RLC_RESTORE_LIST_CNTL',
27: 'FW_ID_RLC_V',
28: 'FW_ID_MMSCH',
29: 'FW_ID_PSP_SYSDRV',
30: 'FW_ID_PSP_SOSDRV',
31: 'FW_ID_PSP_TOC',
32: 'FW_ID_PSP_KEYDB',
33: 'FW_ID_DFC',
34: 'FW_ID_PSP_SPL',
35: 'FW_ID_DRV_CAP',
36: 'FW_ID_MC',
37: 'FW_ID_PSP_BL',
38: 'FW_ID_CP_PM4',
39: 'FW_ID_RLC_P',
40: 'FW_ID_SEC_POLICY_STAGE2',
41: 'FW_ID_REG_ACCESS_WHITELIST',
42: 'FW_ID_IMU_DRAM',
43: 'FW_ID_IMU_IRAM',
44: 'FW_ID_SDMA_TH0',
45: 'FW_ID_SDMA_TH1',
46: 'FW_ID_CP_MES',
47: 'FW_ID_MES_KIQ',
48: 'FW_ID_MES_STACK',
49: 'FW_ID_MES_THREAD1',
50: 'FW_ID_MES_THREAD1_STACK',
51: 'FW_ID_RLX6',
52: 'FW_ID_RLX6_DRAM_BOOT',
53: 'FW_ID_RS64_ME',
54: 'FW_ID_RS64_ME_P0_DATA',
55: 'FW_ID_RS64_ME_P1_DATA',
56: 'FW_ID_RS64_PFP',
57: 'FW_ID_RS64_PFP_P0_DATA',
58: 'FW_ID_RS64_PFP_P1_DATA',
59: 'FW_ID_RS64_MEC',
60: 'FW_ID_RS64_MEC_P0_DATA',
61: 'FW_ID_RS64_MEC_P1_DATA',
62: 'FW_ID_RS64_MEC_P2_DATA',
63: 'FW_ID_RS64_MEC_P3_DATA',
64: 'FW_ID_PPTABLE',
65: 'FW_ID_PSP_SOC',
66: 'FW_ID_PSP_DBG',
67: 'FW_ID_PSP_INTF',
68: 'FW_ID_RLX6_CORE1',
69: 'FW_ID_RLX6_DRAM_BOOT_CORE1',
70: 'FW_ID_RLCV_LX7',
71: 'FW_ID_RLC_SAVE_RESTORE_LIST',
72: 'FW_ID_ASD',
73: 'FW_ID_TA_RAS',
74: 'FW_ID_TA_XGMI',
75: 'FW_ID_RLC_SRLG',
76: 'FW_ID_RLC_SRLS',
77: 'FW_ID_PM',
78: 'FW_ID_DMCU',
79: 'FW_ID__MAX',
1: 'AMDSMI_FW_ID_SMU',
1: 'AMDSMI_FW_ID_FIRST',
2: 'AMDSMI_FW_ID_CP_CE',
3: 'AMDSMI_FW_ID_CP_PFP',
4: 'AMDSMI_FW_ID_CP_ME',
5: 'AMDSMI_FW_ID_CP_MEC_JT1',
6: 'AMDSMI_FW_ID_CP_MEC_JT2',
7: 'AMDSMI_FW_ID_CP_MEC1',
8: 'AMDSMI_FW_ID_CP_MEC2',
9: 'AMDSMI_FW_ID_RLC',
10: 'AMDSMI_FW_ID_SDMA0',
11: 'AMDSMI_FW_ID_SDMA1',
12: 'AMDSMI_FW_ID_SDMA2',
13: 'AMDSMI_FW_ID_SDMA3',
14: 'AMDSMI_FW_ID_SDMA4',
15: 'AMDSMI_FW_ID_SDMA5',
16: 'AMDSMI_FW_ID_SDMA6',
17: 'AMDSMI_FW_ID_SDMA7',
18: 'AMDSMI_FW_ID_VCN',
19: 'AMDSMI_FW_ID_UVD',
20: 'AMDSMI_FW_ID_VCE',
21: 'AMDSMI_ FW_ID_ISP',
22: 'AMDSMI_FW_ID_DMCU_ERAM',
23: 'AMDSMI_FW_ID_DMCU_ISR',
24: 'AMDSMI_FW_ID_RLC_RESTORE_LIST_GPM_MEM',
25: 'AMDSMI_FW_ID_RLC_RESTORE_LIST_SRM_MEM',
26: 'AMDSMI_FW_ID_RLC_RESTORE_LIST_CNTL',
27: 'AMDSMI_FW_ID_RLC_V',
28: 'AMDSMI_FW_ID_MMSCH',
29: 'AMDSMI_FW_ID_PSP_SYSDRV',
30: 'AMDSMI_FW_ID_PSP_SOSDRV',
31: 'AMDSMI_FW_ID_PSP_TOC',
32: 'AMDSMI_FW_ID_PSP_KEYDB',
33: 'AMDSMI_FW_ID_DFC',
34: 'AMDSMI_FW_ID_PSP_SPL',
35: 'AMDSMI_FW_ID_DRV_CAP',
36: 'AMDSMI_FW_ID_MC',
37: 'AMDSMI_FW_ID_PSP_BL',
38: 'AMDSMI_FW_ID_CP_PM4',
39: 'AMDSMI_FW_ID_RLC_P',
40: 'AMDSMI_FW_ID_SEC_POLICY_STAGE2',
41: 'AMDSMI_FW_ID_REG_ACCESS_WHITELIST',
42: 'AMDSMI_FW_ID_IMU_DRAM',
43: 'AMDSMI_FW_ID_IMU_IRAM',
44: 'AMDSMI_FW_ID_SDMA_TH0',
45: 'AMDSMI_FW_ID_SDMA_TH1',
46: 'AMDSMI_FW_ID_CP_MES',
47: 'AMDSMI_FW_ID_MES_KIQ',
48: 'AMDSMI_FW_ID_MES_STACK',
49: 'AMDSMI_FW_ID_MES_THREAD1',
50: 'AMDSMI_FW_ID_MES_THREAD1_STACK',
51: 'AMDSMI_FW_ID_RLX6',
52: 'AMDSMI_FW_ID_RLX6_DRAM_BOOT',
53: 'AMDSMI_FW_ID_RS64_ME',
54: 'AMDSMI_FW_ID_RS64_ME_P0_DATA',
55: 'AMDSMI_FW_ID_RS64_ME_P1_DATA',
56: 'AMDSMI_FW_ID_RS64_PFP',
57: 'AMDSMI_FW_ID_RS64_PFP_P0_DATA',
58: 'AMDSMI_FW_ID_RS64_PFP_P1_DATA',
59: 'AMDSMI_FW_ID_RS64_MEC',
60: 'AMDSMI_FW_ID_RS64_MEC_P0_DATA',
61: 'AMDSMI_FW_ID_RS64_MEC_P1_DATA',
62: 'AMDSMI_FW_ID_RS64_MEC_P2_DATA',
63: 'AMDSMI_FW_ID_RS64_MEC_P3_DATA',
64: 'AMDSMI_FW_ID_PPTABLE',
65: 'AMDSMI_FW_ID_PSP_SOC',
66: 'AMDSMI_FW_ID_PSP_DBG',
67: 'AMDSMI_FW_ID_PSP_INTF',
68: 'AMDSMI_FW_ID_RLX6_CORE1',
69: 'AMDSMI_FW_ID_RLX6_DRAM_BOOT_CORE1',
70: 'AMDSMI_FW_ID_RLCV_LX7',
71: 'AMDSMI_FW_ID_RLC_SAVE_RESTORE_LIST',
72: 'AMDSMI_FW_ID_ASD',
73: 'AMDSMI_FW_ID_TA_RAS',
74: 'AMDSMI_FW_ID_TA_XGMI',
75: 'AMDSMI_FW_ID_RLC_SRLG',
76: 'AMDSMI_FW_ID_RLC_SRLS',
77: 'AMDSMI_FW_ID_PM',
78: 'AMDSMI_FW_ID_DMCU',
79: 'AMDSMI_FW_ID__MAX',
}
FW_ID_SMU = 1
FW_ID_FIRST = 1
FW_ID_CP_CE = 2
FW_ID_CP_PFP = 3
FW_ID_CP_ME = 4
FW_ID_CP_MEC_JT1 = 5
FW_ID_CP_MEC_JT2 = 6
FW_ID_CP_MEC1 = 7
FW_ID_CP_MEC2 = 8
FW_ID_RLC = 9
FW_ID_SDMA0 = 10
FW_ID_SDMA1 = 11
FW_ID_SDMA2 = 12
FW_ID_SDMA3 = 13
FW_ID_SDMA4 = 14
FW_ID_SDMA5 = 15
FW_ID_SDMA6 = 16
FW_ID_SDMA7 = 17
FW_ID_VCN = 18
FW_ID_UVD = 19
FW_ID_VCE = 20
FW_ID_ISP = 21
FW_ID_DMCU_ERAM = 22
FW_ID_DMCU_ISR = 23
FW_ID_RLC_RESTORE_LIST_GPM_MEM = 24
FW_ID_RLC_RESTORE_LIST_SRM_MEM = 25
FW_ID_RLC_RESTORE_LIST_CNTL = 26
FW_ID_RLC_V = 27
FW_ID_MMSCH = 28
FW_ID_PSP_SYSDRV = 29
FW_ID_PSP_SOSDRV = 30
FW_ID_PSP_TOC = 31
FW_ID_PSP_KEYDB = 32
FW_ID_DFC = 33
FW_ID_PSP_SPL = 34
FW_ID_DRV_CAP = 35
FW_ID_MC = 36
FW_ID_PSP_BL = 37
FW_ID_CP_PM4 = 38
FW_ID_RLC_P = 39
FW_ID_SEC_POLICY_STAGE2 = 40
FW_ID_REG_ACCESS_WHITELIST = 41
FW_ID_IMU_DRAM = 42
FW_ID_IMU_IRAM = 43
FW_ID_SDMA_TH0 = 44
FW_ID_SDMA_TH1 = 45
FW_ID_CP_MES = 46
FW_ID_MES_KIQ = 47
FW_ID_MES_STACK = 48
FW_ID_MES_THREAD1 = 49
FW_ID_MES_THREAD1_STACK = 50
FW_ID_RLX6 = 51
FW_ID_RLX6_DRAM_BOOT = 52
FW_ID_RS64_ME = 53
FW_ID_RS64_ME_P0_DATA = 54
FW_ID_RS64_ME_P1_DATA = 55
FW_ID_RS64_PFP = 56
FW_ID_RS64_PFP_P0_DATA = 57
FW_ID_RS64_PFP_P1_DATA = 58
FW_ID_RS64_MEC = 59
FW_ID_RS64_MEC_P0_DATA = 60
FW_ID_RS64_MEC_P1_DATA = 61
FW_ID_RS64_MEC_P2_DATA = 62
FW_ID_RS64_MEC_P3_DATA = 63
FW_ID_PPTABLE = 64
FW_ID_PSP_SOC = 65
FW_ID_PSP_DBG = 66
FW_ID_PSP_INTF = 67
FW_ID_RLX6_CORE1 = 68
FW_ID_RLX6_DRAM_BOOT_CORE1 = 69
FW_ID_RLCV_LX7 = 70
FW_ID_RLC_SAVE_RESTORE_LIST = 71
FW_ID_ASD = 72
FW_ID_TA_RAS = 73
FW_ID_TA_XGMI = 74
FW_ID_RLC_SRLG = 75
FW_ID_RLC_SRLS = 76
FW_ID_PM = 77
FW_ID_DMCU = 78
FW_ID__MAX = 79
AMDSMI_FW_ID_SMU = 1
AMDSMI_FW_ID_FIRST = 1
AMDSMI_FW_ID_CP_CE = 2
AMDSMI_FW_ID_CP_PFP = 3
AMDSMI_FW_ID_CP_ME = 4
AMDSMI_FW_ID_CP_MEC_JT1 = 5
AMDSMI_FW_ID_CP_MEC_JT2 = 6
AMDSMI_FW_ID_CP_MEC1 = 7
AMDSMI_FW_ID_CP_MEC2 = 8
AMDSMI_FW_ID_RLC = 9
AMDSMI_FW_ID_SDMA0 = 10
AMDSMI_FW_ID_SDMA1 = 11
AMDSMI_FW_ID_SDMA2 = 12
AMDSMI_FW_ID_SDMA3 = 13
AMDSMI_FW_ID_SDMA4 = 14
AMDSMI_FW_ID_SDMA5 = 15
AMDSMI_FW_ID_SDMA6 = 16
AMDSMI_FW_ID_SDMA7 = 17
AMDSMI_FW_ID_VCN = 18
AMDSMI_FW_ID_UVD = 19
AMDSMI_FW_ID_VCE = 20
AMDSMI_ FW_ID_ISP = 21
AMDSMI_FW_ID_DMCU_ERAM = 22
AMDSMI_FW_ID_DMCU_ISR = 23
AMDSMI_FW_ID_RLC_RESTORE_LIST_GPM_MEM = 24
AMDSMI_FW_ID_RLC_RESTORE_LIST_SRM_MEM = 25
AMDSMI_FW_ID_RLC_RESTORE_LIST_CNTL = 26
AMDSMI_FW_ID_RLC_V = 27
AMDSMI_FW_ID_MMSCH = 28
AMDSMI_FW_ID_PSP_SYSDRV = 29
AMDSMI_FW_ID_PSP_SOSDRV = 30
AMDSMI_FW_ID_PSP_TOC = 31
AMDSMI_FW_ID_PSP_KEYDB = 32
AMDSMI_FW_ID_DFC = 33
AMDSMI_FW_ID_PSP_SPL = 34
AMDSMI_FW_ID_DRV_CAP = 35
AMDSMI_FW_ID_MC = 36
AMDSMI_FW_ID_PSP_BL = 37
AMDSMI_FW_ID_CP_PM4 = 38
AMDSMI_FW_ID_RLC_P = 39
AMDSMI_FW_ID_SEC_POLICY_STAGE2 = 40
AMDSMI_FW_ID_REG_ACCESS_WHITELIST = 41
AMDSMI_FW_ID_IMU_DRAM = 42
AMDSMI_FW_ID_IMU_IRAM = 43
AMDSMI_FW_ID_SDMA_TH0 = 44
AMDSMI_FW_ID_SDMA_TH1 = 45
AMDSMI_FW_ID_CP_MES = 46
AMDSMI_FW_ID_MES_KIQ = 47
AMDSMI_FW_ID_MES_STACK = 48
AMDSMI_FW_ID_MES_THREAD1 = 49
AMDSMI_FW_ID_MES_THREAD1_STACK = 50
AMDSMI_FW_ID_RLX6 = 51
AMDSMI_FW_ID_RLX6_DRAM_BOOT = 52
AMDSMI_FW_ID_RS64_ME = 53
AMDSMI_FW_ID_RS64_ME_P0_DATA = 54
AMDSMI_FW_ID_RS64_ME_P1_DATA = 55
AMDSMI_FW_ID_RS64_PFP = 56
AMDSMI_FW_ID_RS64_PFP_P0_DATA = 57
AMDSMI_FW_ID_RS64_PFP_P1_DATA = 58
AMDSMI_FW_ID_RS64_MEC = 59
AMDSMI_FW_ID_RS64_MEC_P0_DATA = 60
AMDSMI_FW_ID_RS64_MEC_P1_DATA = 61
AMDSMI_FW_ID_RS64_MEC_P2_DATA = 62
AMDSMI_FW_ID_RS64_MEC_P3_DATA = 63
AMDSMI_FW_ID_PPTABLE = 64
AMDSMI_FW_ID_PSP_SOC = 65
AMDSMI_FW_ID_PSP_DBG = 66
AMDSMI_FW_ID_PSP_INTF = 67
AMDSMI_FW_ID_RLX6_CORE1 = 68
AMDSMI_FW_ID_RLX6_DRAM_BOOT_CORE1 = 69
AMDSMI_FW_ID_RLCV_LX7 = 70
AMDSMI_FW_ID_RLC_SAVE_RESTORE_LIST = 71
AMDSMI_FW_ID_ASD = 72
AMDSMI_FW_ID_TA_RAS = 73
AMDSMI_FW_ID_TA_XGMI = 74
AMDSMI_FW_ID_RLC_SRLG = 75
AMDSMI_FW_ID_RLC_SRLS = 76
AMDSMI_FW_ID_PM = 77
AMDSMI_FW_ID_DMCU = 78
AMDSMI_FW_ID__MAX = 79
amdsmi_fw_block_t = ctypes.c_uint32 # enum
# values for enumeration 'amdsmi_vram_type_t'
amdsmi_vram_type_t__enumvalues = {
0: 'VRAM_TYPE_UNKNOWN',
1: 'VRAM_TYPE_GDDR1',
2: 'VRAM_TYPE_DDR2',
3: 'VRAM_TYPE_GDDR3',
4: 'VRAM_TYPE_GDDR4',
5: 'VRAM_TYPE_GDDR5',
6: 'VRAM_TYPE_HBM',
7: 'VRAM_TYPE_DDR3',
8: 'VRAM_TYPE_DDR4',
9: 'VRAM_TYPE_GDDR6',
9: 'VRAM_TYPE__MAX',
0: 'AMDSMI_VRAM_TYPE_UNKNOWN',
1: 'AMDSMI_VRAM_TYPE_GDDR1',
2: 'AMDSMI_VRAM_TYPE_DDR2',
3: 'AMDSMI_VRAM_TYPE_GDDR3',
4: 'AMDSMI_VRAM_TYPE_GDDR4',
5: 'AMDSMI_VRAM_TYPE_GDDR5',
6: 'AMDSMI_VRAM_TYPE_HBM',
7: 'AMDSMI_VRAM_TYPE_DDR3',
8: 'AMDSMI_VRAM_TYPE_DDR4',
9: 'AMDSMI_VRAM_TYPE_GDDR6',
9: 'AMDSMI_VRAM_TYPE__MAX',
}
VRAM_TYPE_UNKNOWN = 0
VRAM_TYPE_GDDR1 = 1
VRAM_TYPE_DDR2 = 2
VRAM_TYPE_GDDR3 = 3
VRAM_TYPE_GDDR4 = 4
VRAM_TYPE_GDDR5 = 5
VRAM_TYPE_HBM = 6
VRAM_TYPE_DDR3 = 7
VRAM_TYPE_DDR4 = 8
VRAM_TYPE_GDDR6 = 9
VRAM_TYPE__MAX = 9
AMDSMI_VRAM_TYPE_UNKNOWN = 0
AMDSMI_VRAM_TYPE_GDDR1 = 1
AMDSMI_VRAM_TYPE_DDR2 = 2
AMDSMI_VRAM_TYPE_GDDR3 = 3
AMDSMI_VRAM_TYPE_GDDR4 = 4
AMDSMI_VRAM_TYPE_GDDR5 = 5
AMDSMI_VRAM_TYPE_HBM = 6
AMDSMI_VRAM_TYPE_DDR3 = 7
AMDSMI_VRAM_TYPE_DDR4 = 8
AMDSMI_VRAM_TYPE_GDDR6 = 9
AMDSMI_VRAM_TYPE__MAX = 9
amdsmi_vram_type_t = ctypes.c_uint32 # enum
# values for enumeration 'amdsmi_vram_vendor_type_t'
@@ -941,7 +941,7 @@ struct_amdsmi_vram_info_t._pack_ = 1 # source:False
struct_amdsmi_vram_info_t._fields_ = [
('vram_type', amdsmi_vram_type_t),
('vram_vendor', amdsmi_vram_vendor_type_t),
('vram_size_mb', ctypes.c_uint64),
('vram_size', ctypes.c_uint64),
]
amdsmi_vram_info_t = struct_amdsmi_vram_info_t
@@ -990,10 +990,10 @@ class struct_amdsmi_clk_info_t(Structure):
struct_amdsmi_clk_info_t._pack_ = 1 # source:False
struct_amdsmi_clk_info_t._fields_ = [
('cur_clk', ctypes.c_uint32),
('clk', ctypes.c_uint32),
('min_clk', ctypes.c_uint32),
('max_clk', ctypes.c_uint32),
('sleep_clk', ctypes.c_uint32),
('clk_deep_sleep', ctypes.c_uint32),
('reserved', ctypes.c_uint32 * 4),
]
@@ -2488,54 +2488,54 @@ __all__ = \
'AMDSMI_VRAM_VENDOR__PLACEHOLDER5', 'AMDSMI_VRAM_VENDOR__SAMSUNG',
'AMDSMI_VRAM_VENDOR__WINBOND', 'AMDSMI_XGMI_STATUS_ERROR',
'AMDSMI_XGMI_STATUS_MULTIPLE_ERRORS',
'AMDSMI_XGMI_STATUS_NO_ERRORS', 'AMD_APU', 'AMD_CPU',
'AMD_CPU_CORE', 'AMD_GPU', 'CLK_TYPE_DCEF', 'CLK_TYPE_DCLK0',
'CLK_TYPE_DCLK1', 'CLK_TYPE_DF', 'CLK_TYPE_FIRST', 'CLK_TYPE_GFX',
'CLK_TYPE_MEM', 'CLK_TYPE_PCIE', 'CLK_TYPE_SOC', 'CLK_TYPE_SYS',
'CLK_TYPE_VCLK0', 'CLK_TYPE_VCLK1', 'CLK_TYPE__MAX',
'COMPUTE_PARTITION_CPX', 'COMPUTE_PARTITION_DPX',
'COMPUTE_PARTITION_INVALID', 'COMPUTE_PARTITION_QPX',
'COMPUTE_PARTITION_SPX', 'COMPUTE_PARTITION_TPX',
'CONTAINER_DOCKER', 'CONTAINER_LXC', 'FW_ID_ASD', 'FW_ID_CP_CE',
'FW_ID_CP_ME', 'FW_ID_CP_MEC1', 'FW_ID_CP_MEC2',
'FW_ID_CP_MEC_JT1', 'FW_ID_CP_MEC_JT2', 'FW_ID_CP_MES',
'FW_ID_CP_PFP', 'FW_ID_CP_PM4', 'FW_ID_DFC', 'FW_ID_DMCU',
'FW_ID_DMCU_ERAM', 'FW_ID_DMCU_ISR', 'FW_ID_DRV_CAP',
'FW_ID_FIRST', 'FW_ID_IMU_DRAM', 'FW_ID_IMU_IRAM', 'FW_ID_ISP',
'FW_ID_MC', 'FW_ID_MES_KIQ', 'FW_ID_MES_STACK',
'FW_ID_MES_THREAD1', 'FW_ID_MES_THREAD1_STACK', 'FW_ID_MMSCH',
'FW_ID_PM', 'FW_ID_PPTABLE', 'FW_ID_PSP_BL', 'FW_ID_PSP_DBG',
'FW_ID_PSP_INTF', 'FW_ID_PSP_KEYDB', 'FW_ID_PSP_SOC',
'FW_ID_PSP_SOSDRV', 'FW_ID_PSP_SPL', 'FW_ID_PSP_SYSDRV',
'FW_ID_PSP_TOC', 'FW_ID_REG_ACCESS_WHITELIST', 'FW_ID_RLC',
'FW_ID_RLCV_LX7', 'FW_ID_RLC_P', 'FW_ID_RLC_RESTORE_LIST_CNTL',
'FW_ID_RLC_RESTORE_LIST_GPM_MEM',
'FW_ID_RLC_RESTORE_LIST_SRM_MEM', 'FW_ID_RLC_SAVE_RESTORE_LIST',
'FW_ID_RLC_SRLG', 'FW_ID_RLC_SRLS', 'FW_ID_RLC_V', 'FW_ID_RLX6',
'FW_ID_RLX6_CORE1', 'FW_ID_RLX6_DRAM_BOOT',
'FW_ID_RLX6_DRAM_BOOT_CORE1', 'FW_ID_RS64_ME', 'FW_ID_RS64_MEC',
'FW_ID_RS64_MEC_P0_DATA', 'FW_ID_RS64_MEC_P1_DATA',
'FW_ID_RS64_MEC_P2_DATA', 'FW_ID_RS64_MEC_P3_DATA',
'FW_ID_RS64_ME_P0_DATA', 'FW_ID_RS64_ME_P1_DATA',
'FW_ID_RS64_PFP', 'FW_ID_RS64_PFP_P0_DATA',
'FW_ID_RS64_PFP_P1_DATA', 'FW_ID_SDMA0', 'FW_ID_SDMA1',
'FW_ID_SDMA2', 'FW_ID_SDMA3', 'FW_ID_SDMA4', 'FW_ID_SDMA5',
'FW_ID_SDMA6', 'FW_ID_SDMA7', 'FW_ID_SDMA_TH0', 'FW_ID_SDMA_TH1',
'FW_ID_SEC_POLICY_STAGE2', 'FW_ID_SMU', 'FW_ID_TA_RAS',
'FW_ID_TA_XGMI', 'FW_ID_UVD', 'FW_ID_VCE', 'FW_ID_VCN',
'FW_ID__MAX', 'MEMORY_PARTITION_NPS1', 'MEMORY_PARTITION_NPS2',
'MEMORY_PARTITION_NPS4', 'MEMORY_PARTITION_NPS8',
'MEMORY_PARTITION_UNKNOWN', 'NON_AMD_CPU', 'NON_AMD_GPU',
'RD_BW0', 'TEMPERATURE_TYPE_EDGE', 'TEMPERATURE_TYPE_FIRST',
'TEMPERATURE_TYPE_HBM_0', 'TEMPERATURE_TYPE_HBM_1',
'TEMPERATURE_TYPE_HBM_2', 'TEMPERATURE_TYPE_HBM_3',
'TEMPERATURE_TYPE_HOTSPOT', 'TEMPERATURE_TYPE_JUNCTION',
'TEMPERATURE_TYPE_PLX', 'TEMPERATURE_TYPE_VRAM',
'TEMPERATURE_TYPE__MAX', 'UNKNOWN', 'VRAM_TYPE_DDR2',
'VRAM_TYPE_DDR3', 'VRAM_TYPE_DDR4', 'VRAM_TYPE_GDDR1',
'VRAM_TYPE_GDDR3', 'VRAM_TYPE_GDDR4', 'VRAM_TYPE_GDDR5',
'VRAM_TYPE_GDDR6', 'VRAM_TYPE_HBM', 'VRAM_TYPE_UNKNOWN',
'VRAM_TYPE__MAX', 'WR_BW0', 'amd_metrics_table_header_t',
'AMDSMI_XGMI_STATUS_NO_ERRORS', 'AMDSMI_PROCESSOR_TYPE_AMD_APU', 'AMDSMI_PROCESSOR_TYPE_AMD_CPU',
'AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE', 'AMDSMI_PROCESSOR_TYPE_AMD_GPU', 'AMDSMI_CLK_TYPE_DCEF', 'AMDSMI_CLK_TYPE_DCLK0',
'AMDSMI_CLK_TYPE_DCLK1', 'AMDSMI_CLK_TYPE_DF', 'AMDSMI_CLK_TYPE_FIRST', 'AMDSMI_CLK_TYPE_GFX',
'AMDSMI_CLK_TYPE_MEM', 'AMDSMI_CLK_TYPE_PCIE', 'AMDSMI_CLK_TYPE_SOC', 'AMDSMI_CLK_TYPE_SYS',
'AMDSMI_CLK_TYPE_VCLK0', 'AMDSMI_CLK_TYPE_VCLK1', 'AMDSMI_CLK_TYPE__MAX',
'AMDSMI_COMPUTE_PARTITION_CPX', 'AMDSMI_COMPUTE_PARTITION_DPX',
'AMDSMI_COMPUTE_PARTITION_INVALID', 'AMDSMI_COMPUTE_PARTITION_QPX',
'AMDSMI_COMPUTE_PARTITION_SPX', 'AMDSMI_COMPUTE_PARTITION_TPX',
'AMDSMI_CONTAINER_DOCKER', 'AMDSMI_CONTAINER_LXC', 'AMDSMI_FW_ID_ASD', 'AMDSMI_FW_ID_CP_CE',
'AMDSMI_FW_ID_CP_ME', 'AMDSMI_FW_ID_CP_MEC1', 'AMDSMI_FW_ID_CP_MEC2',
'AMDSMI_FW_ID_CP_MEC_JT1', 'AMDSMI_FW_ID_CP_MEC_JT2', 'AMDSMI_FW_ID_CP_MES',
'AMDSMI_FW_ID_CP_PFP', 'AMDSMI_FW_ID_CP_PM4', 'AMDSMI_FW_ID_DFC', 'AMDSMI_FW_ID_DMCU',
'AMDSMI_FW_ID_DMCU_ERAM', 'AMDSMI_FW_ID_DMCU_ISR', 'AMDSMI_FW_ID_DRV_CAP',
'AMDSMI_FW_ID_FIRST', 'AMDSMI_FW_ID_IMU_DRAM', 'AMDSMI_FW_ID_IMU_IRAM', 'AMDSMI_ FW_ID_ISP',
'AMDSMI_FW_ID_MC', 'AMDSMI_FW_ID_MES_KIQ', 'AMDSMI_FW_ID_MES_STACK',
'AMDSMI_FW_ID_MES_THREAD1', 'AMDSMI_FW_ID_MES_THREAD1_STACK', 'AMDSMI_FW_ID_MMSCH',
'AMDSMI_FW_ID_PM', 'AMDSMI_FW_ID_PPTABLE', 'AMDSMI_FW_ID_PSP_BL', 'AMDSMI_FW_ID_PSP_DBG',
'AMDSMI_FW_ID_PSP_INTF', 'AMDSMI_FW_ID_PSP_KEYDB', 'AMDSMI_FW_ID_PSP_SOC',
'AMDSMI_FW_ID_PSP_SOSDRV', 'AMDSMI_FW_ID_PSP_SPL', 'AMDSMI_FW_ID_PSP_SYSDRV',
'AMDSMI_FW_ID_PSP_TOC', 'AMDSMI_FW_ID_REG_ACCESS_WHITELIST', 'AMDSMI_FW_ID_RLC',
'AMDSMI_FW_ID_RLCV_LX7', 'AMDSMI_FW_ID_RLC_P', 'AMDSMI_FW_ID_RLC_RESTORE_LIST_CNTL',
'AMDSMI_FW_ID_RLC_RESTORE_LIST_GPM_MEM',
'AMDSMI_FW_ID_RLC_RESTORE_LIST_SRM_MEM', 'AMDSMI_FW_ID_RLC_SAVE_RESTORE_LIST',
'AMDSMI_FW_ID_RLC_SRLG', 'AMDSMI_FW_ID_RLC_SRLS', 'AMDSMI_FW_ID_RLC_V', 'AMDSMI_FW_ID_RLX6',
'AMDSMI_FW_ID_RLX6_CORE1', 'AMDSMI_FW_ID_RLX6_DRAM_BOOT',
'AMDSMI_FW_ID_RLX6_DRAM_BOOT_CORE1', 'AMDSMI_FW_ID_RS64_ME', 'AMDSMI_FW_ID_RS64_MEC',
'AMDSMI_FW_ID_RS64_MEC_P0_DATA', 'AMDSMI_FW_ID_RS64_MEC_P1_DATA',
'AMDSMI_FW_ID_RS64_MEC_P2_DATA', 'AMDSMI_FW_ID_RS64_MEC_P3_DATA',
'AMDSMI_FW_ID_RS64_ME_P0_DATA', 'AMDSMI_FW_ID_RS64_ME_P1_DATA',
'AMDSMI_FW_ID_RS64_PFP', 'AMDSMI_FW_ID_RS64_PFP_P0_DATA',
'AMDSMI_FW_ID_RS64_PFP_P1_DATA', 'AMDSMI_FW_ID_SDMA0', 'AMDSMI_FW_ID_SDMA1',
'AMDSMI_FW_ID_SDMA2', 'AMDSMI_FW_ID_SDMA3', 'AMDSMI_FW_ID_SDMA4', 'AMDSMI_FW_ID_SDMA5',
'AMDSMI_FW_ID_SDMA6', 'AMDSMI_FW_ID_SDMA7', 'AMDSMI_FW_ID_SDMA_TH0', 'AMDSMI_FW_ID_SDMA_TH1',
'AMDSMI_FW_ID_SEC_POLICY_STAGE2', 'AMDSMI_FW_ID_SMU', 'AMDSMI_FW_ID_TA_RAS',
'AMDSMI_FW_ID_TA_XGMI', 'AMDSMI_FW_ID_UVD', 'AMDSMI_FW_ID_VCE', 'AMDSMI_FW_ID_VCN',
'AMDSMI_FW_ID__MAX', 'AMDSMI_MEMORY_PARTITION_NPS1', 'AMDSMI_MEMORY_PARTITION_NPS2',
'AMDSMI_MEMORY_PARTITION_NPS4', 'AMDSMI_MEMORY_PARTITION_NPS8',
'AMDSMI_MEMORY_PARTITION_UNKNOWN', 'AMDSMI_PROCESSOR_TYPE_NON_AMD_CPU', 'AMDSMI_PROCESSOR_TYPE_NON_AMD_GPU',
'RD_BW0', 'AMDSMI_TEMPERATURE_TYPE_EDGE', 'AMDSMI_TEMPERATURE_TYPE_FIRST',
'AMDSMI_TEMPERATURE_TYPE_HBM_0', 'AMDSMI_TEMPERATURE_TYPE_HBM_1',
'AMDSMI_TEMPERATURE_TYPE_HBM_2', 'AMDSMI_TEMPERATURE_TYPE_HBM_3',
'AMDSMI_TEMPERATURE_TYPE_HOTSPOT', 'AMDSMI_TEMPERATURE_TYPE_JUNCTION',
'AMDSMI_TEMPERATURE_TYPE_PLX', 'AMDSMI_TEMPERATURE_TYPE_VRAM',
'AMDSMI_TEMPERATURE_TYPE__MAX', 'UNKNOWN', 'AMDSMI_VRAM_TYPE_DDR2',
'AMDSMI_VRAM_TYPE_DDR3', 'AMDSMI_VRAM_TYPE_DDR4', 'AMDSMI_VRAM_TYPE_GDDR1',
'AMDSMI_VRAM_TYPE_GDDR3', 'AMDSMI_VRAM_TYPE_GDDR4', 'AMDSMI_VRAM_TYPE_GDDR5',
'AMDSMI_VRAM_TYPE_GDDR6', 'AMDSMI_VRAM_TYPE_HBM', 'AMDSMI_VRAM_TYPE_UNKNOWN',
'AMDSMI_VRAM_TYPE__MAX', 'WR_BW0', 'amd_metrics_table_header_t',
'amdsmi_asic_info_t', 'amdsmi_bdf_t', 'amdsmi_bit_field_t',
'amdsmi_board_info_t', 'amdsmi_cache_property_type_t',
'amdsmi_card_form_factor_t', 'amdsmi_clk_info_t',
src/amd_smi/amd_smi.cc
+63 -63
View File
@@ -94,7 +94,7 @@ static amdsmi_status_t get_gpu_device_from_handle(amdsmi_processor_handle proces
.handle_to_processor(processor_handle, &device);
if (r != AMDSMI_STATUS_SUCCESS) return r;
if (device->get_processor_type() == AMD_GPU) {
if (device->get_processor_type() == AMDSMI_PROCESSOR_TYPE_AMD_GPU) {
*gpudevice = static_cast<amd::smi::AMDSmiGPUDevice*>(processor_handle);
return AMDSMI_STATUS_SUCCESS;
}
@@ -304,11 +304,11 @@ amdsmi_status_t amdsmi_get_processor_count_from_handles(amdsmi_processor_handle*
&processor_type);
if (r != AMDSMI_STATUS_SUCCESS) return r;
if(processor_type == AMD_CPU) {
if(processor_type == AMDSMI_PROCESSOR_TYPE_AMD_CPU) {
count_cpusockets++;
} else if(processor_type == AMD_CPU_CORE) {
} else if(processor_type == AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE) {
count_cpucores++;
} else if(processor_type == AMD_GPU) {
} else if(processor_type == AMDSMI_PROCESSOR_TYPE_AMD_GPU) {
count_gpus++;
}
}
@@ -538,7 +538,7 @@ amdsmi_status_t amdsmi_get_temp_metric(amdsmi_processor_handle processor_handle
}
// Get the PLX temperature from the gpu_metrics
if (sensor_type == TEMPERATURE_TYPE_PLX) {
if (sensor_type == AMDSMI_TEMPERATURE_TYPE_PLX) {
amdsmi_gpu_metrics_t metric_info;
auto r_status = amdsmi_get_gpu_metrics_info(
processor_handle, &metric_info);
@@ -568,7 +568,7 @@ amdsmi_status_t amdsmi_get_gpu_vram_usage(amdsmi_processor_handle processor_hand
.handle_to_processor(processor_handle, &device);
if (ret != AMDSMI_STATUS_SUCCESS) return ret;
if (device->get_processor_type() != AMD_GPU) {
if (device->get_processor_type() != AMDSMI_PROCESSOR_TYPE_AMD_GPU) {
return AMDSMI_STATUS_NOT_SUPPORTED;
}
@@ -639,27 +639,27 @@ amdsmi_status_t amdsmi_get_gpu_revision(amdsmi_processor_handle processor_handle
amdsmi_status_t amdsmi_get_fw_info(amdsmi_processor_handle processor_handle,
amdsmi_fw_info_t *info) {
const std::map<amdsmi_fw_block_t, rsmi_fw_block_t> fw_in_rsmi = {
{ FW_ID_ASD, RSMI_FW_BLOCK_ASD},
{ FW_ID_CP_CE, RSMI_FW_BLOCK_CE},
{ FW_ID_DMCU, RSMI_FW_BLOCK_DMCU},
{ FW_ID_MC, RSMI_FW_BLOCK_MC},
{ FW_ID_CP_ME, RSMI_FW_BLOCK_ME},
{ FW_ID_CP_MEC1, RSMI_FW_BLOCK_MEC},
{ FW_ID_CP_MEC2, RSMI_FW_BLOCK_MEC2},
{ FW_ID_CP_PFP, RSMI_FW_BLOCK_PFP},
{ FW_ID_RLC, RSMI_FW_BLOCK_RLC},
{ FW_ID_RLC_RESTORE_LIST_CNTL, RSMI_FW_BLOCK_RLC_SRLC},
{ FW_ID_RLC_RESTORE_LIST_GPM_MEM, RSMI_FW_BLOCK_RLC_SRLG},
{ FW_ID_RLC_RESTORE_LIST_SRM_MEM, RSMI_FW_BLOCK_RLC_SRLS},
{ FW_ID_SDMA0, RSMI_FW_BLOCK_SDMA},
{ FW_ID_SDMA1, RSMI_FW_BLOCK_SDMA2},
{ FW_ID_PM, RSMI_FW_BLOCK_SMC},
{ FW_ID_PSP_SOSDRV, RSMI_FW_BLOCK_SOS},
{ FW_ID_TA_RAS, RSMI_FW_BLOCK_TA_RAS},
{ FW_ID_TA_XGMI, RSMI_FW_BLOCK_TA_XGMI},
{ FW_ID_UVD, RSMI_FW_BLOCK_UVD},
{ FW_ID_VCE, RSMI_FW_BLOCK_VCE},
{ FW_ID_VCN, RSMI_FW_BLOCK_VCN}
{ AMDSMI_FW_ID_ASD, RSMI_FW_BLOCK_ASD},
{ AMDSMI_FW_ID_CP_CE, RSMI_FW_BLOCK_CE},
{ AMDSMI_FW_ID_DMCU, RSMI_FW_BLOCK_DMCU},
{ AMDSMI_FW_ID_MC, RSMI_FW_BLOCK_MC},
{ AMDSMI_FW_ID_CP_ME, RSMI_FW_BLOCK_ME},
{ AMDSMI_FW_ID_CP_MEC1, RSMI_FW_BLOCK_MEC},
{ AMDSMI_FW_ID_CP_MEC2, RSMI_FW_BLOCK_MEC2},
{ AMDSMI_FW_ID_CP_PFP, RSMI_FW_BLOCK_PFP},
{ AMDSMI_FW_ID_RLC, RSMI_FW_BLOCK_RLC},
{ AMDSMI_FW_ID_RLC_RESTORE_LIST_CNTL, RSMI_FW_BLOCK_RLC_SRLC},
{ AMDSMI_FW_ID_RLC_RESTORE_LIST_GPM_MEM, RSMI_FW_BLOCK_RLC_SRLG},
{ AMDSMI_FW_ID_RLC_RESTORE_LIST_SRM_MEM, RSMI_FW_BLOCK_RLC_SRLS},
{ AMDSMI_FW_ID_SDMA0, RSMI_FW_BLOCK_SDMA},
{ AMDSMI_FW_ID_SDMA1, RSMI_FW_BLOCK_SDMA2},
{ AMDSMI_FW_ID_PM, RSMI_FW_BLOCK_SMC},
{ AMDSMI_FW_ID_PSP_SOSDRV, RSMI_FW_BLOCK_SOS},
{ AMDSMI_FW_ID_TA_RAS, RSMI_FW_BLOCK_TA_RAS},
{ AMDSMI_FW_ID_TA_XGMI, RSMI_FW_BLOCK_TA_XGMI},
{ AMDSMI_FW_ID_UVD, RSMI_FW_BLOCK_UVD},
{AMDSMI_FW_ID_VCE, RSMI_FW_BLOCK_VCE},
{ AMDSMI_FW_ID_VCN, RSMI_FW_BLOCK_VCN}
};
AMDSMI_CHECK_INIT();
@@ -794,8 +794,8 @@ amdsmi_status_t amdsmi_get_gpu_vram_info(
return r;
// init the info structure with default value
info->vram_type = VRAM_TYPE_UNKNOWN;
info->vram_size_mb = 0;
info->vram_type = AMDSMI_VRAM_TYPE_UNKNOWN;
info->vram_size = 0;
info->vram_vendor = AMDSMI_VRAM_VENDOR__PLACEHOLDER0;
// Only can read vram type from libdrm
@@ -811,8 +811,8 @@ amdsmi_status_t amdsmi_get_gpu_vram_info(
}
// if vram type is greater than the max enum set it to unknown
if (info->vram_type > VRAM_TYPE__MAX)
info->vram_type = VRAM_TYPE_UNKNOWN;
if (info->vram_type > AMDSMI_VRAM_TYPE__MAX)
info->vram_type = AMDSMI_VRAM_TYPE_UNKNOWN;
// map the vendor name to enum
char brand[256];
@@ -843,7 +843,7 @@ amdsmi_status_t amdsmi_get_gpu_vram_info(
r = rsmi_wrapper(rsmi_dev_memory_total_get, processor_handle,
RSMI_MEM_TYPE_VRAM, &total);
if (r == AMDSMI_STATUS_SUCCESS) {
info->vram_size_mb = total / (1024 * 1024);
info->vram_size = total / (1024 * 1024);
}
return AMDSMI_STATUS_SUCCESS;
@@ -1250,7 +1250,7 @@ amdsmi_get_power_cap_info(amdsmi_processor_handle processor_handle,
set_ret_success = true;
info->power_cap = power_cap;
status = smi_amdgpu_get_ranges(gpudevice, CLK_TYPE_GFX,
status = smi_amdgpu_get_ranges(gpudevice, AMDSMI_CLK_TYPE_GFX,
NULL, NULL, &dpm, NULL);
if ((status == AMDSMI_STATUS_SUCCESS) && !set_ret_success)
set_ret_success = true;
@@ -1349,10 +1349,10 @@ amdsmi_status_t amdsmi_get_clk_freq(amdsmi_processor_handle processor_handle,
// nullptr api supported
// Get from gpu_metrics
if (clk_type == CLK_TYPE_VCLK0 ||
clk_type == CLK_TYPE_VCLK1 ||
clk_type == CLK_TYPE_DCLK0 ||
clk_type == CLK_TYPE_DCLK1 ) {
if (clk_type == AMDSMI_CLK_TYPE_VCLK0 ||
clk_type == AMDSMI_CLK_TYPE_VCLK1 ||
clk_type == AMDSMI_CLK_TYPE_DCLK0 ||
clk_type == AMDSMI_CLK_TYPE_DCLK1 ) {
// when f == nullptr -> check if metrics are supported
amdsmi_gpu_metrics_t metric_info;
@@ -1369,19 +1369,19 @@ amdsmi_status_t amdsmi_get_clk_freq(amdsmi_processor_handle processor_handle,
return r_status;
f->num_supported = 1;
if (clk_type == CLK_TYPE_VCLK0) {
if (clk_type == AMDSMI_CLK_TYPE_VCLK0) {
f->current = metric_info_p->current_vclk0;
f->frequency[0] = metric_info_p->average_vclk0_frequency;
}
if (clk_type == CLK_TYPE_VCLK1) {
if (clk_type == AMDSMI_CLK_TYPE_VCLK1) {
f->current = metric_info_p->current_vclk1;
f->frequency[0] = metric_info_p->average_vclk1_frequency;
}
if (clk_type == CLK_TYPE_DCLK0) {
if (clk_type == AMDSMI_CLK_TYPE_DCLK0) {
f->current = metric_info_p->current_dclk0;
f->frequency[0] = metric_info_p->average_dclk0_frequency;
}
if (clk_type == CLK_TYPE_DCLK1) {
if (clk_type == AMDSMI_CLK_TYPE_DCLK1) {
f->current = metric_info_p->current_dclk1;
f->frequency[0] = metric_info_p->average_dclk1_frequency;
}
@@ -1399,10 +1399,10 @@ amdsmi_status_t amdsmi_set_clk_freq(amdsmi_processor_handle processor_handle,
AMDSMI_CHECK_INIT();
// Not support the clock type write into gpu_metrics
if (clk_type == CLK_TYPE_VCLK0 ||
clk_type == CLK_TYPE_VCLK1 ||
clk_type == CLK_TYPE_DCLK0 ||
clk_type == CLK_TYPE_DCLK1 ) {
if (clk_type == AMDSMI_CLK_TYPE_VCLK0 ||
clk_type == AMDSMI_CLK_TYPE_VCLK1 ||
clk_type == AMDSMI_CLK_TYPE_DCLK0 ||
clk_type == AMDSMI_CLK_TYPE_DCLK1 ) {
return AMDSMI_STATUS_NOT_SUPPORTED;
}
@@ -1692,7 +1692,7 @@ amdsmi_get_clock_info(amdsmi_processor_handle processor_handle, amdsmi_clk_type_
return AMDSMI_STATUS_INVAL;
}
if (clk_type > CLK_TYPE__MAX) {
if (clk_type > AMDSMI_CLK_TYPE__MAX) {
return AMDSMI_STATUS_INVAL;
}
@@ -1717,26 +1717,26 @@ amdsmi_get_clock_info(amdsmi_processor_handle processor_handle, amdsmi_clk_type_
}
info->max_clk = max_freq;
info->min_clk = min_freq;
info->sleep_clk = sleep_state_freq;
info->clk_deep_sleep = sleep_state_freq;
switch (clk_type) {
case CLK_TYPE_GFX:
info->cur_clk = metrics.current_gfxclk;
case AMDSMI_CLK_TYPE_GFX:
info->clk = metrics.current_gfxclk;
break;
case CLK_TYPE_MEM:
info->cur_clk = metrics.current_uclk;
case AMDSMI_CLK_TYPE_MEM:
info->clk = metrics.current_uclk;
break;
case CLK_TYPE_VCLK0:
info->cur_clk = metrics.current_vclk0;
case AMDSMI_CLK_TYPE_VCLK0:
info->clk = metrics.current_vclk0;
break;
case CLK_TYPE_VCLK1:
info->cur_clk = metrics.current_vclk1;
case AMDSMI_CLK_TYPE_VCLK1:
info->clk = metrics.current_vclk1;
break;
case CLK_TYPE_DCLK0:
info->cur_clk = metrics.current_dclk0;
case AMDSMI_CLK_TYPE_DCLK0:
info->clk = metrics.current_dclk0;
break;
case CLK_TYPE_DCLK1:
info->cur_clk = metrics.current_dclk1;
case AMDSMI_CLK_TYPE_DCLK1:
info->clk = metrics.current_dclk1;
break;
default:
return AMDSMI_STATUS_INVAL;
@@ -2207,10 +2207,10 @@ amdsmi_status_t amdsmi_get_processor_handle_from_bdf(amdsmi_bdf_t bdf,
return status;
}
amdsmi_bdf_t found_bdf = gpu_device->get_bdf();
if ((bdf.fields.bus_number == found_bdf.fields.bus_number) &&
(bdf.fields.device_number == found_bdf.fields.device_number) &&
(bdf.fields.domain_number == found_bdf.fields.domain_number) &&
(bdf.fields.function_number == found_bdf.fields.function_number)) {
if ((bdf.bus_number == found_bdf.bus_number) &&
(bdf.device_number == found_bdf.device_number) &&
(bdf.domain_number == found_bdf.domain_number) &&
(bdf.function_number == found_bdf.function_number)) {
*processor_handle = devs[idx];
return AMDSMI_STATUS_SUCCESS;
}
src/amd_smi/amd_smi_drm.cc
+4 -4
View File
@@ -173,10 +173,10 @@ amdsmi_status_t AMDSmiDrm::init() {
}
has_valid_fds = true;
bdf.fields.function_number = device->businfo.pci->func;
bdf.fields.device_number = device->businfo.pci->dev;
bdf.fields.bus_number = device->businfo.pci->bus;
bdf.fields.domain_number = device->businfo.pci->domain;
bdf.function_number = device->businfo.pci->func;
bdf.device_number = device->businfo.pci->dev;
bdf.bus_number = device->businfo.pci->bus;
bdf.domain_number = device->businfo.pci->domain;
vendor_id = device->deviceinfo.pci->vendor_id;
src/amd_smi/amd_smi_socket.cc
+3 -3
View File
@@ -71,13 +71,13 @@ amdsmi_status_t AMDSmiSocket::get_processor_count(uint32_t* processor_count) con
amdsmi_status_t AMDSmiSocket::get_processor_count(processor_type_t type, uint32_t* processor_count) const {
amdsmi_status_t ret = AMDSMI_STATUS_SUCCESS;
switch (type) {
case AMD_GPU:
case AMDSMI_PROCESSOR_TYPE_AMD_GPU:
*processor_count = static_cast<uint32_t>(processors_.size());
break;
case AMD_CPU:
case AMDSMI_PROCESSOR_TYPE_AMD_CPU:
*processor_count = static_cast<uint32_t>(cpu_processors_.size());
break;
case AMD_CPU_CORE:
case AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE:
*processor_count = static_cast<uint32_t>(cpu_core_processors_.size());
break;
default:
src/amd_smi/amd_smi_system.cc
+3 -3
View File
@@ -162,12 +162,12 @@ amdsmi_status_t AMDSmiSystem::populate_amd_cpus() {
socket = new AMDSmiSocket(cpu_socket_id);
sockets_.push_back(socket);
}
AMDSmiProcessor* cpusocket = new AMDSmiProcessor(AMD_CPU, i);
AMDSmiProcessor* cpusocket = new AMDSmiProcessor(AMDSMI_PROCESSOR_TYPE_AMD_CPU, i);
socket->add_processor(cpusocket);
processors_.insert(cpusocket);
for (uint32_t k = 0; k < (cpus/threads)/sockets; k++) {
AMDSmiProcessor* core = new AMDSmiProcessor(AMD_CPU_CORE, k);
AMDSmiProcessor* core = new AMDSmiProcessor(AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE, k);
socket->add_processor(core);
processors_.insert(core);
}
@@ -322,7 +322,7 @@ amdsmi_status_t AMDSmiSystem::gpu_index_to_handle(uint32_t gpu_index,
auto iter = processors_.begin();
for (; iter != processors_.end(); iter++) {
auto cur_device = (*iter);
if (cur_device->get_processor_type() != AMD_GPU)
if (cur_device->get_processor_type() != AMDSMI_PROCESSOR_TYPE_AMD_GPU)
continue;
amd::smi::AMDSmiGPUDevice* gpu_device =
static_cast<amd::smi::AMDSmiGPUDevice*>(cur_device);
src/amd_smi/amd_smi_utils.cc
+6 -6
View File
@@ -256,22 +256,22 @@ amdsmi_status_t smi_amdgpu_get_ranges(amd::smi::AMDSmiGPUDevice* device, amdsmi_
std::string fullpath = "/sys/class/drm/" + device->get_gpu_path() + "/device";
switch (domain) {
case CLK_TYPE_GFX:
case AMDSMI_CLK_TYPE_GFX:
fullpath += "/pp_dpm_sclk";
break;
case CLK_TYPE_MEM:
case AMDSMI_CLK_TYPE_MEM:
fullpath += "/pp_dpm_mclk";
break;
case CLK_TYPE_VCLK0:
case AMDSMI_CLK_TYPE_VCLK0:
fullpath += "/pp_dpm_vclk";
break;
case CLK_TYPE_VCLK1:
case AMDSMI_CLK_TYPE_VCLK1:
fullpath += "/pp_dpm_vclk1";
break;
case CLK_TYPE_DCLK0:
case AMDSMI_CLK_TYPE_DCLK0:
fullpath += "/pp_dpm_dclk";
break;
case CLK_TYPE_DCLK1:
case AMDSMI_CLK_TYPE_DCLK1:
fullpath += "/pp_dpm_dclk1";
break;
default:
src/amd_smi/fdinfo.cc
+10 -10
View File
@@ -34,8 +34,8 @@
extern "C" {
static const char *container_type_name[AMDSMI_MAX_CONTAINER_TYPE] = {
[CONTAINER_LXC] = "lxc",
[CONTAINER_DOCKER] = "docker",
[AMDSMI_CONTAINER_LXC] = "lxc",
[AMDSMI_CONTAINER_DOCKER] = "docker",
};
amdsmi_status_t gpuvsmi_pid_is_gpu(const std::string &path, const char *bdf)
@@ -74,10 +74,10 @@ amdsmi_status_t gpuvsmi_get_pids(const amdsmi_bdf_t &bdf, std::vector<long int>
/* 0000:00:00.0 */
snprintf(bdf_str, 13, "%04x:%02x:%02x.%d",
bdf.fields.domain_number & 0xffff,
bdf.fields.bus_number & 0xff,
bdf.fields.device_number & 0x1f,
bdf.fields.function_number & 0x7);
bdf.domain_number & 0xffff,
bdf.bus_number & 0xff,
bdf.device_number & 0x1f,
bdf.function_number & 0x7);
d = opendir("/proc");
if (!d)
@@ -123,10 +123,10 @@ amdsmi_status_t gpuvsmi_get_pid_info(const amdsmi_bdf_t &bdf, long int pid,
/* 0000:00:00.0 */
snprintf(bdf_str, 13, "%04x:%02x:%02x.%d",
bdf.fields.domain_number & 0xffff,
bdf.fields.bus_number & 0xff,
bdf.fields.device_number & 0x1f,
bdf.fields.function_number & 0x7);
bdf.domain_number & 0xffff,
bdf.bus_number & 0xff,
bdf.device_number & 0x1f,
bdf.function_number & 0x7);
std::string path = "/proc/" + std::to_string(pid) + "/fdinfo/";
tests/amd_smi_test/functional/frequencies_read.cc
+5 -5
View File
@@ -158,11 +158,11 @@ void TestFrequenciesRead::Run(void) {
PrintDeviceHeader(processor_handles_[i]);
freq_output(CLK_TYPE_MEM, "Supported GPU Memory");
freq_output(CLK_TYPE_SYS, "Supported GPU");
freq_output(CLK_TYPE_DF, "Data Fabric Clock");
freq_output(CLK_TYPE_DCEF, "Display Controller Engine Clock");
freq_output(CLK_TYPE_SOC, "SOC Clock");
freq_output(AMDSMI_CLK_TYPE_MEM, "Supported GPU Memory");
freq_output(AMDSMI_CLK_TYPE_SYS, "Supported GPU");
freq_output(AMDSMI_CLK_TYPE_DF, "Data Fabric Clock");
freq_output(AMDSMI_CLK_TYPE_DCEF, "Display Controller Engine Clock");
freq_output(AMDSMI_CLK_TYPE_SOC, "SOC Clock");
err = amdsmi_get_gpu_pci_bandwidth(processor_handles_[i], &b);
if (err == AMDSMI_STATUS_NOT_SUPPORTED) {
tests/amd_smi_test/functional/frequencies_read_write.cc
+5 -5
View File
@@ -104,13 +104,13 @@ void TestFrequenciesReadWrite::Run(void) {
for (uint32_t dv_ind = 0; dv_ind < num_monitor_devs(); ++dv_ind) {
PrintDeviceHeader(processor_handles_[dv_ind]);
for (uint32_t clk = CLK_TYPE_FIRST; clk <= CLK_TYPE__MAX; ++clk) {
for (uint32_t clk = AMDSMI_CLK_TYPE_FIRST; clk <= AMDSMI_CLK_TYPE__MAX; ++clk) {
amdsmi_clk = (amdsmi_clk_type_t)clk;
auto freq_read = [&]() -> bool {
// Skip CLK_TYPE_PCIE, which does not supported in rocm-smi.
// Skip AMDSMI_CLK_TYPE_PCIE, which does not supported in rocm-smi.
std::cout << amdsmi_clk << std::endl;
if (amdsmi_clk == CLK_TYPE_PCIE)
if (amdsmi_clk == AMDSMI_CLK_TYPE_PCIE)
return false;
ret = amdsmi_get_clk_freq(processor_handles_[dv_ind], amdsmi_clk, &f);
std::cout << ret << std::endl;
@@ -139,8 +139,8 @@ void TestFrequenciesReadWrite::Run(void) {
auto freq_write = [&]() {
// Set clocks to something other than the usual default of the lowest
// frequency.
// Skip CLK_TYPE_PCIE, which does not supported in rocm-smi.
if (amdsmi_clk == CLK_TYPE_PCIE)
// Skip AMDSMI_CLK_TYPE_PCIE, which does not supported in rocm-smi.
if (amdsmi_clk == AMDSMI_CLK_TYPE_PCIE)
return;
freq_bitmask = 0b01100; // Try the 3rd and 4th clocks
tests/amd_smi_test/functional/id_info_read.cc
+1 -1
View File
@@ -155,7 +155,7 @@ void TestIdInfoRead::Run(void) {
std::cout << "\t**Device Vram vendor id: "
<< vram_info.vram_vendor << std::endl;
std::cout << "\t**Device Vram size: "
<< vram_info.vram_size_mb << std::endl;
<< vram_info.vram_size << std::endl;
}
err = amdsmi_get_gpu_vendor_name(processor_handles_[i], buffer, kBufferLen);
tests/amd_smi_test/functional/mutual_exclusion.cc
+3 -3
View File
@@ -229,7 +229,7 @@ void TestMutualExclusion::Run(void) {
CHECK_RET(ret, AMDSMI_STATUS_BUSY);
ret = amdsmi_get_gpu_fan_speed_max(processor_handles_[0], 0, &dmy_ui64);
CHECK_RET(ret, AMDSMI_STATUS_BUSY);
ret = amdsmi_get_temp_metric(processor_handles_[0], TEMPERATURE_TYPE_EDGE, AMDSMI_TEMP_CURRENT, &dmy_i64);
ret = amdsmi_get_temp_metric(processor_handles_[0], AMDSMI_TEMPERATURE_TYPE_EDGE, AMDSMI_TEMP_CURRENT, &dmy_i64);
CHECK_RET(ret, AMDSMI_STATUS_BUSY);
ret = amdsmi_reset_gpu_fan(processor_handles_[0], 0);
CHECK_RET(ret, AMDSMI_STATUS_BUSY);
@@ -239,13 +239,13 @@ void TestMutualExclusion::Run(void) {
CHECK_RET(ret, AMDSMI_STATUS_BUSY);
ret = amdsmi_get_gpu_overdrive_level(processor_handles_[0], &dmy_ui32);
CHECK_RET(ret, AMDSMI_STATUS_BUSY);
ret = amdsmi_get_clk_freq(processor_handles_[0], CLK_TYPE_SYS, &dmy_freqs);
ret = amdsmi_get_clk_freq(processor_handles_[0], AMDSMI_CLK_TYPE_SYS, &dmy_freqs);
CHECK_RET(ret, AMDSMI_STATUS_BUSY);
ret = amdsmi_get_gpu_od_volt_info(processor_handles_[0], &dmy_od_volt);
CHECK_RET(ret, AMDSMI_STATUS_BUSY);
ret = amdsmi_get_gpu_od_volt_curve_regions(processor_handles_[0], &dmy_ui32, &dmy_vlt_reg);
CHECK_RET(ret, AMDSMI_STATUS_BUSY);
ret = amdsmi_set_clk_freq(processor_handles_[0], CLK_TYPE_SYS, 0);
ret = amdsmi_set_clk_freq(processor_handles_[0], AMDSMI_CLK_TYPE_SYS, 0);
CHECK_RET(ret, AMDSMI_STATUS_BUSY);
ret = amdsmi_get_gpu_ecc_count(processor_handles_[0], AMDSMI_GPU_BLOCK_UMC, &dmy_err_cnt);
CHECK_RET(ret, AMDSMI_STATUS_BUSY);
tests/amd_smi_test/functional/temp_read.cc
+10 -10
View File
@@ -57,15 +57,15 @@
static const std::map<uint32_t, std::string> kTempSensorNameMap = {
{TEMPERATURE_TYPE_VRAM, "Memory"},
{TEMPERATURE_TYPE_HOTSPOT, "Hotspot"},
{TEMPERATURE_TYPE_JUNCTION, "Junction"},
{TEMPERATURE_TYPE_EDGE, "Edge"},
{TEMPERATURE_TYPE_HBM_0, "HBM_0"},
{TEMPERATURE_TYPE_HBM_1, "HBM_1"},
{TEMPERATURE_TYPE_HBM_2, "HBM_2"},
{TEMPERATURE_TYPE_HBM_3, "HBM_3"},
{TEMPERATURE_TYPE_PLX, "PLX"}
{AMDSMI_TEMPERATURE_TYPE_VRAM, "Memory"},
{AMDSMI_TEMPERATURE_TYPE_HOTSPOT, "Hotspot"},
{AMDSMI_TEMPERATURE_TYPE_JUNCTION, "Junction"},
{AMDSMI_TEMPERATURE_TYPE_EDGE, "Edge"},
{AMDSMI_TEMPERATURE_TYPE_HBM_0, "HBM_0"},
{AMDSMI_TEMPERATURE_TYPE_HBM_1, "HBM_1"},
{AMDSMI_TEMPERATURE_TYPE_HBM_2, "HBM_2"},
{AMDSMI_TEMPERATURE_TYPE_HBM_3, "HBM_3"},
{AMDSMI_TEMPERATURE_TYPE_PLX, "PLX"}
};
TestTempRead::TestTempRead() : TestBase() {
set_title("AMDSMI Temp Read Test");
@@ -141,7 +141,7 @@ void TestTempRead::Run(void) {
"C" << std::endl;
}
};
for (type = TEMPERATURE_TYPE_FIRST; type <= TEMPERATURE_TYPE__MAX; ++type) {
for (type = AMDSMI_TEMPERATURE_TYPE_FIRST; type <= AMDSMI_TEMPERATURE_TYPE__MAX; ++type) {
IF_VERB(STANDARD) {
std::cout << "\t** **********" << kTempSensorNameMap.at(type) <<
" Temperatures **********" << std::endl;
tests/amd_smi_test/test_common.cc
+11 -11
View File
@@ -220,19 +220,19 @@ const std::string GetVoltSensorNameStr(amdsmi_voltage_type_t st) {
return kVoltSensorNameMap.at(st);
}
const char *FreqEnumToStr(amdsmi_clk_type_t amdsmi_clk) {
static_assert(CLK_TYPE__MAX == CLK_TYPE_DCLK1,
static_assert(AMDSMI_CLK_TYPE__MAX == AMDSMI_CLK_TYPE_DCLK1,
"FreqEnumToStr() needs to be updated");
switch (amdsmi_clk) {
case CLK_TYPE_SYS: return "System clock";
case CLK_TYPE_DF: return "Data Fabric clock";
case CLK_TYPE_DCEF: return "Display Controller Engine clock";
case CLK_TYPE_SOC: return "SOC clock";
case CLK_TYPE_MEM: return "Memory clock";
case CLK_TYPE_PCIE: return "PCIE clock";
case CLK_TYPE_VCLK0: return "VCLK0 clock";
case CLK_TYPE_VCLK1: return "VCLK1 clock";
case CLK_TYPE_DCLK0: return "DCLK0 clock";
case CLK_TYPE_DCLK1: return "DCLK1 clock";
case AMDSMI_CLK_TYPE_SYS: return "System clock";
case AMDSMI_CLK_TYPE_DF: return "Data Fabric clock";
case AMDSMI_CLK_TYPE_DCEF: return "Display Controller Engine clock";
case AMDSMI_CLK_TYPE_SOC: return "SOC clock";
case AMDSMI_CLK_TYPE_MEM: return "Memory clock";
case AMDSMI_CLK_TYPE_PCIE: return "PCIE clock";
case AMDSMI_CLK_TYPE_VCLK0: return "VCLK0 clock";
case AMDSMI_CLK_TYPE_VCLK1: return "VCLK1 clock";
case AMDSMI_CLK_TYPE_DCLK0: return "DCLK0 clock";
case AMDSMI_CLK_TYPE_DCLK1: return "DCLK1 clock";
default: return "Invalid Clock ID";
}
}
tests/amd_smi_test/test_utils.cc
+22 -22
View File
@@ -49,28 +49,28 @@
#include "test_utils.h"
static const std::map<amdsmi_fw_block_t, const char *> kDevFWNameMap = {
{FW_ID_ASD, "asd"},
{FW_ID_CP_CE, "ce"},
{FW_ID_DMCU_ERAM, "dmcu"}, // TODO(bliu): double check
{FW_ID_MC, "mc"},
{FW_ID_CP_ME, "me"},
{FW_ID_CP_MEC1, "mec1"},
{FW_ID_CP_MEC2, "mec2"},
{FW_ID_CP_MES, "mes"},
{FW_ID_MES_KIQ, "mes_kiq"}, // TODO: double check
{FW_ID_CP_PFP, "pfp"},
{FW_ID_RLC, "rlc"},
{FW_ID_RLC_SRLG, "rlc_srlg"},
{FW_ID_RLC_SRLS, "rlc_srls"},
{FW_ID_SDMA1, "sdma1"},
{FW_ID_SDMA2, "sdma2"},
{FW_ID_PM, "pm"},
{FW_ID_PSP_SOSDRV, "sos"},
{FW_ID_TA_RAS, "ta_ras"},
{FW_ID_TA_XGMI, "ta_xgmi"},
{FW_ID_UVD, "uvd"},
{FW_ID_VCE, "vce"},
{FW_ID_VCN, "vcn"},
{AMDSMI_FW_ID_ASD, "asd"},
{AMDSMI_FW_ID_CP_CE, "ce"},
{AMDSMI_FW_ID_DMCU_ERAM, "dmcu"}, // TODO(bliu): double check
{AMDSMI_FW_ID_MC, "mc"},
{AMDSMI_FW_ID_CP_ME, "me"},
{AMDSMI_FW_ID_CP_MEC1, "mec1"},
{AMDSMI_FW_ID_CP_MEC2, "mec2"},
{AMDSMI_FW_ID_CP_MES, "mes"},
{AMDSMI_FW_ID_MES_KIQ, "mes_kiq"}, // TODO: double check
{AMDSMI_FW_ID_CP_PFP, "pfp"},
{AMDSMI_FW_ID_RLC, "rlc"},
{AMDSMI_FW_ID_RLC_SRLG, "rlc_srlg"},
{AMDSMI_FW_ID_RLC_SRLS, "rlc_srls"},
{AMDSMI_FW_ID_SDMA1, "sdma1"},
{AMDSMI_FW_ID_SDMA2, "sdma2"},
{AMDSMI_FW_ID_PM, "pm"},
{AMDSMI_FW_ID_PSP_SOSDRV, "sos"},
{AMDSMI_FW_ID_TA_RAS, "ta_ras"},
{AMDSMI_FW_ID_TA_XGMI, "ta_xgmi"},
{AMDSMI_FW_ID_UVD, "uvd"},
{AMDSMI_FW_ID_VCE, "vce"},
{AMDSMI_FW_ID_VCN, "vcn"},
};
const char *