Update csv headers, and SystemExit codes

Signed-off-by: JoseSantosAMD <Jose.Santos@amd.com> [ROCm/rocprofiler-compute commit: 717a21cf84]
2024-02-02 20:04:11 -06:00
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBuffer.kd,0,0,0,861653,861658,33554432,256,0,0,8,32,6464,0x0,0x7fa2ed804180,4017616,3811368,57010570,524288,365706290,502201,502201,57581369,55291458,172,12242759,0,0,0,1048576,67108864,67108864,0,67108864,0,0,360,33554432,15326,16608774,0,16777216,641000253,0,2809786101,0,8388608,0,0,0,0,0,0,0,0,0,0,0,0,8388608,0,42066228,12075111806057902,12075122867722970,12075122868048567,12075112052782898
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,861653,861658,32768,256,0,0,24,24,12480,0x0,0x7fa2ed835100,226960,75885,1058218,512,1129881,28369,28369,1525247,590890,223,123973,0,0,0,4096,65536,65536,65536,0,0,0,360,16384,120,15064,0,16384,13651060,18072802,0,8192,0,0,0,0,0,0,0,0,0,0,0,0,8192,0,0,433075,12075112067269329,12075122883005681,12075122883012241,12075112067789165
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,861653,861658,4194304,256,0,0,24,24,12928,0x7fa3f9496900,0x7fa2ed835140,1851568,1678532,24917394,65536,123263676,231445,231445,25593587,24315118,28167,4305461,0,0,0,524288,8388608,8388608,8388608,0,0,0,360,2097152,7590,2017879,0,2097152,1001448598,1625054991,0,2097152,0,0,0,0,0,0,0,0,0,0,0,0,2097152,0,0,16241328,12075112068132513,12075122883073521,12075122883205199,12075112068769106
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,6055155.0,6055155.0,6055155.0,9.183478194506762
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4526687.0,4526687.0,4526687.0,6.86534553745647
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 256u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,3053577.0,3053577.0,3053577.0,4.631170927044374
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,33617.4255854441,2790.1175689697266,547908.5648803711,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,24.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,29.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBuffer.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,23070.72,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,23070.72,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,4614.144,
 Scalar L1D Cache Hit Rate,,Pct,100,
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,23.976047904191617,8,36,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBuffer.kd",0,0,0,861981,861986,33554432,256,0,0,8,32,6464,0x0,0x7fbb92a04180,12075122867675859,12075122867722970,12075122868048567,12075122868154970
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,861981,861986,32768,256,0,0,24,24,12480,0x0,0x7fbb92a35100,12075122882900422,12075122883005681,12075122883012241,12075122883018001
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,4,861981,861986,4194304,256,0,0,24,24,12928,0x7fbcc2b2b900,0x7fbb92a35140,12075122883060480,12075122883073521,12075122883205199,12075122883208515
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,__amd_rocclr_fillBufferAligned.kd,0,0,0,151449,151449,33554432,256,0,0,4,32,4160,0x0,0x7f022a604280,3076512,2989574,38842013,524288,242121889,384563,384563,39106410.0,38083768.0,3.0,4067115.0,0.0,0.0,0.0,524288.0,33554432.0,33554432.0,0.0,33554432.0,0.0,0.0,104.0,8388608.0,13284.0,8242484.0,0.0,8388608.0,313264439.0,0.0,1463068751.0,0.0,4194304.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,4194304.0,0.0,19128712.0,16219564975519,16227562900659,16227563139060,16219710251567
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,151449,151449,32768,256,0,0,12,24,13888,0x0,0x7f022a623f80,265008,169056,1410267,512,1756157,33125,33125,2433904.0,174869.0,208.0,0.0,0.0,0.0,0.0,4096.0,65536.0,65536.0,65536.0,0.0,0.0,0.0,104.0,16384.0,104.0,15240.0,0.0,16384.0,3868580.0,5430964.0,0.0,8192.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,8192.0,0.0,0.0,124860.0,16219715974101,16227567936047,16227567949487,16219716213625
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,151449,151449,4194304,256,0,0,12,24,14336,0x7f022d5aa380,0x7f022a623fc0,1390672,1257890,16244343,65536,95138833,173833,173833,16588733.0,13862093.0,23826.0,680816.0,0.0,0.0,0.0,524288.0,8388608.0,8388608.0,8388608.0,0.0,0.0,0.0,208.0,2097152.0,6560.0,2028965.0,0.0,2097152.0,894852738.0,2174316602.0,0.0,2097152.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,2097152.0,0.0,0.0,11602704.0,16219716751753,16227568019567,16227568112208,16219717067306
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3357619.0,3357619.0,3357619.0,7.844741995405001
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1724810.0,1724810.0,1724810.0,4.029846579106951
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1716969.0,1716969.0,1716969.0,4.011526864456191
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,,Instr per wave
 VMEM,,Instr per wave
-LDS,,Instr per wave
+LDS_Per_Workgroup,,Instr per wave
 VALU - MFMA,,Instr per wave
 SALU,,Instr per wave
 SMEM,,Instr per wave
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18369.813897641117,1847.2434158325195,257897.74127197266,Cycles/wave
-LDS Instrs,,,,Instr per wave
+LDS_Per_Workgroup Instrs,,,,Instr per wave
 Bandwidth,,,,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,,,,Cycles per wave
+Dispatch_ID Accesses,,,,Cycles per wave
 Atomic Cycles,,,,Cycles per wave
 Bank Conflict,,,,Cycles per wave
 Addr Conflict,,,,Cycles per wave
 Unaligned Stall,,,,Cycles per wave
 Mem Violations,,,, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
@@ -6,16 +6,16 @@ SMEM,,smem_
 VALU,,valu_
 MFMA,,mfma_
 VMEM,,vmem_
-LDS,,lds_
+LDS_Per_Workgroup,,lds_
 GWS,,gws_
 BR,,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,,wavefronts_
 Workgroups,,workgroups_
-LDS Req,,lds_req_
+LDS_Per_Workgroup Req,,lds_req_
 IL1 Fetch,,il1_fetch_
 IL1 Hit,,il1_hit_
 IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
 Fabric_l2 Atomic,,l2_fabric_atom_
 HBM Rd,,hbm_rd_
 HBM Wr,,hbm_wr_
-LDS Util,,lds_util_
+LDS_Per_Workgroup Util,,lds_util_
 VL1 Coalesce,,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,,wave_occ_
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
 MFMA Util,,Pct,100,
 VALU Active Threads/Wave,,Threads,64,
 IPC - Issue,,Instr/cycle,5,
-LDS BW,,Gb/sec,22630.4,
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,,Gb/sec,22630.4,
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,,Pct,100,
 Instr Cache BW,,Gb/s,6092.8,
 Scalar L1D Cache Hit Rate,,Pct,100,
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
 Insufficient SIMD Waveslots,,,,Simd
 Insufficient SIMD VGPRs,,,,Simd
 Insufficient SIMD SGPRs,,,,Simd
-Insufficient CU LDS,,,,Cu
+Insufficient CU LDS_Per_Workgroup,,,,Cu
 Insufficient CU Barries,,,,Cu
 Insufficient Bulky Resource,,,,Cu
 Reach CU Threadgroups Limit,,,,Cycles
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
 Restored Wavefronts,,,,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,DispatchNs,BeginNs,EndNs,CompleteNs
+Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
 0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,151766,151766,33554432,256,0,0,4,32,4160,0x0,0x7fde9d204280,16227562875467,16227562900659,16227563139060,16227563229520
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,151766,151766,32768,256,0,0,12,24,13888,0x0,0x7fde9d223f80,16227567920646,16227567936047,16227567949487,16227567968405
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,151766,151766,4194304,256,0,0,12,24,14336,0x7fdea01c0380,0x7fde9d223fc0,16227567970275,16227568019567,16227568112208,16227568114092