Update csv headers, and SystemExit codes

Signed-off-by: JoseSantosAMD <Jose.Santos@amd.com> [ROCm/rocprofiler-compute commit: 717a21cf84]
2024-02-02 20:04:11 -06:00
parent 595ca9141a
commit 8ecc6dff7f
2842 changed files with 5653 additions and 3927 deletions
@@ -1,4 +1,4 @@
-KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
+Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
 "void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,3357122.0,3357122.0,3357122.0,7.840630919671416
 "void benchmark_func<HIP_vector_type<float, 2u>, 256, 8u, 512u>(HIP_vector_type<float, 2u>, HIP_vector_type<float, 2u>*) [clone .kd]",1,1724001.0,1724001.0,1724001.0,4.026441560999106
 "void benchmark_func<double, 256, 8u, 512u>(double, double*) [clone .kd]",1,1714881.0,1714881.0,1714881.0,4.005141604075466
@@ -1,7 +1,7 @@
 Metric,Count,Unit
 VALU - Vector,494.8622754491018,Instr per wave
 VMEM,7.958083832335329,Instr per wave
-LDS,0.0,Instr per wave
+LDS_Per_Workgroup,0.0,Instr per wave
 VALU - MFMA,0.0,Instr per wave
 SALU,24.520958083832337,Instr per wave
 SMEM,1.8023952095808384,Instr per wave
@@ -23,4 +23,4 @@ gfx90a
 mi200
 56
 1638.4
-roofline|SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
+roofline|SQ|LDS_Per_Workgroup|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
@@ -1,12 +1,12 @@
 Metric,Avg,Min,Max,Unit
 Wave Cycles,18296.269474052384,1894.2776184082031,258229.23516845703,Cycles/wave
-LDS Instrs,0.0,0.0,0.0,Instr per wave
+LDS_Per_Workgroup Instrs,0.0,0.0,0.0,Instr per wave
 Bandwidth,0.0,0.0,0.0,Bytes per wave
 Bank Conficts/Access,,,,Conflicts/access
-Index Accesses,0.0,0.0,0.0,Cycles per wave
+Dispatch_ID Accesses,0.0,0.0,0.0,Cycles per wave
 Atomic Cycles,0.0,0.0,0.0,Cycles per wave
 Bank Conflict,0.0,0.0,0.0,Cycles per wave
 Addr Conflict,0.0,0.0,0.0,Cycles per wave
 Unaligned Stall,0.0,0.0,0.0,Cycles per wave
 Mem Violations,0.0,0.0,0.0, per wave
-LDS Latency,,,,Cycles
+LDS_Per_Workgroup Latency,,,,Cycles
@@ -6,16 +6,16 @@ SMEM,2.0,smem_
 VALU,495.0,valu_
 MFMA,0.0,mfma_
 VMEM,8.0,vmem_
-LDS,0.0,lds_
+LDS_Per_Workgroup,0.0,lds_
 GWS,0.0,gws_
 BR,10.0,br_
 VGPR,12.0,vgpr_
 SGPR,24.0,sgpr_
-LDS Allocation,0.0,lds_alloc_
+LDS_Per_Workgroup Allocation,0.0,lds_alloc_
 Scratch Allocation,0.0,scratch_alloc_
 Wavefronts,67894.0,wavefronts_
 Workgroups,16973.0,workgroups_
-LDS Req,0.0,lds_req_
+LDS_Per_Workgroup Req,0.0,lds_req_
 IL1 Fetch,128.0,il1_fetch_
 IL1 Hit,100.0,il1_hit_
 IL1_L2 Rd,0.0,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,0.0,l2_fabric_wr_
 Fabric_l2 Atomic,0.0,l2_fabric_atom_
 HBM Rd,44.0,hbm_rd_
 HBM Wr,0.0,hbm_wr_
-LDS Util,0.0,lds_util_
+LDS_Per_Workgroup Util,0.0,lds_util_
 VL1 Coalesce,70.0,vl1_coales_
 VL1 Stall,2.0,vl1_stall_
-LDS Lat,,lds_lat_
+LDS_Per_Workgroup Lat,,lds_lat_
 vL1D Lat,,sl1_lat_
 IL1 Lat,,il1_lat_
 Wave Occupancy,25.0,wave_occ_
@@ -1,4 +1,4 @@
-Index,KernelName,gpu-id
+Dispatch_ID,Kernel_Name,GPU_ID
 0,__amd_rocclr_fillBufferAligned.kd,0
 1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
 2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
@@ -12,8 +12,8 @@ VALU Util,58.3677767471036,Pct,100,58.3677767471036
 MFMA Util,0.0,Pct,100,0.0
 VALU Active Threads/Wave,64.0,Threads,64,100.0
 IPC - Issue,1.0,Instr/cycle,5,20.0
-LDS BW,0.0,Gb/sec,22630.4,0.0
-LDS Bank Conflict,,Conflicts/access,32,
+LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
+LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
 Instr Cache Hit Rate,99.99259859947313,Pct,100,99.99259859947313
 Instr Cache BW,1671.978257589768,Gb/s,6092.8,27.441870036596768
 Scalar L1D Cache Hit Rate,99.3485588612334,Pct,100,99.3485588612334
@@ -6,7 +6,7 @@ Scratch Stall,0.0,0,0,Cycles
 Insufficient SIMD Waveslots,12526180.185628742,0,370304750,Simd
 Insufficient SIMD VGPRs,0.0,0,0,Simd
 Insufficient SIMD SGPRs,0.0,0,0,Simd
-Insufficient CU LDS,0.0,0,0,Cu
+Insufficient CU LDS_Per_Workgroup,0.0,0,0,Cu
 Insufficient CU Barries,0.0,0,0,Cu
 Insufficient Bulky Resource,0.0,0,0,Cu
 Reach CU Threadgroups Limit,0.0,0,0,Cycles
@@ -6,5 +6,5 @@ Saved Wavefronts,0.0,0,0,Wavefronts
 Restored Wavefronts,0.0,0,0,Wavefronts
 VGPRs,11.784431137724551,4,16,Registers
 SGPRs,24.047904191616766,24,32,Registers
-LDS Allocation,0.0,0,0,Bytes
+LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
 Scratch Allocation,0.0,0,0,Bytes