Update csv headers, and SystemExit codes

Signed-off-by: JoseSantosAMD <Jose.Santos@amd.com>


[ROCm/rocprofiler-compute commit: 717a21cf84]
This commit is contained in:
JoseSantosAMD
2024-02-02 20:04:11 -06:00
committed by Karl W. Schulz
parent 595ca9141a
commit 8ecc6dff7f
2842 changed files with 5653 additions and 3927 deletions
@@ -1,4 +1,4 @@
Index,KernelName,gpu-id
Dispatch_ID,Kernel_Name,GPU_ID
0,__amd_rocclr_fillBufferAligned.kd,0
1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
1 Index Dispatch_ID KernelName Kernel_Name gpu-id GPU_ID
2 0 __amd_rocclr_fillBufferAligned.kd 0
3 1 void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd] 0
4 2 void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd] 0
@@ -1,4 +1,4 @@
Index,KernelName,gpu-id,queue-id,queue-index,pid,tid,grd,wgr,lds,scr,vgpr,sgpr,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,BeginNs,EndNs,CompleteNs
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,grd,Workgroup_Size,LDS_Per_Workgroup,scr,vgpr,SGPR,fbar,sig,obj,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,TCP_TCC_READ_REQ_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RDREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WRREQ_sum,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,SQ_LDS_IDX_ACTIVE,SQ_LDS_BANK_CONFLICT,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
0,"__amd_rocclr_fillBufferAligned.kd",0,0,0,241894,241894,33554432,256,0,0,4,32,4160,0x0,0x7f6e9cc04280,0,0,0,0,0,0,0,0,0.0000000000,8388608.0000000000,4194304.0000000000,0.0000000000,0.0000000000,310.0000000000,4128768.0000000000,4128768.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17931286038190,17901582538237,17931431845031,17931431958331
1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0,0,2,241894,241894,32768,256,0,0,12,24,13888,0x0,0x7f6e9cc23f80,0,0,0,0,0,0,0,0,8192.0000000000,16384.0000000000,0.0000000000,0.0000000000,0.0000000000,8262.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17931437652391,17931431845031,17931438008283,17931438016542
2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0,0,5,241894,241894,4194304,256,0,0,12,24,14336,0x7f6e9fb92380,0x7f6e9cc23fc0,0,0,0,0,0,0,262144,0,2097152.0000000000,2097152.0000000000,0.0000000000,0.0000000000,0.0000000000,2097343.0000000000,0.0000000000,0.0000000000,0,0,0,0,0,0,0,0,0.0000000000,0,0,17931438610067,17931438008283,17931439296934,17931439297600
1 Index Dispatch_ID KernelName Kernel_Name gpu-id GPU_ID queue-id queue-index pid tid grd wgr Workgroup_Size lds LDS_Per_Workgroup scr vgpr sgpr SGPR fbar sig obj SQ_INSTS_VALU_ADD_F16 SQ_INSTS_VALU_MUL_F16 SQ_INSTS_VALU_FMA_F16 SQ_INSTS_VALU_TRANS_F16 SQ_INSTS_VALU_ADD_F32 SQ_INSTS_VALU_MUL_F32 SQ_INSTS_VALU_FMA_F32 SQ_INSTS_VALU_TRANS_F32 TCP_TCC_READ_REQ_sum TCP_TOTAL_CACHE_ACCESSES_sum TCP_TCC_WRITE_REQ_sum TCP_TCC_ATOMIC_WITH_RET_REQ_sum TCC_EA_RDREQ_32B_sum TCC_EA_RDREQ_sum TCC_EA_WRREQ_64B_sum TCC_EA_WRREQ_sum SQ_INSTS_VALU_ADD_F64 SQ_INSTS_VALU_MUL_F64 SQ_INSTS_VALU_FMA_F64 SQ_INSTS_VALU_TRANS_F64 SQ_INSTS_VALU_MFMA_MOPS_F16 SQ_INSTS_VALU_MFMA_MOPS_BF16 SQ_INSTS_VALU_MFMA_MOPS_F32 SQ_INSTS_VALU_MFMA_MOPS_F64 TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum SQ_LDS_IDX_ACTIVE SQ_LDS_BANK_CONFLICT DispatchNs BeginNs Start_Timestamp EndNs End_Timestamp CompleteNs
2 0 __amd_rocclr_fillBufferAligned.kd 0 0 0 241894 241894 33554432 256 0 0 4 32 4160 0x0 0x7f6e9cc04280 0 0 0 0 0 0 0 0 0.0000000000 8388608.0000000000 4194304.0000000000 0.0000000000 0.0000000000 310.0000000000 4128768.0000000000 4128768.0000000000 0 0 0 0 0 0 0 0 0.0000000000 0 0 17931286038190 17901582538237 17931431845031 17931431958331
3 1 void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd] 0 0 2 241894 241894 32768 256 0 0 12 24 13888 0x0 0x7f6e9cc23f80 0 0 0 0 0 0 0 0 8192.0000000000 16384.0000000000 0.0000000000 0.0000000000 0.0000000000 8262.0000000000 0.0000000000 0.0000000000 0 0 0 0 0 0 0 0 0.0000000000 0 0 17931437652391 17931431845031 17931438008283 17931438016542
4 2 void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd] 0 0 5 241894 241894 4194304 256 0 0 12 24 14336 0x7f6e9fb92380 0x7f6e9cc23fc0 0 0 0 0 0 0 262144 0 2097152.0000000000 2097152.0000000000 0.0000000000 0.0000000000 0.0000000000 2097343.0000000000 0.0000000000 0.0000000000 0 0 0 0 0 0 0 0 0.0000000000 0 0 17931438610067 17931438008283 17931439296934 17931439297600
@@ -1,4 +1,4 @@
KernelName,Count,Sum(ns),Mean(ns),Median(ns),Pct
Kernel_Name,Count,Sum(ns),Mean(ns),Median(ns),Pct
__amd_rocclr_fillBufferAligned.kd,1,29849306794.0,29849306794.0,29849306794.0,99.23161614424411
"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",1,6163252.0,6163252.0,6163252.0,0.0204892348383507
"void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd]",1,4454736.0,4454736.0,4454736.0,0.0148094110133506
1 KernelName Kernel_Name Count Sum(ns) Mean(ns) Median(ns) Pct
2 __amd_rocclr_fillBufferAligned.kd 1 29849306794.0 29849306794.0 29849306794.0 99.23161614424411
3 void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd] 1 6163252.0 6163252.0 6163252.0 0.0204892348383507
4 void benchmark_func<int, 256, 8u, 512u>(int, int*) [clone .kd] 1 4454736.0 4454736.0 4454736.0 0.0148094110133506
@@ -1,7 +1,7 @@
Metric,Count,Unit
VALU - Vector,,Instr per wave
VMEM,,Instr per wave
LDS,,Instr per wave
LDS_Per_Workgroup,,Instr per wave
VALU - MFMA,,Instr per wave
SALU,,Instr per wave
SMEM,,Instr per wave
1 Metric Count Unit
2 VALU - Vector Instr per wave
3 VMEM Instr per wave
4 LDS LDS_Per_Workgroup Instr per wave
5 VALU - MFMA Instr per wave
6 SALU Instr per wave
7 SMEM Instr per wave
@@ -1,12 +1,12 @@
Metric,Avg,Min,Max,Unit
Wave Cycles,,,,Cycles/wave
LDS Instrs,,,,Instr per wave
LDS_Per_Workgroup Instrs,,,,Instr per wave
Bandwidth,,,,Bytes per wave
Bank Conficts/Access,,,,Conflicts/access
Index Accesses,,,,Cycles per wave
Dispatch_ID Accesses,,,,Cycles per wave
Atomic Cycles,,,,Cycles per wave
Bank Conflict,,,,Cycles per wave
Addr Conflict,,,,Cycles per wave
Unaligned Stall,,,,Cycles per wave
Mem Violations,,,, per wave
LDS Latency,,,,Cycles
LDS_Per_Workgroup Latency,,,,Cycles
1 Metric Avg Min Max Unit
2 Wave Cycles Cycles/wave
3 LDS Instrs LDS_Per_Workgroup Instrs Instr per wave
4 Bandwidth Bytes per wave
5 Bank Conficts/Access Conflicts/access
6 Index Accesses Dispatch_ID Accesses Cycles per wave
7 Atomic Cycles Cycles per wave
8 Bank Conflict Cycles per wave
9 Addr Conflict Cycles per wave
10 Unaligned Stall Cycles per wave
11 Mem Violations per wave
12 LDS Latency LDS_Per_Workgroup Latency Cycles
@@ -6,16 +6,16 @@ SMEM,,smem_
VALU,,valu_
MFMA,,mfma_
VMEM,,vmem_
LDS,,lds_
LDS_Per_Workgroup,,lds_
GWS,,gws_
BR,,br_
VGPR,12.0,vgpr_
SGPR,24.0,sgpr_
LDS Allocation,0.0,lds_alloc_
LDS_Per_Workgroup Allocation,0.0,lds_alloc_
Scratch Allocation,0.0,scratch_alloc_
Wavefronts,,wavefronts_
Workgroups,,workgroups_
LDS Req,,lds_req_
LDS_Per_Workgroup Req,,lds_req_
IL1 Fetch,,il1_fetch_
IL1 Hit,,il1_hit_
IL1_L2 Rd,,il1_l2_req_
@@ -46,10 +46,10 @@ Fabric_L2 Wr,,l2_fabric_wr_
Fabric_l2 Atomic,,l2_fabric_atom_
HBM Rd,,hbm_rd_
HBM Wr,,hbm_wr_
LDS Util,,lds_util_
LDS_Per_Workgroup Util,,lds_util_
VL1 Coalesce,,vl1_coales_
VL1 Stall,,vl1_stall_
LDS Lat,,lds_lat_
LDS_Per_Workgroup Lat,,lds_lat_
vL1D Lat,,sl1_lat_
IL1 Lat,,il1_lat_
Wave Occupancy,,wave_occ_
1 Metric Value Alias
6 VALU valu_
7 MFMA mfma_
8 VMEM vmem_
9 LDS LDS_Per_Workgroup lds_
10 GWS gws_
11 BR br_
12 VGPR 12.0 vgpr_
13 SGPR 24.0 sgpr_
14 LDS Allocation LDS_Per_Workgroup Allocation 0.0 lds_alloc_
15 Scratch Allocation 0.0 scratch_alloc_
16 Wavefronts wavefronts_
17 Workgroups workgroups_
18 LDS Req LDS_Per_Workgroup Req lds_req_
19 IL1 Fetch il1_fetch_
20 IL1 Hit il1_hit_
21 IL1_L2 Rd il1_l2_req_
46 Fabric_l2 Atomic l2_fabric_atom_
47 HBM Rd hbm_rd_
48 HBM Wr hbm_wr_
49 LDS Util LDS_Per_Workgroup Util lds_util_
50 VL1 Coalesce vl1_coales_
51 VL1 Stall vl1_stall_
52 LDS Lat LDS_Per_Workgroup Lat lds_lat_
53 vL1D Lat sl1_lat_
54 IL1 Lat il1_lat_
55 Wave Occupancy wave_occ_
@@ -1,4 +1,4 @@
Index,KernelName,gpu-id
Dispatch_ID,Kernel_Name,GPU_ID
0,__amd_rocclr_fillBufferAligned.kd,0
1,"void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd]",0
2,"void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd]",0
1 Index Dispatch_ID KernelName Kernel_Name gpu-id GPU_ID
2 0 __amd_rocclr_fillBufferAligned.kd 0
3 1 void benchmark_func<short, 256, 8u, 0u>(short, short*) [clone .kd] 0
4 2 void benchmark_func<float, 256, 8u, 0u>(float, float*) [clone .kd] 0
@@ -12,8 +12,8 @@ VALU Util,,Pct,100,
MFMA Util,,Pct,100,
VALU Active Threads/Wave,,Threads,64,
IPC - Issue,,Instr/cycle,5,
LDS BW,0.0,Gb/sec,22630.4,0.0
LDS Bank Conflict,,Conflicts/access,32,
LDS_Per_Workgroup BW,0.0,Gb/sec,22630.4,0.0
LDS_Per_Workgroup Bank Conflict,,Conflicts/access,32,
Instr Cache Hit Rate,,Pct,100,
Instr Cache BW,,Gb/s,6092.8,
Scalar L1D Cache Hit Rate,,Pct,100,
1 Metric Value Unit Peak PoP
12 MFMA Util Pct 100
13 VALU Active Threads/Wave Threads 64
14 IPC - Issue Instr/cycle 5
15 LDS BW LDS_Per_Workgroup BW 0.0 Gb/sec 22630.4 0.0
16 LDS Bank Conflict LDS_Per_Workgroup Bank Conflict Conflicts/access 32
17 Instr Cache Hit Rate Pct 100
18 Instr Cache BW Gb/s 6092.8
19 Scalar L1D Cache Hit Rate Pct 100
@@ -6,7 +6,7 @@ Scratch Stall,,,,Cycles
Insufficient SIMD Waveslots,,,,Simd
Insufficient SIMD VGPRs,,,,Simd
Insufficient SIMD SGPRs,,,,Simd
Insufficient CU LDS,,,,Cu
Insufficient CU LDS_Per_Workgroup,,,,Cu
Insufficient CU Barries,,,,Cu
Insufficient Bulky Resource,,,,Cu
Reach CU Threadgroups Limit,,,,Cycles
1 Metric Avg Min Max Unit
6 Insufficient SIMD Waveslots Simd
7 Insufficient SIMD VGPRs Simd
8 Insufficient SIMD SGPRs Simd
9 Insufficient CU LDS Insufficient CU LDS_Per_Workgroup Cu
10 Insufficient CU Barries Cu
11 Insufficient Bulky Resource Cu
12 Reach CU Threadgroups Limit Cycles
@@ -6,5 +6,5 @@ Saved Wavefronts,,,,Wavefronts
Restored Wavefronts,,,,Wavefronts
VGPRs,11.784431137724551,4,16,Registers
SGPRs,24.047904191616766,24,32,Registers
LDS Allocation,0.0,0,0,Bytes
LDS_Per_Workgroup Allocation,0.0,0,0,Bytes
Scratch Allocation,0.0,0,0,Bytes
1 Metric Avg Min Max Unit
6 Restored Wavefronts Wavefronts
7 VGPRs 11.784431137724551 4 16 Registers
8 SGPRs 24.047904191616766 24 32 Registers
9 LDS Allocation LDS_Per_Workgroup Allocation 0.0 0 0 Bytes
10 Scratch Allocation 0.0 0 0 Bytes