P4 to Git Change 1495187 by gandryey@gera-w8 on 2017/12/15 14:50:07

SWDEV-79445 - OCL generic changes and code clean-up
	- Add a workaround for incorrect profiling results, when release_mem can occur later in the pipeline and breaking the timeline sequence with dispatches. Ucode can't process RM packets and cs_partial_flush at the same time, thus RM packets are delayed up to 2 cs_patial_flush calls. A workaround adds CS partial flush after dispatch and switches to write_reg_mem for TS updates

Affected files ...

... //depot/stg/opencl/drivers/opencl/runtime/device/pal/paltimestamp.cpp#4 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palvirtual.cpp#66 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palvirtual.hpp#37 edit

rocclr/runtime/device/pal/paltimestamp.cpp

@@ -19,7 +19,7 @@ TimeStamp::~TimeStamp() {}
 
 void TimeStamp::begin(bool sdma) {
   if (!flags_.beginIssued_) {
-    gpu().iCmd()->CmdWriteTimestamp(Pal::HwPipePoint::HwPipeBottom, *iMem_,
+    gpu().iCmd()->CmdWriteTimestamp(Pal::HwPipePoint::HwPipeTop, *iMem_,
                                     memOffset_ + CommandStartTime * sizeof(uint64_t));
     flags_.beginIssued_ = true;
   }
@@ -27,7 +27,7 @@ void TimeStamp::begin(bool sdma) {
 
 void TimeStamp::end(bool sdma) {
   CondLog(!flags_.beginIssued_, "We didn't issue a begin operation!");
-  gpu().iCmd()->CmdWriteTimestamp(Pal::HwPipePoint::HwPipeBottom, *iMem_,
+  gpu().iCmd()->CmdWriteTimestamp(Pal::HwPipePoint::HwPipeTop, *iMem_,
                                   memOffset_ + CommandEndTime * sizeof(uint64_t));
   flags_.endIssued_ = true;
   flags_.sdma_ = sdma;

rocclr/runtime/device/pal/palvirtual.cpp

@@ -451,7 +451,9 @@ void VirtualGPU::MemoryDependency::validate(VirtualGPU& gpu, const Memory* memor
 
   if (flushL1Cache) {
     // Flush cache
-    gpu.flushCUCaches();
+    if (!gpu.profiling()) {
+        gpu.flushCUCaches();
+    }
 
     // Clear memory dependency state
     const static bool All = true;
@@ -757,7 +759,7 @@ bool VirtualGPU::create(bool profiling, uint deviceQueueSize, uint rtCUs,
   createInfo.allocInfo[Pal::CommandDataAlloc].allocHeap = Pal::GpuHeapGartCacheable;
   createInfo.allocInfo[Pal::CommandDataAlloc].allocSize =
   createInfo.allocInfo[Pal::CommandDataAlloc].suballocSize =
-    VirtualGPU::Queue::MaxCommands * (320 + ((profiling) ? 64 : 0));
+    VirtualGPU::Queue::MaxCommands * (320 + ((profiling) ? 96 : 0));
 
   createInfo.allocInfo[Pal::EmbeddedDataAlloc].allocHeap = Pal::GpuHeapGartCacheable;
   createInfo.allocInfo[Pal::EmbeddedDataAlloc].allocSize = 64 * Ki;
@@ -1980,7 +1982,13 @@ bool VirtualGPU::submitKernelInternal(const amd::NDRangeContainer& sizes, const
     // Run AQL dispatch in HW
     eventBegin(MainEngine);
     iCmd()->CmdDispatchAql(dispatchParam);
+    // Note: This a workaround for incorrect results reported with release_mem packet,
+    // when the packet can be processed later after this dispatch and including extra time
+    if (profiling()) {
+      flushCUCaches();
+    }
     eventEnd(MainEngine, gpuEvent);
+
     if (id != gpuEvent.id) {
       LogError("something is wrong. ID mismatch!\n");
     }

rocclr/runtime/device/pal/palvirtual.hpp

@@ -449,7 +449,9 @@ class VirtualGPU : public device::VirtualDevice {
     barrier.pTransitions = &trans;
     barrier.waitPoint = Pal::HwPipePreCs;
     iCmd()->CmdBarrier(barrier);
-    queues_[engineID_]->submit(false);
+    if (!profiling()) {
+      queues_[engineID_]->submit(false);
+    }
   }
 
   void eventBegin(EngineType engId) const {