Merge "integrating memory_validation bench in cmake build" into amd-master

[ROCm/rocprofiler commit: 710a9de411]

projects/rocprofiler/src/core/context_pool.h

@@ -73,7 +73,28 @@ class ContextPool {
   void Flush() {
     check_completed();
   }
+#if 0
+  template <class F>
+  F for_each(const F& f_p) {
+    F f = f_p;
+    while (sync_flag_.test_and_set(std::memory_order_acquire) != false) {
+      std::this_thread::yield();
+    }
 
+    index_t read_index = read_index_.load(std::memory_order_relaxed);
+    const index_t write_index = write_index_.load(std::memory_order_relaxed);
+    while(read_index < write_index) {
+      rocprofiler_pool_entry_t pool_entry{};
+      entry_t* entry = GetPoolEntry(read_index, &pool_entry);
+      const bool completed = entry->completed.load(std::memory_order_acquire);
+      if (completed == false) {
+        f(entry->context, entry->payload);
+      }
+    }
+
+    return f;
+  }
+#endif
   private:
   static unsigned aligned64(const unsigned& size) { return (size + 0x3f) & ~0x3fu; }
 

projects/rocprofiler/test/CMakeLists.txt

@@ -88,3 +88,9 @@ set ( TEST_LIB_SRC ${TEST_DIR}/tool/tool.cpp ${UTIL_SRC} )
 add_library ( ${TEST_LIB} SHARED ${TEST_LIB_SRC} )
 target_include_directories ( ${TEST_LIB} PRIVATE ${TEST_DIR} ${ROOT_DIR} ${HSA_RUNTIME_INC_PATH} )
 target_link_libraries ( ${TEST_LIB} ${ROCPROFILER_TARGET} ${HSA_RUNTIME_LIB} c stdc++ dl pthread rt )
+
+## Build memory test bench
+add_custom_target( mbench
+  COMMAND sh -xc "cp -r ${TEST_DIR}/memory_validation ${PROJECT_BINARY_DIR}/test/."
+  COMMAND make -C "${PROJECT_BINARY_DIR}/test/memory_validation"
+)

projects/rocprofiler/test/memory_validation/run.sh

@@ -1,4 +1,5 @@
 #!/bin/bash
+BDIR=`dirname $0`
 
 ###############################################################################
 # Copyright (c) 2019 Advanced Micro Devices, Inc. All rights reserved.
@@ -24,7 +25,7 @@
 
 # test TCP/TCC miss
 # to test separately, append TCP or TCC as argument
-run_scripts/test_cache_miss.sh
+$BDIR/run_scripts/test_cache_miss.sh
 
 # test data fetch/write size to memory
-run_scripts/test_fetchwrite_size.sh
+$BDIR/run_scripts/test_fetchwrite_size.sh

projects/rocprofiler/test/memory_validation/run_scripts/test_cache_miss.sh

@@ -107,7 +107,7 @@ function one_run
         done
 
         rstdiff=1        # check result (0: pass/no-difference, 1: fail)
-        totTccReqs=$(( $hitTccReqs + $missTccReqs ))
+        totTccReqs=$((hitTccReqs + missTccReqs))
 
         #-- use kernel 'cache_test_RO' to validate read miss rate
         if [[ $kern == cache_test_RO ]]; then