Moving workloads to old
Signed-off-by: Jose Santos <josantos@login1.hpcfund>
Этот коммит содержится в:
Jose Santos authored and 
Karl W. Schulz committed
1 родитель
76873dd0c4
Коммит
989e29cf81
9701 file changed
+4016
No files matched your search
@@ -0,0 +1,4 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
|
||||
0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,181827,181827,1048576,256,0,0,8,8,16,64,0x0,0x7f07663bae80,47978,47978,16384,65536,14494,1861536,6402045414567,6401146042762,6401146066762,6402053157530
|
||||
1,"vecCopy(double*, double*, double*, int, int) ",2,0,2,181827,181827,1048576,256,0,0,8,8,16,64,0x0,0x7f07663bae80,44012,44012,16384,65536,8160,1048580,6402053180624,6401146167882,6401146186922,6402053517320
|
||||
2,"vecCopy(double*, double*, double*, int, int) ",2,0,4,181827,181827,1048576,256,0,0,8,8,16,64,0x0,0x7f07663bae80,43085,43085,16384,65536,8145,1048584,6402053549281,6401146207402,6401146226282,6402053732076
|
||||
|
@@ -0,0 +1,4 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
|
||||
0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,178576,178576,1048576,256,0,0,8,8,16,64,0x0,0x7f74bd5b6e80,0,0,0,6386463651065,6401146042762,6401146066762,6386471177349
|
||||
1,"vecCopy(double*, double*, double*, int, int) ",2,0,2,178576,178576,1048576,256,0,0,8,8,16,64,0x0,0x7f74bd5b6e80,0,0,0,6386471197998,6401146167882,6401146186922,6386471552869
|
||||
2,"vecCopy(double*, double*, double*, int, int) ",2,0,4,178576,178576,1048576,256,0,0,8,8,16,64,0x0,0x7f74bd5b6e80,0,0,0,6386471582034,6401146207402,6401146226282,6386471757676
|
||||
|
@@ -0,0 +1,4 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
|
||||
0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,182838,182838,1048576,256,0,0,8,8,16,64,0x0,0x7faf17528e80,65536,221118,28351800,6406815203658,6401146042762,6401146066762,6406822956018
|
||||
1,"vecCopy(double*, double*, double*, int, int) ",2,0,2,182838,182838,1048576,256,0,0,8,8,16,64,0x0,0x7faf17528e80,65536,203702,26080032,6406822974133,6401146167882,6401146186922,6406823418142
|
||||
2,"vecCopy(double*, double*, double*, int, int) ",2,0,4,182838,182838,1048576,256,0,0,8,8,16,64,0x0,0x7faf17528e80,65536,203144,25999920,6406823446055,6401146207402,6401146226282,6406823622218
|
||||
|
@@ -0,0 +1,4 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
|
||||
0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,178778,178778,1048576,256,0,0,8,8,16,64,0x0,0x7fc7e6412e80,32768,659106,84360532,6387368867286,6401146042762,6401146066762,6387376507826
|
||||
1,"vecCopy(double*, double*, double*, int, int) ",2,0,2,178778,178778,1048576,256,0,0,8,8,16,64,0x0,0x7fc7e6412e80,32768,653457,83634844,6387376528044,6401146167882,6401146186922,6387376826258
|
||||
2,"vecCopy(double*, double*, double*, int, int) ",2,0,4,178778,178778,1048576,256,0,0,8,8,16,64,0x0,0x7fc7e6412e80,32768,670775,85843888,6387376854291,6401146207402,6401146226282,6387377024353
|
||||
|
@@ -0,0 +1,4 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
|
||||
0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,180006,180006,1048576,256,0,0,8,8,16,64,0x0,0x7ff7b376ee80,49008,49008,17099,392072,16384,25315374,242746,0,101780108,6393202548827,6401146042762,6401146066762,6393210198774
|
||||
1,"vecCopy(double*, double*, double*, int, int) ",2,0,2,180006,180006,1048576,256,0,0,8,8,16,64,0x0,0x7ff7b376ee80,42135,42135,12945,337088,16384,24545355,232922,0,98697060,6393210228730,6401146167882,6401146186922,6393210558173
|
||||
2,"vecCopy(double*, double*, double*, int, int) ",2,0,4,180006,180006,1048576,256,0,0,8,8,16,64,0x0,0x7ff7b376ee80,41623,41623,13083,332992,16384,24635089,231002,0,99051052,6393210596947,6401146207402,6401146226282,6393210786946
|
||||
|
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
@@ -0,0 +1,5 @@
|
||||
pmc: SQ_CYCLES SQ_BUSY_CYCLES SQ_BUSY_CU_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQC_TC_INST_REQ SQC_TC_DATA_READ_REQ SQC_TC_DATA_WRITE_REQ GRBM_COUNT GRBM_GUI_ACTIVE TCP_GATE_EN1_sum TCP_GATE_EN2_sum TCP_TD_TCP_STALL_CYCLES_sum TCP_TCR_TCP_STALL_CYCLES_sum TA_TA_BUSY_sum TA_BUFFER_WAVEFRONTS_sum TD_TD_BUSY_sum TD_TC_STALL_sum SPI_CSN_WINDOW_VALID SPI_CSN_BUSY CPC_CPC_STAT_BUSY CPC_CPC_STAT_IDLE CPF_CPF_STAT_BUSY CPF_CPF_STAT_STALL TCC_CYCLE_sum TCC_BUSY_sum TCC_PROBE_sum TCC_PROBE_ALL_sum
|
||||
|
||||
gpu:
|
||||
range:
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQC_TC_DATA_ATOMIC_REQ SQC_TC_STALL SQC_TC_REQ SQC_DCACHE_REQ_READ_16 SQC_ICACHE_REQ SQC_ICACHE_HITS SQC_ICACHE_MISSES SQC_ICACHE_MISSES_DUPLICATE GRBM_SPI_BUSY TCP_READ_TAGCONFLICT_STALL_CYCLES_sum TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum TCP_TA_TCP_STATE_READ_sum TA_BUFFER_READ_WAVEFRONTS_sum TA_BUFFER_WRITE_WAVEFRONTS_sum TD_COALESCABLE_WAVEFRONT_sum TD_LOAD_WAVEFRONT_sum SPI_CSN_NUM_THREADGROUPS SPI_CSN_WAVE CPC_CPC_TCIU_BUSY CPC_CPC_TCIU_IDLE CPF_CPF_TCIU_BUSY CPF_CPF_TCIU_STALL TCC_NC_REQ_sum TCC_UC_REQ_sum TCC_CC_REQ_sum TCC_RW_REQ_sum
|
||||
|
||||
gpu:
|
||||
range:
|
||||
kernel:
|
||||
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
@@ -0,0 +1,5 @@
|
||||
pmc: SQC_DCACHE_INPUT_VALID_READYB SQC_DCACHE_ATOMIC SQC_DCACHE_REQ_READ_8 SQC_DCACHE_REQ SQC_DCACHE_HITS SQC_DCACHE_MISSES SQC_DCACHE_MISSES_DUPLICATE SQC_DCACHE_REQ_READ_1 TCP_VOLATILE_sum TCP_TOTAL_ACCESSES_sum TCP_TOTAL_READ_sum TCP_TOTAL_WRITE_sum TA_BUFFER_ATOMIC_WAVEFRONTS_sum TA_BUFFER_TOTAL_CYCLES_sum TD_ATOMIC_WAVEFRONT_sum TD_STORE_WAVEFRONT_sum SPI_RA_REQ_NO_ALLOC SPI_RA_REQ_NO_ALLOC_CSN CPC_CPC_STAT_STALL CPC_UTCL1_STALL_ON_TRANSLATION CPF_CPF_STAT_IDLE CPF_CPF_TCIU_IDLE TCC_REQ_sum TCC_STREAMING_REQ_sum TCC_HIT_sum TCC_MISS_sum
|
||||
|
||||
gpu:
|
||||
range:
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQC_DCACHE_REQ_READ_2 SQC_DCACHE_REQ_READ_4 SQ_INSTS_VMEM_WR SQ_INSTS_VMEM_RD SQ_INSTS_VMEM SQ_INSTS_SALU SQ_INSTS_VSKIPPED SQ_INSTS_SMEM TCP_TOTAL_ATOMIC_WITH_RET_sum TCP_TOTAL_ATOMIC_WITHOUT_RET_sum TCP_TOTAL_WRITEBACK_INVALIDATES_sum TCP_TOTAL_CACHE_ACCESSES_sum TA_BUFFER_COALESCED_READ_CYCLES_sum TA_BUFFER_COALESCED_WRITE_CYCLES_sum SPI_RA_RES_STALL_CSN SPI_RA_TMP_STALL_CSN CPC_CPC_UTCL2IU_BUSY CPC_CPC_UTCL2IU_IDLE CPF_CMP_UTCL1_STALL_ON_TRANSLATION TCC_READ_sum TCC_WRITE_sum TCC_ATOMIC_sum TCC_WRITEBACK_sum
|
||||
|
||||
gpu:
|
||||
range:
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQ_INSTS_FLAT SQ_INSTS_LDS SQ_INSTS_GDS SQ_INSTS_EXP_GDS SQ_INSTS_BRANCH SQ_INSTS_SENDMSG SQ_INSTS SQ_WAIT_ANY TCP_UTCL1_TRANSLATION_MISS_sum TCP_UTCL1_TRANSLATION_HIT_sum TCP_UTCL1_PERMISSION_MISS_sum TCP_UTCL1_REQUEST_sum TA_ADDR_STALLED_BY_TC_CYCLES_sum TA_TOTAL_WAVEFRONTS_sum SPI_RA_WAVE_SIMD_FULL_CSN SPI_RA_VGPR_SIMD_FULL_CSN CPC_CPC_UTCL2IU_STALL CPC_ME1_BUSY_FOR_PACKET_DECODE TCC_EA_WRREQ_sum TCC_EA_WRREQ_64B_sum TCC_EA_WR_UNCACHED_32B_sum TCC_EA_WRREQ_DRAM_sum
|
||||
|
||||
gpu:
|
||||
range:
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQ_WAIT_INST_ANY SQ_ACTIVE_INST_ANY SQ_INSTS_VALU SQ_ACTIVE_INST_VMEM SQ_ACTIVE_INST_LDS SQ_ACTIVE_INST_VALU SQ_ACTIVE_INST_SCA SQ_ACTIVE_INST_EXP_GDS TCP_TCP_LATENCY_sum TCP_TCC_READ_REQ_LATENCY_sum TCP_TCC_WRITE_REQ_LATENCY_sum TCP_TCC_READ_REQ_sum TA_ADDR_STALLED_BY_TD_CYCLES_sum TA_DATA_STALLED_BY_TC_CYCLES_sum SPI_RA_SGPR_SIMD_FULL_CSN SPI_RA_LDS_CU_FULL_CSN CPC_ME1_DC0_SPI_BUSY TCC_EA_WRREQ_STALL_sum TCC_EA_WRREQ_IO_CREDIT_STALL_sum TCC_EA_WRREQ_GMI_CREDIT_STALL_sum TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum
|
||||
|
||||
gpu:
|
||||
range:
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQ_ACTIVE_INST_MISC SQ_ACTIVE_INST_FLAT SQ_INST_CYCLES_VMEM_WR SQ_INST_CYCLES_VMEM_RD SQ_INST_CYCLES_SMEM SQ_INST_CYCLES_SALU SQ_THREAD_CYCLES_VALU SQ_IFETCH TCP_TCC_WRITE_REQ_sum TCP_TCC_ATOMIC_WITH_RET_REQ_sum TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum TCP_TCC_NC_READ_REQ_sum TA_FLAT_WAVEFRONTS_sum TA_FLAT_READ_WAVEFRONTS_sum SPI_RA_BAR_CU_FULL_CSN SPI_RA_TGLIM_CU_FULL_CSN TCC_EA_RDREQ_sum TCC_EA_RDREQ_32B_sum TCC_EA_RD_UNCACHED_32B_sum TCC_EA_RDREQ_DRAM_sum
|
||||
|
||||
gpu:
|
||||
range:
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQ_LDS_BANK_CONFLICT SQ_LDS_ADDR_CONFLICT SQ_LDS_UNALIGNED_STALL SQ_WAVES_EQ_64 SQ_WAVES_LT_64 SQ_WAVES_LT_48 SQ_WAVES_LT_32 SQ_WAVES_LT_16 TCP_TCC_NC_WRITE_REQ_sum TCP_TCC_NC_ATOMIC_REQ_sum TCP_TCC_UC_READ_REQ_sum TCP_TCC_UC_WRITE_REQ_sum TA_FLAT_WRITE_WAVEFRONTS_sum TA_FLAT_ATOMIC_WAVEFRONTS_sum SPI_RA_WVLIM_STALL_CSN SPI_SWC_CSC_WR TCC_EA_RDREQ_IO_CREDIT_STALL_sum TCC_EA_RDREQ_GMI_CREDIT_STALL_sum TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum TCC_TAG_STALL_sum
|
||||
|
||||
gpu:
|
||||
range:
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQ_ITEMS SQ_LDS_MEM_VIOLATIONS SQ_LDS_ATOMIC_RETURN SQ_LDS_IDX_ACTIVE SQ_WAVES_RESTORED SQ_WAVES_SAVED SQ_INSTS_SMEM_NORM TCP_TCC_UC_ATOMIC_REQ_sum TCP_TCC_CC_READ_REQ_sum TCP_TCC_CC_WRITE_REQ_sum TCP_TCC_CC_ATOMIC_REQ_sum SPI_VWC_CSC_WR SPI_RA_BULKY_CU_FULL_CSN TCC_NORMAL_WRITEBACK_sum TCC_ALL_TC_OP_WB_WRITEBACK_sum TCC_NORMAL_EVICT_sum TCC_ALL_TC_OP_INV_EVICT_sum
|
||||
|
||||
gpu:
|
||||
range:
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: TCP_TCC_RW_READ_REQ_sum TCP_TCC_RW_WRITE_REQ_sum TCP_TCC_RW_ATOMIC_REQ_sum TCP_PENDING_STALL_CYCLES_sum TCC_TOO_MANY_EA_WRREQS_STALL_sum TCC_EA_ATOMIC_sum TCC_EA_RDREQ_LEVEL_sum TCC_EA_WRREQ_LEVEL_sum
|
||||
|
||||
gpu:
|
||||
range:
|
||||
kernel:
|
||||
File renamed without changes.
@@ -0,0 +1,4 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,obj,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],wave_size_1,obj_1,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,wave_size_2,obj_2,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,TCC_EA_RDREQ_DRAM_sum,wave_size_3,obj_3,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],wave_size_4,obj_4,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_LEVEL_sLine truncated
|
||||
0,"vecCopy(double*, double*, double*, int, int) ",2,1048576,256,0,0,8,8,16,64,0x7f8d2f830e80,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,0,49587,0,0,64,0x7f644a954e80,1048576,0,0,0,0,0,131072,0.0,0.0,0.0,0.0,16384,0,87134.0,43938.0,131111.0,0.0,64,0x7f2b60eb0e80,32768,32768,16384,16384,65536,49152,11534336,65536,131072.0,0.0,0.0,0.0,32768.0,16384.0,0,0,131344.0,0.0,536.0,131343.0,64,0x7f0f4a34ae80,0,8192,4096,8192,0,8192,4096,8192,141,8195,4240,8336,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8240,4144,8240,0,8192,4096,8192,0,8240,4144,8240,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,47,8193,4144,8240,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8432,4336,8432,64,0x7f3046420e80,131072.0,131072.0,0.0,2395494.0,0.0,0.0,120528457.0,58922799.0,64,0x7f4f4b326e80,4096,0,0,0,4096,0,78,0,4099,0,92,0,4096,0,107,0,4096,0,0,0,4096,0,0,0,4096,0,0,0,4096,0,0,0,4096,0,0,0,4096,0,164,0,4096,0,465,0,4096,0,73,0,4096,0,1130,0,4096,0,0,0,4096,0,540,0,4096,0,0,0,4096,0,0,0,4096,0,8945,0,4096,0,3,0,4096,0,0,0,4096,0,0,0,4096,0,0,0,4096,0,498,0,4097,0,1091,0,4096,0,0,0,4096,0,0,0,4096,0,0,0,4096,0,0,0,4144,0,1477,0,4096,0,0,0,4144,0,32,0,4284,0,497,0,64,0x7fecb0d5ce80,376904,230792,3357903,16384,24760041,144,48,0,47112,47112,3814019.0,2976853.0,5738.0,985388.0,2192342.0,0.0,2967674.0,2658473.0,375583,240738,47112,0,47112,0,1507584.0,975483.0,0.0,0.0,64,0x7fa07fd82e80,0.0,64,0x7fdf3cd2ae80,190442,0,0,65536,64048,48,1440,32768,2097152.0,2097152.0,1048576.0,1048576.0,0.0,0.0,0.0,16384.0,14624,31008,9370,588,0,45997,262548.0,0.0,188.0,262360.0,64,0x7fb38df68e80,0,0,192,0,65536,64516,48,1237,30682,0.0,0.0,0.0,32768.0,0.0,0.0,0.0,32768.0,4096,16384,513,46290,1694,0,48.0,374.0,0.0,262288.0,64,0x7f127d5a6e80,32768,0,16384,16384,32768,49152,0,65536,0.0,0.0,120.0,524288.0,0.0,0.0,0,0,913,47172,0,131586.0,131072.0,0.0,131104.0,64,0x7ff1b2b5ee80,8192,0,4096,8192,0,4096,8336,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,64,0x7f02303c8e80,2761247,360448,163840,0,0,180224,114688,0,62712797.0,166197421.0,65940938.0,131072.0,0.0,809165.0,0,0,27263,129275.0,0.0,0.0,129275.0,64,0x7f6fac218e80,0,0,0,16384,0,0,0,0,0.0,0.0,0.0,0.0,16384.0,0.0,0,81920,0.0,0.0,46034.0,117861.0,64,0x7f772616ee80,32768,0,0,0,16384,16384,393216,22041595,960.0,513895.0,0.0,524288.0,1139463.0,32768.0,0,0,0,16845,131072.0,131072.0,0.0,131072.0,64,0x7ff8e5aa2e80,0,3390202,4096,4096,0,3030998,4096,4096,0,3199857,4096,4096,0,2899960,4096,4096,0,3249414,4096,4096,0,3140864,4096,4096,0,3182508,4096,4096,0,3420545,4096,4096,0,3369133,4096,4096,0,3127958,4096,4096,0,3562084,4096,4096,0,4725832,4096,4096,0,3264542,4096,4096,0,3046568,4096,4096,0,3119683,4096,4096,0,2197731,4096,4096,0,3318429,4096,4096,0,3410159,4096,4096,0,3308436,4096,4096,0,3031551,4096,4096,0,3053087,4096,4096,0,3004147,4096,4096,0,3427244,4096,4096,0,2541016,4096,4096,0,2657709,4096,4096,0,3272631,4096,4096,0,3134811,4096,4096,0,2953171,4096,4096,0,3141282,4096,4096,0,3068986,4096,4096,0,3613602,4096,4096,0,2498301,4096,4096,64,0x7f399fc26e80,2511,0,0,1845207,2711,0,0,1931071,4658,0,0,2096105,1902,0,0,1809377,2599,0,0,1898147,552,0,0,1553694,3710,0,0,2049510,1978,0,0,1822040,2864,0,0,1893049,4732,0,0,2143090,1506,0,0,1788296,2356,0,0,1878544,3357,0,0,1941504,1504,0,0,1742355,979,0,0,1698673,2117,0,0,1799752,2628,0,0,1841567,1473,0,0,1735184,3412,0,0,1991946,3915,0,0,2002789,2692,0,0,1875124,978,0,0,1666762,5266,0,0,2124752,3676,0,0,1982064,3091,0,0,1884284,525,0,0,1613866,3723,0,0,1942532,2528,0,0,1825903,3073,0,0,1948604,1468,0,0,1765924,3170,0,0,1961447,4769,0,0,2069353,6401146042762,6401146066762
|
||||
1,"vecCopy(double*, double*, double*, int, int) ",2,1048576,256,0,0,8,8,16,64,0x7f8d2f830e80,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,0,43503,0,0,64,0x7f644a954e80,1048576,0,0,0,0,0,131072,0.0,0.0,0.0,0.0,16384,0,86942.0,0.0,131112.0,0.0,64,0x7f2b60eb0e80,32768,32768,16384,16384,65536,49152,11534336,65536,131072.0,0.0,0.0,0.0,32768.0,16384.0,0,0,131210.0,0.0,274.0,131209.0,64,0x7f0f4a34ae80,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8240,4144,8240,0,8192,4096,8192,0,8240,4144,8240,0,8192,4096,8192,0,8194,4098,8194,0,8192,4096,8192,0,8193,4097,8193,0,8192,4096,8192,0,8192,4096,8192,0,8194,4098,8194,0,8193,4097,8193,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,47,8193,4144,8240,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8431,4335,8431,64,0x7f3046420e80,131072.0,131072.0,0.0,2667257.0,0.0,0.0,119196319.0,59225115.0,64,0x7f4f4b326e80,4096,0,2591,0,4096,0,43,0,4096,0,18,0,4096,0,480,0,4096,0,2247,0,4096,0,0,0,4096,0,0,0,4096,0,189,0,4096,0,2031,0,4096,0,2817,0,4096,0,0,0,4096,0,900,0,4096,0,1395,0,4096,0,237,0,4096,0,297,0,4097,0,1117,0,4096,0,660,0,4096,0,3283,0,4096,0,0,0,4099,0,875,0,4096,0,1658,0,4096,0,684,0,4096,0,0,0,4097,0,0,0,4096,0,2017,0,4096,0,1741,0,4096,0,0,0,4096,0,72,0,4146,0,2462,0,4096,0,1131,0,4144,0,25,0,4380,0,4417,0,64,0x7fecb0d5ce80,419656,278055,3935784,16384,25396552,0,48,0,52456,52456,4455405.0,3611224.0,5448.0,1173370.0,2546417.0,0.0,3602470.0,3296128.0,419648,286455,52456,0,52456,1044,1678592.0,985135.0,1.0,0.0,64,0x7fa07fd82e80,0.0,64,0x7fdf3cd2ae80,225120,0,0,65536,64048,48,1440,32768,2097152.0,2097152.0,1048576.0,1048576.0,0.0,0.0,0.0,16384.0,15120,31504,8587,3265,0,41265,262452.0,0.0,47.0,262405.0,64,0x7fb38df68e80,0,0,48,0,65536,65536,0,0,30644,0.0,0.0,0.0,32768.0,0.0,0.0,0.0,32768.0,4096,16384,457,42370,1710,0,48.0,360.0,0.0,262144.0,64,0x7f127d5a6e80,32768,0,16384,16384,32768,49152,0,65536,0.0,0.0,240.0,524288.0,0.0,0.0,0,0,5046,43509,1088,131544.0,131072.0,0.0,86787.0,64,0x7ff1b2b5ee80,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,64,0x7f02303c8e80,231746,360448,163840,0,0,180224,114688,0,71282283.0,196480494.0,73304574.0,131072.0,0.0,600606.0,0,0,23735,65455.0,0.0,0.0,65455.0,64,0x7f6fac218e80,0,0,0,16384,0,0,0,0,0.0,0.0,0.0,0.0,16384.0,0.0,0,81920,0.0,0.0,34860.0,104541.0,64,0x7f772616ee80,32768,0,0,0,16384,16384,393216,21576120,960.0,513874.0,0.0,524288.0,1117900.0,32768.0,0,0,0,13633,87306.0,87306.0,0.0,87306.0,64,0x7ff8e5aa2e80,0,3182435,2748,2748,0,2846843,2712,2712,0,3270560,2672,2672,0,3370231,2731,2731,0,3319924,2669,2669,0,3222460,2744,2744,0,3457492,2720,2720,0,4095239,2733,2733,0,3439885,2708,2708,0,3520704,2690,2690,0,3563263,2724,2724,0,4747701,2726,2726,0,3201333,2674,2674,0,3394553,2716,2716,0,3411636,2704,2704,0,3140342,2726,2726,0,3677889,2708,2708,0,3342911,2714,2714,0,3950057,2736,2736,0,3631324,2728,2728,0,3361026,2679,2679,0,3623698,2762,2762,0,3983237,2738,2738,0,3360600,2712,2712,0,3286797,2684,2684,0,3472804,2732,2732,0,3621270,2726,2726,0,3675557,2730,2730,0,3218851,2708,2708,0,2643686,2725,2725,0,3394416,2720,2720,0,3344836,2732,2732,64,0x7f399fc26e80,2308,0,0,1453175,950,0,0,1344904,2068,0,0,1454846,3164,0,0,1557269,2190,0,0,1548144,153,0,0,1191643,3461,0,0,1652838,958,0,0,1290631,868,0,0,1353851,609,0,0,1317645,1858,0,0,1443457,2397,0,0,1487712,3980,0,0,1629665,4143,0,0,1669882,629,0,0,1231148,7582,0,0,1932016,2543,0,0,1551398,2407,0,0,1486532,1601,0,0,1366745,1637,0,0,1449874,4451,0,0,1632486,3069,0,0,1574008,2691,0,0,1465045,3460,0,0,1567805,4203,0,0,1699639,512,0,0,1195455,1275,0,0,1458267,1954,0,0,1479178,2049,0,0,1503491,1285,0,0,1354941,690,0,0,1290003,4214,0,0,1656569,6401146167882,6401146186922
|
||||
2,"vecCopy(double*, double*, double*, int, int) ",2,1048576,256,0,0,8,8,16,64,0x7f8d2f830e80,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,0,43704,0,0,64,0x7f644a954e80,1048576,0,0,0,0,0,131072,0.0,0.0,0.0,0.0,16384,0,86888.0,0.0,131112.0,0.0,64,0x7f2b60eb0e80,32768,32768,16384,16384,65536,49152,11534336,65536,131072.0,0.0,0.0,0.0,32768.0,16384.0,0,0,131231.0,0.0,316.0,131230.0,64,0x7f0f4a34ae80,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8240,4144,8240,0,8192,4096,8192,0,8240,4144,8240,0,8192,4096,8192,0,8194,4098,8194,0,8192,4096,8192,0,8193,4097,8193,0,8192,4096,8192,0,8192,4096,8192,0,8194,4098,8194,0,8193,4097,8193,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,47,8193,4144,8240,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8432,4336,8432,64,0x7f3046420e80,131072.0,131072.0,0.0,2599947.0,0.0,0.0,116939011.0,45174328.0,64,0x7f4f4b326e80,4096,0,2763,0,4096,0,0,0,4096,0,1147,0,4096,0,0,0,4096,0,2838,0,4096,0,73,0,4096,0,881,0,4096,0,397,0,4096,0,1306,0,4096,0,987,0,4096,0,1237,0,4096,0,325,0,4096,0,2033,0,4096,0,1345,0,4096,0,293,0,4097,0,0,0,4096,0,1954,0,4096,0,1865,0,4096,0,1496,0,4099,0,285,0,4096,0,1423,0,4096,0,1418,0,4096,0,1487,0,4097,0,0,0,4096,0,171,0,4096,0,1977,0,4096,0,594,0,4096,0,319,0,4146,0,0,0,4096,0,2263,0,4144,0,884,0,4373,0,3262,0,64,0x7fecb0d5ce80,340944,229788,3312307,16384,23742902,0,48,0,42617,42617,3736001.0,3016003.0,5658.0,1045666.0,2227860.0,0.0,3006820.0,2696975.0,340936,239245,42617,0,42617,0,1363744.0,837264.0,0.0,0.0,64,0x7fa07fd82e80,0.0,64,0x7fdf3cd2ae80,186336,0,0,65536,64048,48,1440,32768,2097152.0,2097152.0,1048576.0,1048576.0,0.0,0.0,0.0,16384.0,12999,29383,8585,3731,0,39879,262474.0,0.0,47.0,262427.0,64,0x7fb38df68e80,0,0,48,0,65536,65536,0,0,30652,0.0,0.0,0.0,32768.0,0.0,0.0,0.0,32768.0,4096,16384,457,41950,1676,0,48.0,341.0,0.0,262144.0,64,0x7f127d5a6e80,32768,0,16384,16384,32768,49152,0,65536,0.0,0.0,120.0,524288.0,0.0,0.0,0,0,3745,37920,0,131395.0,131072.0,0.0,86456.0,64,0x7ff1b2b5ee80,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,64,0x7f02303c8e80,1446255,360448,163840,0,0,180224,114688,0,68875193.0,192103698.0,81403584.0,131072.0,0.0,797205.0,0,0,25888,107142.0,0.0,0.0,107142.0,64,0x7f6fac218e80,0,0,0,16384,0,0,0,0,0.0,0.0,0.0,0.0,16384.0,0.0,0,81920,0.0,0.0,44536.0,114067.0,64,0x7f772616ee80,32768,0,0,0,16384,16384,393216,22220888,960.0,513849.0,0.0,524288.0,1247745.0,32768.0,0,0,0,15202,86695.0,86695.0,0.0,86695.0,64,0x7ff8e5aa2e80,0,3496500,2720,2720,0,3656242,2725,2725,0,3170717,2707,2707,0,3169735,2742,2742,0,3253209,2744,2744,0,3890092,2737,2737,0,3069789,2716,2716,0,3595758,2736,2736,0,3015176,2724,2724,0,3687216,2756,2756,0,3106520,2756,2756,0,4237156,2768,2768,0,3105540,2746,2746,0,3358141,2744,2744,0,3218054,2748,2748,0,3078502,2700,2700,0,2877904,2739,2739,0,4015336,2724,2724,0,3138255,2711,2711,0,3700361,2760,2760,0,3405314,2710,2710,0,3221275,2749,2749,0,3450631,2728,2728,0,2844359,2717,2717,0,2959011,2716,2716,0,3542425,2752,2752,0,2866822,2739,2739,0,2599880,2757,2757,0,3369847,2731,2731,0,3481744,2722,2722,0,2751536,2728,2728,0,3157248,2757,2757,64,0x7f399fc26e80,1797,0,0,1360084,2530,0,0,1534985,1156,0,0,1319985,4323,0,0,1695977,2177,0,0,1419788,1030,0,0,1353190,3272,0,0,1687855,2304,0,0,1499520,65,0,0,1170703,1085,0,0,1322718,763,0,0,1270235,3255,0,0,1621990,1263,0,0,1274922,1361,0,0,1339329,1362,0,0,1416040,3535,0,0,1605487,1309,0,0,1279842,1190,0,0,1260519,3864,0,0,1624298,3192,0,0,1568979,572,0,0,1298418,1787,0,0,1438456,3539,0,0,1656845,2282,0,0,1552154,658,0,0,1291293,1066,0,0,1335287,2735,0,0,1548004,3480,0,0,1569792,1332,0,0,1300340,1891,0,0,1385489,2664,0,0,1592361,3400,0,0,1551854,6401146207402,6401146226282
|
||||
@@ -0,0 +1,2 @@
|
||||
workload_name,command,host_name,host_cpu,sbios,host_distro,host_kernel,host_rocmver,date,gpu_soc,vbios,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,totalL2Banks,LDSBanks,name,numSQC,numPipes,hbmBW,compute_partition,memory_partition,ip_blocks
|
||||
device_inv_int,./tests/vcopy -n 1048576 -b 256 -i 3,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,5.7.1-98,Mon Feb 19 13:25:16 2024 (CST),gfx908,113-D3431401-100,8,120,4,64,40,1024,16,8192,1502,1200,1502,1200,32,32,32,MI100,30,4,1200,,,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
|
||||
|
@@ -0,0 +1,4 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
|
||||
0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,181625,181625,1048576,256,0,0,8,8,16,64,0x0,0x7f124867ce80,6401146016248,6401146042762,6401146066762,6401146079037
|
||||
1,"vecCopy(double*, double*, double*, int, int) ",2,0,2,181625,181625,1048576,256,0,0,8,8,16,64,0x0,0x7f124867ce80,6401146079558,6401146167882,6401146186922,6401146188174
|
||||
2,"vecCopy(double*, double*, double*, int, int) ",2,0,4,181625,181625,1048576,256,0,0,8,8,16,64,0x0,0x7f124867ce80,6401146198824,6401146207402,6401146226282,6401146227678
|
||||
|
@@ -0,0 +1,2 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
|
||||
0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,103052,103052,1048576,256,0,0,8,8,16,64,0x0,0x7fe965116e80,47544,47544,16384,65536,13103,1693740,4876162203440,4881310843226,4881310867386,4876170172288
|
||||
|
@@ -0,0 +1,2 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
|
||||
0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,101830,101830,1048576,256,0,0,8,8,16,64,0x0,0x7fb30b508e80,0,0,0,4870225346608,4881310843226,4881310867386,4870233229204
|
||||
|
@@ -0,0 +1,2 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
|
||||
0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,100812,100812,1048576,256,0,0,8,8,16,64,0x0,0x7f3f44bd2e80,65536,195450,25045552,4865251370909,4881310843226,4881310867386,4865258954789
|
||||
|
@@ -0,0 +1,2 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
|
||||
0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,103458,103458,1048576,256,0,0,8,8,16,64,0x0,0x7fa2e8b18e80,32768,633554,81092720,4878063446499,4881310843226,4881310867386,4878071065706
|
||||
|
@@ -0,0 +1,2 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
|
||||
0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,99996,99996,1048576,256,0,0,8,8,16,64,0x0,0x7fec3b190e80,47808,47808,16527,382472,16384,24462222,233988,0,98360336,4861216749685,4881310843226,4881310867386,4861224344736
|
||||
|
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
File renamed without changes.
@@ -0,0 +1,5 @@
|
||||
pmc: SQ_CYCLES SQ_BUSY_CYCLES SQ_BUSY_CU_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQC_TC_INST_REQ SQC_TC_DATA_READ_REQ SQC_TC_DATA_WRITE_REQ GRBM_COUNT GRBM_GUI_ACTIVE TCP_GATE_EN1_sum TCP_GATE_EN2_sum TCP_TD_TCP_STALL_CYCLES_sum TCP_TCR_TCP_STALL_CYCLES_sum TA_TA_BUSY_sum TA_BUFFER_WAVEFRONTS_sum TD_TD_BUSY_sum TD_TC_STALL_sum SPI_CSN_WINDOW_VALID SPI_CSN_BUSY CPC_CPC_STAT_BUSY CPC_CPC_STAT_IDLE CPF_CPF_STAT_BUSY CPF_CPF_STAT_STALL TCC_CYCLE_sum TCC_BUSY_sum TCC_PROBE_sum TCC_PROBE_ALL_sum
|
||||
|
||||
gpu:
|
||||
range: 0
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQC_TC_DATA_ATOMIC_REQ SQC_TC_STALL SQC_TC_REQ SQC_DCACHE_REQ_READ_16 SQC_ICACHE_REQ SQC_ICACHE_HITS SQC_ICACHE_MISSES SQC_ICACHE_MISSES_DUPLICATE GRBM_SPI_BUSY TCP_READ_TAGCONFLICT_STALL_CYCLES_sum TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum TCP_TA_TCP_STATE_READ_sum TA_BUFFER_READ_WAVEFRONTS_sum TA_BUFFER_WRITE_WAVEFRONTS_sum TD_COALESCABLE_WAVEFRONT_sum TD_LOAD_WAVEFRONT_sum SPI_CSN_NUM_THREADGROUPS SPI_CSN_WAVE CPC_CPC_TCIU_BUSY CPC_CPC_TCIU_IDLE CPF_CPF_TCIU_BUSY CPF_CPF_TCIU_STALL TCC_NC_REQ_sum TCC_UC_REQ_sum TCC_CC_REQ_sum TCC_RW_REQ_sum
|
||||
|
||||
gpu:
|
||||
range: 0
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: TCC_EA_ATOMIC_LEVEL_sum
|
||||
|
||||
gpu:
|
||||
range: 0
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: TCC_ATOMIC[0] TCC_CYCLE[0] TCC_EA_ATOMIC[0] TCC_EA_ATOMIC_LEVEL[0] TCC_ATOMIC[1] TCC_CYCLE[1] TCC_EA_ATOMIC[1] TCC_EA_ATOMIC_LEVEL[1] TCC_ATOMIC[2] TCC_CYCLE[2] TCC_EA_ATOMIC[2] TCC_EA_ATOMIC_LEVEL[2] TCC_ATOMIC[3] TCC_CYCLE[3] TCC_EA_ATOMIC[3] TCC_EA_ATOMIC_LEVEL[3] TCC_ATOMIC[4] TCC_CYCLE[4] TCC_EA_ATOMIC[4] TCC_EA_ATOMIC_LEVEL[4] TCC_ATOMIC[5] TCC_CYCLE[5] TCC_EA_ATOMIC[5] TCC_EA_ATOMIC_LEVEL[5] TCC_ATOMIC[6] TCC_CYCLE[6] TCC_EA_ATOMIC[6] TCC_EA_ATOMIC_LEVEL[6] TCC_ATOMIC[7] TCC_CYCLE[7] TCC_EA_ATOMIC[7] TCC_EA_ATOMIC_LEVEL[7] TCC_ATOMIC[8] TCC_CYCLE[8] TCC_EA_ATOMIC[8] TCC_EA_ATOMIC_LEVEL[8] TCC_ATOMIC[9] TCC_CYCLE[9] TCC_EA_ATOMIC[9] TCC_EA_ATOMIC_LEVEL[9] TCC_ATOMIC[10] TCC_CYCLE[10] TCC_EA_ATOMIC[10] TCC_EA_ATOMIC_LEVEL[10] TCC_ATOMIC[11] TCC_CYCLE[11] TCC_EA_ATOMIC[11] TCC_EA_ATOMIC_LEVEL[11] TCC_ATOMIC[12] TCC_CYCLE[12] TCC_EA_ATOMIC[12] TCC_EA_ATOMIC_LEVEL[12] TCC_ATOMIC[13] TCC_CYCLE[13] TCC_EA_ATOMIC[13] TCC_EA_ATOMIC_LEVEL[13] TCC_ATOMIC[14] TCC_CYCLE[14] TCC_EA_ATOMIC[14] TCC_EA_ATOMIC_LEVEL[14] TCC_ATOMIC[15] TCC_CYCLE[15] TCC_EA_ATOMIC[15] TCC_EA_ATOMIC_LEVEL[15] TCC_ATOMIC[16] TCC_CYCLE[16] TCC_EA_ATOMIC[16] TCC_EA_ATOMIC_LEVEL[16] TCC_ATOMIC[17] TCC_CYCLE[17] TCC_EA_ATOMIC[17] TCC_EA_ATOMIC_LEVEL[17] TCC_ATOMIC[18] TCC_CYCLE[18] TCC_EA_ATOMIC[18] TCC_EA_ATOMIC_LEVEL[18] TCC_ATOMIC[19] TCC_CYCLE[19] TCC_EA_ATOMIC[19] TCC_EA_ATOMIC_LEVEL[19] TCC_ATOMIC[20] TCC_CYCLE[20] TCC_EA_ATOMIC[20] TCC_EA_ATOMIC_LEVEL[20] TCC_ATOMIC[21] TCC_CYCLE[21] TCC_EA_ATOMIC[21] TCC_EA_ATOMIC_LEVEL[21] TCC_ATOMIC[22] TCC_CYCLE[22] TCC_EA_ATOMIC[22] TCC_EA_ATOMIC_LEVEL[22] TCC_ATOMIC[23] TCC_CYCLE[23] TCC_EA_ATOMIC[23] TCC_EA_ATOMIC_LEVEL[23] TCC_ATOMIC[24] TCC_CYCLE[24] TCC_EA_ATOMIC[24] TCC_EA_ATOMIC_LEVEL[24] TCC_ATOMIC[25] TCC_CYCLE[25] TCC_EA_ATOMIC[25] TCC_EA_ATOMIC_LEVEL[25] TCC_ATOMIC[26] TCC_CYCLE[26] TCC_EA_ATOMIC[26] TCC_EA_ATOMIC_LEVEL[26] TCC_ATOMIC[27] TCC_CYCLE[27] TCC_EA_ATOMIC[27] TCC_EA_ATOMIC_LEVEL[27] TCC_ATOMIC[28] TCC_CYCLE[28] TCC_EA_ATOMIC[28] TCC_EA_ATOMIC_LEVEL[28] TCC_ATOMIC[29] TCC_CYCLE[29] TCC_EA_ATOMIC[29] TCC_EA_ATOMIC_LEVEL[29] TCC_ATOMIC[30] TCC_CYCLE[30] TCC_EA_ATOMIC[30] TCC_EA_ATOMIC_LEVEL[30] TCC_ATOMIC[31] TCC_CYCLE[31] TCC_EA_ATOMIC[31] TCC_EA_ATOMIC_LEVEL[31]
|
||||
|
||||
gpu:
|
||||
range: 0
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: TCC_EA_RDREQ[0] TCC_EA_RDREQ_32B[0] TCC_EA_RDREQ_DRAM_CREDIT_STALL[0] TCC_EA_RDREQ_GMI_CREDIT_STALL[0] TCC_EA_RDREQ[1] TCC_EA_RDREQ_32B[1] TCC_EA_RDREQ_DRAM_CREDIT_STALL[1] TCC_EA_RDREQ_GMI_CREDIT_STALL[1] TCC_EA_RDREQ[2] TCC_EA_RDREQ_32B[2] TCC_EA_RDREQ_DRAM_CREDIT_STALL[2] TCC_EA_RDREQ_GMI_CREDIT_STALL[2] TCC_EA_RDREQ[3] TCC_EA_RDREQ_32B[3] TCC_EA_RDREQ_DRAM_CREDIT_STALL[3] TCC_EA_RDREQ_GMI_CREDIT_STALL[3] TCC_EA_RDREQ[4] TCC_EA_RDREQ_32B[4] TCC_EA_RDREQ_DRAM_CREDIT_STALL[4] TCC_EA_RDREQ_GMI_CREDIT_STALL[4] TCC_EA_RDREQ[5] TCC_EA_RDREQ_32B[5] TCC_EA_RDREQ_DRAM_CREDIT_STALL[5] TCC_EA_RDREQ_GMI_CREDIT_STALL[5] TCC_EA_RDREQ[6] TCC_EA_RDREQ_32B[6] TCC_EA_RDREQ_DRAM_CREDIT_STALL[6] TCC_EA_RDREQ_GMI_CREDIT_STALL[6] TCC_EA_RDREQ[7] TCC_EA_RDREQ_32B[7] TCC_EA_RDREQ_DRAM_CREDIT_STALL[7] TCC_EA_RDREQ_GMI_CREDIT_STALL[7] TCC_EA_RDREQ[8] TCC_EA_RDREQ_32B[8] TCC_EA_RDREQ_DRAM_CREDIT_STALL[8] TCC_EA_RDREQ_GMI_CREDIT_STALL[8] TCC_EA_RDREQ[9] TCC_EA_RDREQ_32B[9] TCC_EA_RDREQ_DRAM_CREDIT_STALL[9] TCC_EA_RDREQ_GMI_CREDIT_STALL[9] TCC_EA_RDREQ[10] TCC_EA_RDREQ_32B[10] TCC_EA_RDREQ_DRAM_CREDIT_STALL[10] TCC_EA_RDREQ_GMI_CREDIT_STALL[10] TCC_EA_RDREQ[11] TCC_EA_RDREQ_32B[11] TCC_EA_RDREQ_DRAM_CREDIT_STALL[11] TCC_EA_RDREQ_GMI_CREDIT_STALL[11] TCC_EA_RDREQ[12] TCC_EA_RDREQ_32B[12] TCC_EA_RDREQ_DRAM_CREDIT_STALL[12] TCC_EA_RDREQ_GMI_CREDIT_STALL[12] TCC_EA_RDREQ[13] TCC_EA_RDREQ_32B[13] TCC_EA_RDREQ_DRAM_CREDIT_STALL[13] TCC_EA_RDREQ_GMI_CREDIT_STALL[13] TCC_EA_RDREQ[14] TCC_EA_RDREQ_32B[14] TCC_EA_RDREQ_DRAM_CREDIT_STALL[14] TCC_EA_RDREQ_GMI_CREDIT_STALL[14] TCC_EA_RDREQ[15] TCC_EA_RDREQ_32B[15] TCC_EA_RDREQ_DRAM_CREDIT_STALL[15] TCC_EA_RDREQ_GMI_CREDIT_STALL[15] TCC_EA_RDREQ[16] TCC_EA_RDREQ_32B[16] TCC_EA_RDREQ_DRAM_CREDIT_STALL[16] TCC_EA_RDREQ_GMI_CREDIT_STALL[16] TCC_EA_RDREQ[17] TCC_EA_RDREQ_32B[17] TCC_EA_RDREQ_DRAM_CREDIT_STALL[17] TCC_EA_RDREQ_GMI_CREDIT_STALL[17] TCC_EA_RDREQ[18] TCC_EA_RDREQ_32B[18] TCC_EA_RDREQ_DRAM_CREDIT_STALL[18] TCC_EA_RDREQ_GMI_CREDIT_STALL[18] TCC_EA_RDREQ[19] TCC_EA_RDREQ_32B[19] TCC_EA_RDREQ_DRAM_CREDIT_STALL[19] TCC_EA_RDREQ_GMI_CREDIT_STALL[19] TCC_EA_RDREQ[20] TCC_EA_RDREQ_32B[20] TCC_EA_RDREQ_DRAM_CREDIT_STALL[20] TCC_EA_RDREQ_GMI_CREDIT_STALL[20] TCC_EA_RDREQ[21] TCC_EA_RDREQ_32B[21] TCC_EA_RDREQ_DRAM_CREDIT_STALL[21] TCC_EA_RDREQ_GMI_CREDIT_STALL[21] TCC_EA_RDREQ[22] TCC_EA_RDREQ_32B[22] TCC_EA_RDREQ_DRAM_CREDIT_STALL[22] TCC_EA_RDREQ_GMI_CREDIT_STALL[22] TCC_EA_RDREQ[23] TCC_EA_RDREQ_32B[23] TCC_EA_RDREQ_DRAM_CREDIT_STALL[23] TCC_EA_RDREQ_GMI_CREDIT_STALL[23] TCC_EA_RDREQ[24] TCC_EA_RDREQ_32B[24] TCC_EA_RDREQ_DRAM_CREDIT_STALL[24] TCC_EA_RDREQ_GMI_CREDIT_STALL[24] TCC_EA_RDREQ[25] TCC_EA_RDREQ_32B[25] TCC_EA_RDREQ_DRAM_CREDIT_STALL[25] TCC_EA_RDREQ_GMI_CREDIT_STALL[25] TCC_EA_RDREQ[26] TCC_EA_RDREQ_32B[26] TCC_EA_RDREQ_DRAM_CREDIT_STALL[26] TCC_EA_RDREQ_GMI_CREDIT_STALL[26] TCC_EA_RDREQ[27] TCC_EA_RDREQ_32B[27] TCC_EA_RDREQ_DRAM_CREDIT_STALL[27] TCC_EA_RDREQ_GMI_CREDIT_STALL[27] TCC_EA_RDREQ[28] TCC_EA_RDREQ_32B[28] TCC_EA_RDREQ_DRAM_CREDIT_STALL[28] TCC_EA_RDREQ_GMI_CREDIT_STALL[28] TCC_EA_RDREQ[29] TCC_EA_RDREQ_32B[29] TCC_EA_RDREQ_DRAM_CREDIT_STALL[29] TCC_EA_RDREQ_GMI_CREDIT_STALL[29] TCC_EA_RDREQ[30] TCC_EA_RDREQ_32B[30] TCC_EA_RDREQ_DRAM_CREDIT_STALL[30] TCC_EA_RDREQ_GMI_CREDIT_STALL[30] TCC_EA_RDREQ[31] TCC_EA_RDREQ_32B[31] TCC_EA_RDREQ_DRAM_CREDIT_STALL[31] TCC_EA_RDREQ_GMI_CREDIT_STALL[31]
|
||||
|
||||
gpu:
|
||||
range: 0
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: TCC_EA_RDREQ_IO_CREDIT_STALL[0] TCC_EA_RDREQ_LEVEL[0] TCC_EA_WRREQ[0] TCC_EA_WRREQ_64B[0] TCC_EA_RDREQ_IO_CREDIT_STALL[1] TCC_EA_RDREQ_LEVEL[1] TCC_EA_WRREQ[1] TCC_EA_WRREQ_64B[1] TCC_EA_RDREQ_IO_CREDIT_STALL[2] TCC_EA_RDREQ_LEVEL[2] TCC_EA_WRREQ[2] TCC_EA_WRREQ_64B[2] TCC_EA_RDREQ_IO_CREDIT_STALL[3] TCC_EA_RDREQ_LEVEL[3] TCC_EA_WRREQ[3] TCC_EA_WRREQ_64B[3] TCC_EA_RDREQ_IO_CREDIT_STALL[4] TCC_EA_RDREQ_LEVEL[4] TCC_EA_WRREQ[4] TCC_EA_WRREQ_64B[4] TCC_EA_RDREQ_IO_CREDIT_STALL[5] TCC_EA_RDREQ_LEVEL[5] TCC_EA_WRREQ[5] TCC_EA_WRREQ_64B[5] TCC_EA_RDREQ_IO_CREDIT_STALL[6] TCC_EA_RDREQ_LEVEL[6] TCC_EA_WRREQ[6] TCC_EA_WRREQ_64B[6] TCC_EA_RDREQ_IO_CREDIT_STALL[7] TCC_EA_RDREQ_LEVEL[7] TCC_EA_WRREQ[7] TCC_EA_WRREQ_64B[7] TCC_EA_RDREQ_IO_CREDIT_STALL[8] TCC_EA_RDREQ_LEVEL[8] TCC_EA_WRREQ[8] TCC_EA_WRREQ_64B[8] TCC_EA_RDREQ_IO_CREDIT_STALL[9] TCC_EA_RDREQ_LEVEL[9] TCC_EA_WRREQ[9] TCC_EA_WRREQ_64B[9] TCC_EA_RDREQ_IO_CREDIT_STALL[10] TCC_EA_RDREQ_LEVEL[10] TCC_EA_WRREQ[10] TCC_EA_WRREQ_64B[10] TCC_EA_RDREQ_IO_CREDIT_STALL[11] TCC_EA_RDREQ_LEVEL[11] TCC_EA_WRREQ[11] TCC_EA_WRREQ_64B[11] TCC_EA_RDREQ_IO_CREDIT_STALL[12] TCC_EA_RDREQ_LEVEL[12] TCC_EA_WRREQ[12] TCC_EA_WRREQ_64B[12] TCC_EA_RDREQ_IO_CREDIT_STALL[13] TCC_EA_RDREQ_LEVEL[13] TCC_EA_WRREQ[13] TCC_EA_WRREQ_64B[13] TCC_EA_RDREQ_IO_CREDIT_STALL[14] TCC_EA_RDREQ_LEVEL[14] TCC_EA_WRREQ[14] TCC_EA_WRREQ_64B[14] TCC_EA_RDREQ_IO_CREDIT_STALL[15] TCC_EA_RDREQ_LEVEL[15] TCC_EA_WRREQ[15] TCC_EA_WRREQ_64B[15] TCC_EA_RDREQ_IO_CREDIT_STALL[16] TCC_EA_RDREQ_LEVEL[16] TCC_EA_WRREQ[16] TCC_EA_WRREQ_64B[16] TCC_EA_RDREQ_IO_CREDIT_STALL[17] TCC_EA_RDREQ_LEVEL[17] TCC_EA_WRREQ[17] TCC_EA_WRREQ_64B[17] TCC_EA_RDREQ_IO_CREDIT_STALL[18] TCC_EA_RDREQ_LEVEL[18] TCC_EA_WRREQ[18] TCC_EA_WRREQ_64B[18] TCC_EA_RDREQ_IO_CREDIT_STALL[19] TCC_EA_RDREQ_LEVEL[19] TCC_EA_WRREQ[19] TCC_EA_WRREQ_64B[19] TCC_EA_RDREQ_IO_CREDIT_STALL[20] TCC_EA_RDREQ_LEVEL[20] TCC_EA_WRREQ[20] TCC_EA_WRREQ_64B[20] TCC_EA_RDREQ_IO_CREDIT_STALL[21] TCC_EA_RDREQ_LEVEL[21] TCC_EA_WRREQ[21] TCC_EA_WRREQ_64B[21] TCC_EA_RDREQ_IO_CREDIT_STALL[22] TCC_EA_RDREQ_LEVEL[22] TCC_EA_WRREQ[22] TCC_EA_WRREQ_64B[22] TCC_EA_RDREQ_IO_CREDIT_STALL[23] TCC_EA_RDREQ_LEVEL[23] TCC_EA_WRREQ[23] TCC_EA_WRREQ_64B[23] TCC_EA_RDREQ_IO_CREDIT_STALL[24] TCC_EA_RDREQ_LEVEL[24] TCC_EA_WRREQ[24] TCC_EA_WRREQ_64B[24] TCC_EA_RDREQ_IO_CREDIT_STALL[25] TCC_EA_RDREQ_LEVEL[25] TCC_EA_WRREQ[25] TCC_EA_WRREQ_64B[25] TCC_EA_RDREQ_IO_CREDIT_STALL[26] TCC_EA_RDREQ_LEVEL[26] TCC_EA_WRREQ[26] TCC_EA_WRREQ_64B[26] TCC_EA_RDREQ_IO_CREDIT_STALL[27] TCC_EA_RDREQ_LEVEL[27] TCC_EA_WRREQ[27] TCC_EA_WRREQ_64B[27] TCC_EA_RDREQ_IO_CREDIT_STALL[28] TCC_EA_RDREQ_LEVEL[28] TCC_EA_WRREQ[28] TCC_EA_WRREQ_64B[28] TCC_EA_RDREQ_IO_CREDIT_STALL[29] TCC_EA_RDREQ_LEVEL[29] TCC_EA_WRREQ[29] TCC_EA_WRREQ_64B[29] TCC_EA_RDREQ_IO_CREDIT_STALL[30] TCC_EA_RDREQ_LEVEL[30] TCC_EA_WRREQ[30] TCC_EA_WRREQ_64B[30] TCC_EA_RDREQ_IO_CREDIT_STALL[31] TCC_EA_RDREQ_LEVEL[31] TCC_EA_WRREQ[31] TCC_EA_WRREQ_64B[31]
|
||||
|
||||
gpu:
|
||||
range: 0
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: TCC_EA_WRREQ_DRAM_CREDIT_STALL[0] TCC_EA_WRREQ_GMI_CREDIT_STALL[0] TCC_EA_WRREQ_IO_CREDIT_STALL[0] TCC_EA_WRREQ_LEVEL[0] TCC_EA_WRREQ_DRAM_CREDIT_STALL[1] TCC_EA_WRREQ_GMI_CREDIT_STALL[1] TCC_EA_WRREQ_IO_CREDIT_STALL[1] TCC_EA_WRREQ_LEVEL[1] TCC_EA_WRREQ_DRAM_CREDIT_STALL[2] TCC_EA_WRREQ_GMI_CREDIT_STALL[2] TCC_EA_WRREQ_IO_CREDIT_STALL[2] TCC_EA_WRREQ_LEVEL[2] TCC_EA_WRREQ_DRAM_CREDIT_STALL[3] TCC_EA_WRREQ_GMI_CREDIT_STALL[3] TCC_EA_WRREQ_IO_CREDIT_STALL[3] TCC_EA_WRREQ_LEVEL[3] TCC_EA_WRREQ_DRAM_CREDIT_STALL[4] TCC_EA_WRREQ_GMI_CREDIT_STALL[4] TCC_EA_WRREQ_IO_CREDIT_STALL[4] TCC_EA_WRREQ_LEVEL[4] TCC_EA_WRREQ_DRAM_CREDIT_STALL[5] TCC_EA_WRREQ_GMI_CREDIT_STALL[5] TCC_EA_WRREQ_IO_CREDIT_STALL[5] TCC_EA_WRREQ_LEVEL[5] TCC_EA_WRREQ_DRAM_CREDIT_STALL[6] TCC_EA_WRREQ_GMI_CREDIT_STALL[6] TCC_EA_WRREQ_IO_CREDIT_STALL[6] TCC_EA_WRREQ_LEVEL[6] TCC_EA_WRREQ_DRAM_CREDIT_STALL[7] TCC_EA_WRREQ_GMI_CREDIT_STALL[7] TCC_EA_WRREQ_IO_CREDIT_STALL[7] TCC_EA_WRREQ_LEVEL[7] TCC_EA_WRREQ_DRAM_CREDIT_STALL[8] TCC_EA_WRREQ_GMI_CREDIT_STALL[8] TCC_EA_WRREQ_IO_CREDIT_STALL[8] TCC_EA_WRREQ_LEVEL[8] TCC_EA_WRREQ_DRAM_CREDIT_STALL[9] TCC_EA_WRREQ_GMI_CREDIT_STALL[9] TCC_EA_WRREQ_IO_CREDIT_STALL[9] TCC_EA_WRREQ_LEVEL[9] TCC_EA_WRREQ_DRAM_CREDIT_STALL[10] TCC_EA_WRREQ_GMI_CREDIT_STALL[10] TCC_EA_WRREQ_IO_CREDIT_STALL[10] TCC_EA_WRREQ_LEVEL[10] TCC_EA_WRREQ_DRAM_CREDIT_STALL[11] TCC_EA_WRREQ_GMI_CREDIT_STALL[11] TCC_EA_WRREQ_IO_CREDIT_STALL[11] TCC_EA_WRREQ_LEVEL[11] TCC_EA_WRREQ_DRAM_CREDIT_STALL[12] TCC_EA_WRREQ_GMI_CREDIT_STALL[12] TCC_EA_WRREQ_IO_CREDIT_STALL[12] TCC_EA_WRREQ_LEVEL[12] TCC_EA_WRREQ_DRAM_CREDIT_STALL[13] TCC_EA_WRREQ_GMI_CREDIT_STALL[13] TCC_EA_WRREQ_IO_CREDIT_STALL[13] TCC_EA_WRREQ_LEVEL[13] TCC_EA_WRREQ_DRAM_CREDIT_STALL[14] TCC_EA_WRREQ_GMI_CREDIT_STALL[14] TCC_EA_WRREQ_IO_CREDIT_STALL[14] TCC_EA_WRREQ_LEVEL[14] TCC_EA_WRREQ_DRAM_CREDIT_STALL[15] TCC_EA_WRREQ_GMI_CREDIT_STALL[15] TCC_EA_WRREQ_IO_CREDIT_STALL[15] TCC_EA_WRREQ_LEVEL[15] TCC_EA_WRREQ_DRAM_CREDIT_STALL[16] TCC_EA_WRREQ_GMI_CREDIT_STALL[16] TCC_EA_WRREQ_IO_CREDIT_STALL[16] TCC_EA_WRREQ_LEVEL[16] TCC_EA_WRREQ_DRAM_CREDIT_STALL[17] TCC_EA_WRREQ_GMI_CREDIT_STALL[17] TCC_EA_WRREQ_IO_CREDIT_STALL[17] TCC_EA_WRREQ_LEVEL[17] TCC_EA_WRREQ_DRAM_CREDIT_STALL[18] TCC_EA_WRREQ_GMI_CREDIT_STALL[18] TCC_EA_WRREQ_IO_CREDIT_STALL[18] TCC_EA_WRREQ_LEVEL[18] TCC_EA_WRREQ_DRAM_CREDIT_STALL[19] TCC_EA_WRREQ_GMI_CREDIT_STALL[19] TCC_EA_WRREQ_IO_CREDIT_STALL[19] TCC_EA_WRREQ_LEVEL[19] TCC_EA_WRREQ_DRAM_CREDIT_STALL[20] TCC_EA_WRREQ_GMI_CREDIT_STALL[20] TCC_EA_WRREQ_IO_CREDIT_STALL[20] TCC_EA_WRREQ_LEVEL[20] TCC_EA_WRREQ_DRAM_CREDIT_STALL[21] TCC_EA_WRREQ_GMI_CREDIT_STALL[21] TCC_EA_WRREQ_IO_CREDIT_STALL[21] TCC_EA_WRREQ_LEVEL[21] TCC_EA_WRREQ_DRAM_CREDIT_STALL[22] TCC_EA_WRREQ_GMI_CREDIT_STALL[22] TCC_EA_WRREQ_IO_CREDIT_STALL[22] TCC_EA_WRREQ_LEVEL[22] TCC_EA_WRREQ_DRAM_CREDIT_STALL[23] TCC_EA_WRREQ_GMI_CREDIT_STALL[23] TCC_EA_WRREQ_IO_CREDIT_STALL[23] TCC_EA_WRREQ_LEVEL[23] TCC_EA_WRREQ_DRAM_CREDIT_STALL[24] TCC_EA_WRREQ_GMI_CREDIT_STALL[24] TCC_EA_WRREQ_IO_CREDIT_STALL[24] TCC_EA_WRREQ_LEVEL[24] TCC_EA_WRREQ_DRAM_CREDIT_STALL[25] TCC_EA_WRREQ_GMI_CREDIT_STALL[25] TCC_EA_WRREQ_IO_CREDIT_STALL[25] TCC_EA_WRREQ_LEVEL[25] TCC_EA_WRREQ_DRAM_CREDIT_STALL[26] TCC_EA_WRREQ_GMI_CREDIT_STALL[26] TCC_EA_WRREQ_IO_CREDIT_STALL[26] TCC_EA_WRREQ_LEVEL[26] TCC_EA_WRREQ_DRAM_CREDIT_STALL[27] TCC_EA_WRREQ_GMI_CREDIT_STALL[27] TCC_EA_WRREQ_IO_CREDIT_STALL[27] TCC_EA_WRREQ_LEVEL[27] TCC_EA_WRREQ_DRAM_CREDIT_STALL[28] TCC_EA_WRREQ_GMI_CREDIT_STALL[28] TCC_EA_WRREQ_IO_CREDIT_STALL[28] TCC_EA_WRREQ_LEVEL[28] TCC_EA_WRREQ_DRAM_CREDIT_STALL[29] TCC_EA_WRREQ_GMI_CREDIT_STALL[29] TCC_EA_WRREQ_IO_CREDIT_STALL[29] TCC_EA_WRREQ_LEVEL[29] TCC_EA_WRREQ_DRAM_CREDIT_STALL[30] TCC_EA_WRREQ_GMI_CREDIT_STALL[30] TCC_EA_WRREQ_IO_CREDIT_STALL[30] TCC_EA_WRREQ_LEVEL[30] TCC_EA_WRREQ_DRAM_CREDIT_STALL[31] TCC_EA_WRREQ_GMI_CREDIT_STALL[31] TCC_EA_WRREQ_IO_CREDIT_STALL[31] TCC_EA_WRREQ_LEVEL[31]
|
||||
|
||||
gpu:
|
||||
range: 0
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: TCC_HIT[0] TCC_MISS[0] TCC_READ[0] TCC_REQ[0] TCC_HIT[1] TCC_MISS[1] TCC_READ[1] TCC_REQ[1] TCC_HIT[2] TCC_MISS[2] TCC_READ[2] TCC_REQ[2] TCC_HIT[3] TCC_MISS[3] TCC_READ[3] TCC_REQ[3] TCC_HIT[4] TCC_MISS[4] TCC_READ[4] TCC_REQ[4] TCC_HIT[5] TCC_MISS[5] TCC_READ[5] TCC_REQ[5] TCC_HIT[6] TCC_MISS[6] TCC_READ[6] TCC_REQ[6] TCC_HIT[7] TCC_MISS[7] TCC_READ[7] TCC_REQ[7] TCC_HIT[8] TCC_MISS[8] TCC_READ[8] TCC_REQ[8] TCC_HIT[9] TCC_MISS[9] TCC_READ[9] TCC_REQ[9] TCC_HIT[10] TCC_MISS[10] TCC_READ[10] TCC_REQ[10] TCC_HIT[11] TCC_MISS[11] TCC_READ[11] TCC_REQ[11] TCC_HIT[12] TCC_MISS[12] TCC_READ[12] TCC_REQ[12] TCC_HIT[13] TCC_MISS[13] TCC_READ[13] TCC_REQ[13] TCC_HIT[14] TCC_MISS[14] TCC_READ[14] TCC_REQ[14] TCC_HIT[15] TCC_MISS[15] TCC_READ[15] TCC_REQ[15] TCC_HIT[16] TCC_MISS[16] TCC_READ[16] TCC_REQ[16] TCC_HIT[17] TCC_MISS[17] TCC_READ[17] TCC_REQ[17] TCC_HIT[18] TCC_MISS[18] TCC_READ[18] TCC_REQ[18] TCC_HIT[19] TCC_MISS[19] TCC_READ[19] TCC_REQ[19] TCC_HIT[20] TCC_MISS[20] TCC_READ[20] TCC_REQ[20] TCC_HIT[21] TCC_MISS[21] TCC_READ[21] TCC_REQ[21] TCC_HIT[22] TCC_MISS[22] TCC_READ[22] TCC_REQ[22] TCC_HIT[23] TCC_MISS[23] TCC_READ[23] TCC_REQ[23] TCC_HIT[24] TCC_MISS[24] TCC_READ[24] TCC_REQ[24] TCC_HIT[25] TCC_MISS[25] TCC_READ[25] TCC_REQ[25] TCC_HIT[26] TCC_MISS[26] TCC_READ[26] TCC_REQ[26] TCC_HIT[27] TCC_MISS[27] TCC_READ[27] TCC_REQ[27] TCC_HIT[28] TCC_MISS[28] TCC_READ[28] TCC_REQ[28] TCC_HIT[29] TCC_MISS[29] TCC_READ[29] TCC_REQ[29] TCC_HIT[30] TCC_MISS[30] TCC_READ[30] TCC_REQ[30] TCC_HIT[31] TCC_MISS[31] TCC_READ[31] TCC_REQ[31]
|
||||
|
||||
gpu:
|
||||
range: 0
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: TCC_RW_REQ[0] TCC_TOO_MANY_EA_WRREQS_STALL[0] TCC_WRITE[0] TCC_RW_REQ[1] TCC_TOO_MANY_EA_WRREQS_STALL[1] TCC_WRITE[1] TCC_RW_REQ[2] TCC_TOO_MANY_EA_WRREQS_STALL[2] TCC_WRITE[2] TCC_RW_REQ[3] TCC_TOO_MANY_EA_WRREQS_STALL[3] TCC_WRITE[3] TCC_RW_REQ[4] TCC_TOO_MANY_EA_WRREQS_STALL[4] TCC_WRITE[4] TCC_RW_REQ[5] TCC_TOO_MANY_EA_WRREQS_STALL[5] TCC_WRITE[5] TCC_RW_REQ[6] TCC_TOO_MANY_EA_WRREQS_STALL[6] TCC_WRITE[6] TCC_RW_REQ[7] TCC_TOO_MANY_EA_WRREQS_STALL[7] TCC_WRITE[7] TCC_RW_REQ[8] TCC_TOO_MANY_EA_WRREQS_STALL[8] TCC_WRITE[8] TCC_RW_REQ[9] TCC_TOO_MANY_EA_WRREQS_STALL[9] TCC_WRITE[9] TCC_RW_REQ[10] TCC_TOO_MANY_EA_WRREQS_STALL[10] TCC_WRITE[10] TCC_RW_REQ[11] TCC_TOO_MANY_EA_WRREQS_STALL[11] TCC_WRITE[11] TCC_RW_REQ[12] TCC_TOO_MANY_EA_WRREQS_STALL[12] TCC_WRITE[12] TCC_RW_REQ[13] TCC_TOO_MANY_EA_WRREQS_STALL[13] TCC_WRITE[13] TCC_RW_REQ[14] TCC_TOO_MANY_EA_WRREQS_STALL[14] TCC_WRITE[14] TCC_RW_REQ[15] TCC_TOO_MANY_EA_WRREQS_STALL[15] TCC_WRITE[15] TCC_RW_REQ[16] TCC_TOO_MANY_EA_WRREQS_STALL[16] TCC_WRITE[16] TCC_RW_REQ[17] TCC_TOO_MANY_EA_WRREQS_STALL[17] TCC_WRITE[17] TCC_RW_REQ[18] TCC_TOO_MANY_EA_WRREQS_STALL[18] TCC_WRITE[18] TCC_RW_REQ[19] TCC_TOO_MANY_EA_WRREQS_STALL[19] TCC_WRITE[19] TCC_RW_REQ[20] TCC_TOO_MANY_EA_WRREQS_STALL[20] TCC_WRITE[20] TCC_RW_REQ[21] TCC_TOO_MANY_EA_WRREQS_STALL[21] TCC_WRITE[21] TCC_RW_REQ[22] TCC_TOO_MANY_EA_WRREQS_STALL[22] TCC_WRITE[22] TCC_RW_REQ[23] TCC_TOO_MANY_EA_WRREQS_STALL[23] TCC_WRITE[23] TCC_RW_REQ[24] TCC_TOO_MANY_EA_WRREQS_STALL[24] TCC_WRITE[24] TCC_RW_REQ[25] TCC_TOO_MANY_EA_WRREQS_STALL[25] TCC_WRITE[25] TCC_RW_REQ[26] TCC_TOO_MANY_EA_WRREQS_STALL[26] TCC_WRITE[26] TCC_RW_REQ[27] TCC_TOO_MANY_EA_WRREQS_STALL[27] TCC_WRITE[27] TCC_RW_REQ[28] TCC_TOO_MANY_EA_WRREQS_STALL[28] TCC_WRITE[28] TCC_RW_REQ[29] TCC_TOO_MANY_EA_WRREQS_STALL[29] TCC_WRITE[29] TCC_RW_REQ[30] TCC_TOO_MANY_EA_WRREQS_STALL[30] TCC_WRITE[30] TCC_RW_REQ[31] TCC_TOO_MANY_EA_WRREQS_STALL[31] TCC_WRITE[31]
|
||||
|
||||
gpu:
|
||||
range: 0
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQC_DCACHE_INPUT_VALID_READYB SQC_DCACHE_ATOMIC SQC_DCACHE_REQ_READ_8 SQC_DCACHE_REQ SQC_DCACHE_HITS SQC_DCACHE_MISSES SQC_DCACHE_MISSES_DUPLICATE SQC_DCACHE_REQ_READ_1 TCP_VOLATILE_sum TCP_TOTAL_ACCESSES_sum TCP_TOTAL_READ_sum TCP_TOTAL_WRITE_sum TA_BUFFER_ATOMIC_WAVEFRONTS_sum TA_BUFFER_TOTAL_CYCLES_sum TD_ATOMIC_WAVEFRONT_sum TD_STORE_WAVEFRONT_sum SPI_RA_REQ_NO_ALLOC SPI_RA_REQ_NO_ALLOC_CSN CPC_CPC_STAT_STALL CPC_UTCL1_STALL_ON_TRANSLATION CPF_CPF_STAT_IDLE CPF_CPF_TCIU_IDLE TCC_REQ_sum TCC_STREAMING_REQ_sum TCC_HIT_sum TCC_MISS_sum
|
||||
|
||||
gpu:
|
||||
range: 0
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQC_DCACHE_REQ_READ_2 SQC_DCACHE_REQ_READ_4 SQ_INSTS_VMEM_WR SQ_INSTS_VMEM_RD SQ_INSTS_VMEM SQ_INSTS_SALU SQ_INSTS_VSKIPPED SQ_INSTS_SMEM TCP_TOTAL_ATOMIC_WITH_RET_sum TCP_TOTAL_ATOMIC_WITHOUT_RET_sum TCP_TOTAL_WRITEBACK_INVALIDATES_sum TCP_TOTAL_CACHE_ACCESSES_sum TA_BUFFER_COALESCED_READ_CYCLES_sum TA_BUFFER_COALESCED_WRITE_CYCLES_sum SPI_RA_RES_STALL_CSN SPI_RA_TMP_STALL_CSN CPC_CPC_UTCL2IU_BUSY CPC_CPC_UTCL2IU_IDLE CPF_CMP_UTCL1_STALL_ON_TRANSLATION TCC_READ_sum TCC_WRITE_sum TCC_ATOMIC_sum TCC_WRITEBACK_sum
|
||||
|
||||
gpu:
|
||||
range: 0
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQ_INSTS_FLAT SQ_INSTS_LDS SQ_INSTS_GDS SQ_INSTS_EXP_GDS SQ_INSTS_BRANCH SQ_INSTS_SENDMSG SQ_INSTS SQ_WAIT_ANY TCP_UTCL1_TRANSLATION_MISS_sum TCP_UTCL1_TRANSLATION_HIT_sum TCP_UTCL1_PERMISSION_MISS_sum TCP_UTCL1_REQUEST_sum TA_ADDR_STALLED_BY_TC_CYCLES_sum TA_TOTAL_WAVEFRONTS_sum SPI_RA_WAVE_SIMD_FULL_CSN SPI_RA_VGPR_SIMD_FULL_CSN CPC_CPC_UTCL2IU_STALL CPC_ME1_BUSY_FOR_PACKET_DECODE TCC_EA_WRREQ_sum TCC_EA_WRREQ_64B_sum TCC_EA_WR_UNCACHED_32B_sum TCC_EA_WRREQ_DRAM_sum
|
||||
|
||||
gpu:
|
||||
range: 0
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQ_WAIT_INST_ANY SQ_ACTIVE_INST_ANY SQ_INSTS_VALU SQ_ACTIVE_INST_VMEM SQ_ACTIVE_INST_LDS SQ_ACTIVE_INST_VALU SQ_ACTIVE_INST_SCA SQ_ACTIVE_INST_EXP_GDS TCP_TCP_LATENCY_sum TCP_TCC_READ_REQ_LATENCY_sum TCP_TCC_WRITE_REQ_LATENCY_sum TCP_TCC_READ_REQ_sum TA_ADDR_STALLED_BY_TD_CYCLES_sum TA_DATA_STALLED_BY_TC_CYCLES_sum SPI_RA_SGPR_SIMD_FULL_CSN SPI_RA_LDS_CU_FULL_CSN CPC_ME1_DC0_SPI_BUSY TCC_EA_WRREQ_STALL_sum TCC_EA_WRREQ_IO_CREDIT_STALL_sum TCC_EA_WRREQ_GMI_CREDIT_STALL_sum TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum
|
||||
|
||||
gpu:
|
||||
range: 0
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQ_ACTIVE_INST_MISC SQ_ACTIVE_INST_FLAT SQ_INST_CYCLES_VMEM_WR SQ_INST_CYCLES_VMEM_RD SQ_INST_CYCLES_SMEM SQ_INST_CYCLES_SALU SQ_THREAD_CYCLES_VALU SQ_IFETCH TCP_TCC_WRITE_REQ_sum TCP_TCC_ATOMIC_WITH_RET_REQ_sum TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum TCP_TCC_NC_READ_REQ_sum TA_FLAT_WAVEFRONTS_sum TA_FLAT_READ_WAVEFRONTS_sum SPI_RA_BAR_CU_FULL_CSN SPI_RA_TGLIM_CU_FULL_CSN TCC_EA_RDREQ_sum TCC_EA_RDREQ_32B_sum TCC_EA_RD_UNCACHED_32B_sum TCC_EA_RDREQ_DRAM_sum
|
||||
|
||||
gpu:
|
||||
range: 0
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQ_LDS_BANK_CONFLICT SQ_LDS_ADDR_CONFLICT SQ_LDS_UNALIGNED_STALL SQ_WAVES_EQ_64 SQ_WAVES_LT_64 SQ_WAVES_LT_48 SQ_WAVES_LT_32 SQ_WAVES_LT_16 TCP_TCC_NC_WRITE_REQ_sum TCP_TCC_NC_ATOMIC_REQ_sum TCP_TCC_UC_READ_REQ_sum TCP_TCC_UC_WRITE_REQ_sum TA_FLAT_WRITE_WAVEFRONTS_sum TA_FLAT_ATOMIC_WAVEFRONTS_sum SPI_RA_WVLIM_STALL_CSN SPI_SWC_CSC_WR TCC_EA_RDREQ_IO_CREDIT_STALL_sum TCC_EA_RDREQ_GMI_CREDIT_STALL_sum TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum TCC_TAG_STALL_sum
|
||||
|
||||
gpu:
|
||||
range: 0
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQ_ITEMS SQ_LDS_MEM_VIOLATIONS SQ_LDS_ATOMIC_RETURN SQ_LDS_IDX_ACTIVE SQ_WAVES_RESTORED SQ_WAVES_SAVED SQ_INSTS_SMEM_NORM TCP_TCC_UC_ATOMIC_REQ_sum TCP_TCC_CC_READ_REQ_sum TCP_TCC_CC_WRITE_REQ_sum TCP_TCC_CC_ATOMIC_REQ_sum SPI_VWC_CSC_WR SPI_RA_BULKY_CU_FULL_CSN TCC_NORMAL_WRITEBACK_sum TCC_ALL_TC_OP_WB_WRITEBACK_sum TCC_NORMAL_EVICT_sum TCC_ALL_TC_OP_INV_EVICT_sum
|
||||
|
||||
gpu:
|
||||
range: 0
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: TCP_TCC_RW_READ_REQ_sum TCP_TCC_RW_WRITE_REQ_sum TCP_TCC_RW_ATOMIC_REQ_sum TCP_PENDING_STALL_CYCLES_sum TCC_TOO_MANY_EA_WRREQS_STALL_sum TCC_EA_ATOMIC_sum TCC_EA_RDREQ_LEVEL_sum TCC_EA_WRREQ_LEVEL_sum
|
||||
|
||||
gpu:
|
||||
range: 0
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc:
|
||||
|
||||
gpu:
|
||||
range: 0
|
||||
kernel:
|
||||
@@ -0,0 +1,2 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,obj,TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],wave_size_1,obj_1,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SQ_INSTS_SMEM_NORM,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,wave_size_2,obj_2,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,TCC_EA_ATOMIC_sum,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,wave_size_3,obj_3,TCC_EA_ATOMIC_LEVEL_sum,wave_size_4,obj_4,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,TCC_EA_RDREQ_DRAM_sum,wave_size_5,obj_5,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_SLine truncated
|
||||
0,"vecCopy(double*, double*, double*, int, int) ",2,1048576,256,0,0,8,8,16,64,0x7f91dd28ee80,8192,0,4096,8192,0,4096,8336,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,64,0x7f580b6a6e80,1048576,0,0,0,0,0,131072,0.0,0.0,0.0,0.0,16384,0,86448.0,44624.0,131111.0,0.0,64,0x7fa33d1dce80,131072.0,131072.0,0.0,2534709.0,0.0,0.0,126704913.0,60098733.0,64,0x7f3404ff8e80,0.0,64,0x7f5e573a8e80,32768,32768,16384,16384,65536,49152,11534336,65536,131072.0,0.0,0.0,0.0,32768.0,16384.0,0,0,131386.0,0.0,620.0,131385.0,64,0x7ffac2522e80,4899,0,0,2154490,5112,0,0,2141628,4242,0,0,2099314,5357,0,0,2015243,2858,0,0,1971340,5525,0,0,2178508,5077,0,0,2125203,5170,0,0,2080515,6188,0,0,2204969,2540,0,0,2011521,5484,0,0,2038214,3802,0,0,2057846,6120,0,0,2188834,3964,0,0,2027001,3383,0,0,1951352,4886,0,0,1980478,5245,0,0,2139220,2483,0,0,1951930,1638,0,0,1757386,4098,0,0,1994334,4640,0,0,2046564,5457,0,0,2072723,5415,0,0,2087828,3760,0,0,1964796,5619,0,0,2176379,4009,0,0,2014267,3014,0,0,1971646,5768,0,0,2094089,7323,0,0,2265486,3095,0,0,1937313,3916,0,0,2003354,5743,0,0,2105191,64,0x7f947ef90e80,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,0,46963,0,0,64,0x7f04d97fae80,185690,0,0,65536,64048,48,1440,32768,2097152.0,2097152.0,1048576.0,1048576.0,0.0,0.0,0.0,16384.0,12216,28600,9466,588,0,46066,262676.0,0.0,188.0,262488.0,64,0x7fa021208e80,0,0,192,0,65536,64426,48,1488,31188,0.0,0.0,0.0,32768.0,0.0,0.0,0.0,32768.0,4096,16384,512,46763,1702,0,48.0,294.0,0.0,262288.0,64,0x7f0a57764e80,3065523,360448,163840,0,0,180224,114688,0,60135592.0,169786350.0,65689398.0,131072.0,0.0,731236.0,0,0,26752,95968.0,0.0,0.0,95968.0,64,0x7f1eb01bee80,0,3470274,4096,4096,0,2444985,4096,4096,0,4308279,4096,4096,0,4136335,4096,4096,0,3158928,4096,4096,0,2797634,4096,4096,0,2905250,4096,4096,0,2598975,4096,4096,0,2812077,4096,4096,0,2632160,4096,4096,0,3011451,4096,4096,0,3779904,4096,4096,0,4673131,4096,4096,0,3602062,4096,4096,0,2948938,4096,4096,0,3354396,4096,4096,0,3635035,4096,4096,0,5510591,4096,4096,0,2509949,4096,4096,0,3356820,4096,4096,0,2724107,4096,4096,0,2514690,4096,4096,0,3254665,4096,4096,0,3294102,4096,4096,0,2338345,4096,4096,0,2570120,4096,4096,0,4762167,4096,4096,0,2430399,4096,4096,0,2849988,4096,4096,0,2598496,4096,4096,0,3123416,4096,4096,0,2442105,4096,4096,64,0x7ff65c1dce80,0,8192,4096,8192,0,8192,4096,8192,141,8195,4240,8336,0,8240,4144,8240,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8360,4264,8360,47,8193,4144,8240,0,8192,4096,8192,0,8192,4096,8192,0,8250,4154,8250,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,64,0x7f0c82278e80,380160,229905,3356941,16384,23833009,144,48,0,47519,47519,3801049.0,2981796.0,7064.0,1235445.0,2014864.0,0.0,2972634.0,2660465.0,378519,239852,47519,0,47519,0,1520608.0,955123.0,0.0,0.0,64,0x7f348ea8ce80,32768,0,0,0,16384,16384,393216,21897956,960.0,513939.0,0.0,524288.0,1162699.0,32768.0,0,0,0,16558,131072.0,131072.0,0.0,131072.0,64,0x7f5614bfce80,4096,0,0,0,4096,0,90,0,4099,0,0,0,4104,0,464,0,4096,0,162,0,4096,0,0,0,4096,0,396,0,4096,0,802,0,4096,0,380,0,4096,0,0,0,4096,0,27,0,4144,0,166,0,4096,0,131,0,4096,0,0,0,4096,0,1871,0,4336,0,2310,0,4096,0,353,0,4096,0,49,0,4096,0,1999,0,4096,0,778,0,4096,0,1227,0,4096,0,0,0,4096,0,1138,0,4096,0,861,0,4096,0,251,0,4144,0,0,0,4096,0,173,0,4096,0,104,0,4097,0,165,0,4096,0,129,0,4096,0,82,0,4096,0,39,0,64,0x7f62a4cdee80,32768,0,16384,16384,32768,49152,0,65536,0.0,0.0,120.0,524288.0,0.0,0.0,0,0,913,46331,0,131587.0,131072.0,0.0,131104.0,64,0x7f13c2ec8e80,0,0,0,16384,0,0,0,0,0.0,0.0,0.0,0.0,16384.0,0.0,0,81920,0.0,0.0,34824.0,126032.0,4881310843226,4881310867386
|
||||
@@ -0,0 +1,2 @@
|
||||
workload_name,command,host_name,host_cpu,sbios,host_distro,host_kernel,host_rocmver,date,gpu_soc,vbios,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,totalL2Banks,LDSBanks,name,numSQC,numPipes,hbmBW,compute_partition,memory_partition,ip_blocks
|
||||
dispatch_0,./tests/vcopy -n 1048576 -b 256 -i 3,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,5.7.1-98,Mon Feb 19 12:59:52 2024 (CST),gfx908,113-D3431401-100,8,120,4,64,40,1024,16,8192,1502,1200,1502,1200,32,32,32,MI100,30,4,1200,,,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
|
||||
|
@@ -0,0 +1,2 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
|
||||
0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,104067,104067,1048576,256,0,0,8,8,16,64,0x0,0x7fb012a3ce80,4881310814096,4881310843226,4881310867386,4881310880141
|
||||
|
@@ -0,0 +1,3 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
|
||||
0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,106306,106306,1048576,256,0,0,8,8,16,64,0x0,0x7f07ca94ee80,47170,47170,16384,65536,14343,1843816,4893155122265,4896137259986,4896137284466,4893162800916
|
||||
1,"vecCopy(double*, double*, double*, int, int) ",2,0,2,106306,106306,1048576,256,0,0,8,8,16,64,0x0,0x7f07ca94ee80,41313,41313,16384,65536,8217,1048584,4893162823870,4896137389586,4896137408466,4893163144176
|
||||
|
@@ -0,0 +1,3 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
|
||||
0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,108543,108543,1048576,256,0,0,8,8,16,64,0x0,0x7ffb9d048e80,0,0,0,4903924355712,4896137259986,4896137284466,4903931980111
|
||||
1,"vecCopy(double*, double*, double*, int, int) ",2,0,2,108543,108543,1048576,256,0,0,8,8,16,64,0x0,0x7ffb9d048e80,0,0,0,4903931998325,4896137389586,4896137408466,4903932324242
|
||||
|
@@ -0,0 +1,3 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
|
||||
0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,105885,105885,1048576,256,0,0,8,8,16,64,0x0,0x7f06d787ae80,65536,221164,28292080,4891310211821,4896137259986,4896137284466,4891317996641
|
||||
1,"vecCopy(double*, double*, double*, int, int) ",2,0,2,105885,105885,1048576,256,0,0,8,8,16,64,0x0,0x7f06d787ae80,65536,172286,22054296,4891318015607,4896137389586,4896137408466,4891318319862
|
||||
|
@@ -0,0 +1,3 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
|
||||
0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,107122,107122,1048576,256,0,0,8,8,16,64,0x0,0x7f8c2ec5ce80,32768,652466,83517588,4897035318717,4896137259986,4896137284466,4897042979986
|
||||
1,"vecCopy(double*, double*, double*, int, int) ",2,0,2,107122,107122,1048576,256,0,0,8,8,16,64,0x0,0x7f8c2ec5ce80,32768,666290,85282176,4897042999433,4896137389586,4896137408466,4897043314900
|
||||
|
@@ -0,0 +1,3 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
|
||||
0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,105274,105274,1048576,256,0,0,8,8,16,64,0x0,0x7f5a39766e80,48042,48042,17103,384344,16384,24957228,232500,0,100356280,4888569436024,4896137259986,4896137284466,4888577137587
|
||||
1,"vecCopy(double*, double*, double*, int, int) ",2,0,2,105274,105274,1048576,256,0,0,8,8,16,64,0x0,0x7f5a39766e80,41327,41327,12734,330624,16384,23699957,225369,0,95346784,4888577166532,4896137389586,4896137408466,4888577502207
|
||||
|
@@ -0,0 +1,5 @@
|
||||
pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_WAVES SQ_IFETCH SQ_IFETCH_LEVEL SQ_ACCUM_PREV_HIRES
|
||||
|
||||
gpu:
|
||||
range: 0:2
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQ_INSTS_LDS SQ_INST_LEVEL_LDS SQ_ACCUM_PREV_HIRES
|
||||
|
||||
gpu:
|
||||
range: 0:2
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQ_INSTS_SMEM SQ_INST_LEVEL_SMEM SQ_ACCUM_PREV_HIRES
|
||||
|
||||
gpu:
|
||||
range: 0:2
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQ_INSTS_VMEM SQ_INST_LEVEL_VMEM SQ_ACCUM_PREV_HIRES
|
||||
|
||||
gpu:
|
||||
range: 0:2
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: GRBM_COUNT GRBM_GUI_ACTIVE CPC_ME1_BUSY_FOR_PACKET_DECODE SQ_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQ_BUSY_CYCLES SQ_LEVEL_WAVES SQ_ACCUM_PREV_HIRES
|
||||
|
||||
gpu:
|
||||
range: 0:2
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQ_CYCLES SQ_BUSY_CYCLES SQ_BUSY_CU_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQC_TC_INST_REQ SQC_TC_DATA_READ_REQ SQC_TC_DATA_WRITE_REQ GRBM_COUNT GRBM_GUI_ACTIVE TCP_GATE_EN1_sum TCP_GATE_EN2_sum TCP_TD_TCP_STALL_CYCLES_sum TCP_TCR_TCP_STALL_CYCLES_sum TA_TA_BUSY_sum TA_BUFFER_WAVEFRONTS_sum TD_TD_BUSY_sum TD_TC_STALL_sum SPI_CSN_WINDOW_VALID SPI_CSN_BUSY CPC_CPC_STAT_BUSY CPC_CPC_STAT_IDLE CPF_CPF_STAT_BUSY CPF_CPF_STAT_STALL TCC_CYCLE_sum TCC_BUSY_sum TCC_PROBE_sum TCC_PROBE_ALL_sum
|
||||
|
||||
gpu:
|
||||
range: 0:2
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQC_TC_DATA_ATOMIC_REQ SQC_TC_STALL SQC_TC_REQ SQC_DCACHE_REQ_READ_16 SQC_ICACHE_REQ SQC_ICACHE_HITS SQC_ICACHE_MISSES SQC_ICACHE_MISSES_DUPLICATE GRBM_SPI_BUSY TCP_READ_TAGCONFLICT_STALL_CYCLES_sum TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum TCP_TA_TCP_STATE_READ_sum TA_BUFFER_READ_WAVEFRONTS_sum TA_BUFFER_WRITE_WAVEFRONTS_sum TD_COALESCABLE_WAVEFRONT_sum TD_LOAD_WAVEFRONT_sum SPI_CSN_NUM_THREADGROUPS SPI_CSN_WAVE CPC_CPC_TCIU_BUSY CPC_CPC_TCIU_IDLE CPF_CPF_TCIU_BUSY CPF_CPF_TCIU_STALL TCC_NC_REQ_sum TCC_UC_REQ_sum TCC_CC_REQ_sum TCC_RW_REQ_sum
|
||||
|
||||
gpu:
|
||||
range: 0:2
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: TCC_EA_ATOMIC_LEVEL_sum
|
||||
|
||||
gpu:
|
||||
range: 0:2
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: TCC_ATOMIC[0] TCC_CYCLE[0] TCC_EA_ATOMIC[0] TCC_EA_ATOMIC_LEVEL[0] TCC_ATOMIC[1] TCC_CYCLE[1] TCC_EA_ATOMIC[1] TCC_EA_ATOMIC_LEVEL[1] TCC_ATOMIC[2] TCC_CYCLE[2] TCC_EA_ATOMIC[2] TCC_EA_ATOMIC_LEVEL[2] TCC_ATOMIC[3] TCC_CYCLE[3] TCC_EA_ATOMIC[3] TCC_EA_ATOMIC_LEVEL[3] TCC_ATOMIC[4] TCC_CYCLE[4] TCC_EA_ATOMIC[4] TCC_EA_ATOMIC_LEVEL[4] TCC_ATOMIC[5] TCC_CYCLE[5] TCC_EA_ATOMIC[5] TCC_EA_ATOMIC_LEVEL[5] TCC_ATOMIC[6] TCC_CYCLE[6] TCC_EA_ATOMIC[6] TCC_EA_ATOMIC_LEVEL[6] TCC_ATOMIC[7] TCC_CYCLE[7] TCC_EA_ATOMIC[7] TCC_EA_ATOMIC_LEVEL[7] TCC_ATOMIC[8] TCC_CYCLE[8] TCC_EA_ATOMIC[8] TCC_EA_ATOMIC_LEVEL[8] TCC_ATOMIC[9] TCC_CYCLE[9] TCC_EA_ATOMIC[9] TCC_EA_ATOMIC_LEVEL[9] TCC_ATOMIC[10] TCC_CYCLE[10] TCC_EA_ATOMIC[10] TCC_EA_ATOMIC_LEVEL[10] TCC_ATOMIC[11] TCC_CYCLE[11] TCC_EA_ATOMIC[11] TCC_EA_ATOMIC_LEVEL[11] TCC_ATOMIC[12] TCC_CYCLE[12] TCC_EA_ATOMIC[12] TCC_EA_ATOMIC_LEVEL[12] TCC_ATOMIC[13] TCC_CYCLE[13] TCC_EA_ATOMIC[13] TCC_EA_ATOMIC_LEVEL[13] TCC_ATOMIC[14] TCC_CYCLE[14] TCC_EA_ATOMIC[14] TCC_EA_ATOMIC_LEVEL[14] TCC_ATOMIC[15] TCC_CYCLE[15] TCC_EA_ATOMIC[15] TCC_EA_ATOMIC_LEVEL[15] TCC_ATOMIC[16] TCC_CYCLE[16] TCC_EA_ATOMIC[16] TCC_EA_ATOMIC_LEVEL[16] TCC_ATOMIC[17] TCC_CYCLE[17] TCC_EA_ATOMIC[17] TCC_EA_ATOMIC_LEVEL[17] TCC_ATOMIC[18] TCC_CYCLE[18] TCC_EA_ATOMIC[18] TCC_EA_ATOMIC_LEVEL[18] TCC_ATOMIC[19] TCC_CYCLE[19] TCC_EA_ATOMIC[19] TCC_EA_ATOMIC_LEVEL[19] TCC_ATOMIC[20] TCC_CYCLE[20] TCC_EA_ATOMIC[20] TCC_EA_ATOMIC_LEVEL[20] TCC_ATOMIC[21] TCC_CYCLE[21] TCC_EA_ATOMIC[21] TCC_EA_ATOMIC_LEVEL[21] TCC_ATOMIC[22] TCC_CYCLE[22] TCC_EA_ATOMIC[22] TCC_EA_ATOMIC_LEVEL[22] TCC_ATOMIC[23] TCC_CYCLE[23] TCC_EA_ATOMIC[23] TCC_EA_ATOMIC_LEVEL[23] TCC_ATOMIC[24] TCC_CYCLE[24] TCC_EA_ATOMIC[24] TCC_EA_ATOMIC_LEVEL[24] TCC_ATOMIC[25] TCC_CYCLE[25] TCC_EA_ATOMIC[25] TCC_EA_ATOMIC_LEVEL[25] TCC_ATOMIC[26] TCC_CYCLE[26] TCC_EA_ATOMIC[26] TCC_EA_ATOMIC_LEVEL[26] TCC_ATOMIC[27] TCC_CYCLE[27] TCC_EA_ATOMIC[27] TCC_EA_ATOMIC_LEVEL[27] TCC_ATOMIC[28] TCC_CYCLE[28] TCC_EA_ATOMIC[28] TCC_EA_ATOMIC_LEVEL[28] TCC_ATOMIC[29] TCC_CYCLE[29] TCC_EA_ATOMIC[29] TCC_EA_ATOMIC_LEVEL[29] TCC_ATOMIC[30] TCC_CYCLE[30] TCC_EA_ATOMIC[30] TCC_EA_ATOMIC_LEVEL[30] TCC_ATOMIC[31] TCC_CYCLE[31] TCC_EA_ATOMIC[31] TCC_EA_ATOMIC_LEVEL[31]
|
||||
|
||||
gpu:
|
||||
range: 0:2
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: TCC_EA_RDREQ[0] TCC_EA_RDREQ_32B[0] TCC_EA_RDREQ_DRAM_CREDIT_STALL[0] TCC_EA_RDREQ_GMI_CREDIT_STALL[0] TCC_EA_RDREQ[1] TCC_EA_RDREQ_32B[1] TCC_EA_RDREQ_DRAM_CREDIT_STALL[1] TCC_EA_RDREQ_GMI_CREDIT_STALL[1] TCC_EA_RDREQ[2] TCC_EA_RDREQ_32B[2] TCC_EA_RDREQ_DRAM_CREDIT_STALL[2] TCC_EA_RDREQ_GMI_CREDIT_STALL[2] TCC_EA_RDREQ[3] TCC_EA_RDREQ_32B[3] TCC_EA_RDREQ_DRAM_CREDIT_STALL[3] TCC_EA_RDREQ_GMI_CREDIT_STALL[3] TCC_EA_RDREQ[4] TCC_EA_RDREQ_32B[4] TCC_EA_RDREQ_DRAM_CREDIT_STALL[4] TCC_EA_RDREQ_GMI_CREDIT_STALL[4] TCC_EA_RDREQ[5] TCC_EA_RDREQ_32B[5] TCC_EA_RDREQ_DRAM_CREDIT_STALL[5] TCC_EA_RDREQ_GMI_CREDIT_STALL[5] TCC_EA_RDREQ[6] TCC_EA_RDREQ_32B[6] TCC_EA_RDREQ_DRAM_CREDIT_STALL[6] TCC_EA_RDREQ_GMI_CREDIT_STALL[6] TCC_EA_RDREQ[7] TCC_EA_RDREQ_32B[7] TCC_EA_RDREQ_DRAM_CREDIT_STALL[7] TCC_EA_RDREQ_GMI_CREDIT_STALL[7] TCC_EA_RDREQ[8] TCC_EA_RDREQ_32B[8] TCC_EA_RDREQ_DRAM_CREDIT_STALL[8] TCC_EA_RDREQ_GMI_CREDIT_STALL[8] TCC_EA_RDREQ[9] TCC_EA_RDREQ_32B[9] TCC_EA_RDREQ_DRAM_CREDIT_STALL[9] TCC_EA_RDREQ_GMI_CREDIT_STALL[9] TCC_EA_RDREQ[10] TCC_EA_RDREQ_32B[10] TCC_EA_RDREQ_DRAM_CREDIT_STALL[10] TCC_EA_RDREQ_GMI_CREDIT_STALL[10] TCC_EA_RDREQ[11] TCC_EA_RDREQ_32B[11] TCC_EA_RDREQ_DRAM_CREDIT_STALL[11] TCC_EA_RDREQ_GMI_CREDIT_STALL[11] TCC_EA_RDREQ[12] TCC_EA_RDREQ_32B[12] TCC_EA_RDREQ_DRAM_CREDIT_STALL[12] TCC_EA_RDREQ_GMI_CREDIT_STALL[12] TCC_EA_RDREQ[13] TCC_EA_RDREQ_32B[13] TCC_EA_RDREQ_DRAM_CREDIT_STALL[13] TCC_EA_RDREQ_GMI_CREDIT_STALL[13] TCC_EA_RDREQ[14] TCC_EA_RDREQ_32B[14] TCC_EA_RDREQ_DRAM_CREDIT_STALL[14] TCC_EA_RDREQ_GMI_CREDIT_STALL[14] TCC_EA_RDREQ[15] TCC_EA_RDREQ_32B[15] TCC_EA_RDREQ_DRAM_CREDIT_STALL[15] TCC_EA_RDREQ_GMI_CREDIT_STALL[15] TCC_EA_RDREQ[16] TCC_EA_RDREQ_32B[16] TCC_EA_RDREQ_DRAM_CREDIT_STALL[16] TCC_EA_RDREQ_GMI_CREDIT_STALL[16] TCC_EA_RDREQ[17] TCC_EA_RDREQ_32B[17] TCC_EA_RDREQ_DRAM_CREDIT_STALL[17] TCC_EA_RDREQ_GMI_CREDIT_STALL[17] TCC_EA_RDREQ[18] TCC_EA_RDREQ_32B[18] TCC_EA_RDREQ_DRAM_CREDIT_STALL[18] TCC_EA_RDREQ_GMI_CREDIT_STALL[18] TCC_EA_RDREQ[19] TCC_EA_RDREQ_32B[19] TCC_EA_RDREQ_DRAM_CREDIT_STALL[19] TCC_EA_RDREQ_GMI_CREDIT_STALL[19] TCC_EA_RDREQ[20] TCC_EA_RDREQ_32B[20] TCC_EA_RDREQ_DRAM_CREDIT_STALL[20] TCC_EA_RDREQ_GMI_CREDIT_STALL[20] TCC_EA_RDREQ[21] TCC_EA_RDREQ_32B[21] TCC_EA_RDREQ_DRAM_CREDIT_STALL[21] TCC_EA_RDREQ_GMI_CREDIT_STALL[21] TCC_EA_RDREQ[22] TCC_EA_RDREQ_32B[22] TCC_EA_RDREQ_DRAM_CREDIT_STALL[22] TCC_EA_RDREQ_GMI_CREDIT_STALL[22] TCC_EA_RDREQ[23] TCC_EA_RDREQ_32B[23] TCC_EA_RDREQ_DRAM_CREDIT_STALL[23] TCC_EA_RDREQ_GMI_CREDIT_STALL[23] TCC_EA_RDREQ[24] TCC_EA_RDREQ_32B[24] TCC_EA_RDREQ_DRAM_CREDIT_STALL[24] TCC_EA_RDREQ_GMI_CREDIT_STALL[24] TCC_EA_RDREQ[25] TCC_EA_RDREQ_32B[25] TCC_EA_RDREQ_DRAM_CREDIT_STALL[25] TCC_EA_RDREQ_GMI_CREDIT_STALL[25] TCC_EA_RDREQ[26] TCC_EA_RDREQ_32B[26] TCC_EA_RDREQ_DRAM_CREDIT_STALL[26] TCC_EA_RDREQ_GMI_CREDIT_STALL[26] TCC_EA_RDREQ[27] TCC_EA_RDREQ_32B[27] TCC_EA_RDREQ_DRAM_CREDIT_STALL[27] TCC_EA_RDREQ_GMI_CREDIT_STALL[27] TCC_EA_RDREQ[28] TCC_EA_RDREQ_32B[28] TCC_EA_RDREQ_DRAM_CREDIT_STALL[28] TCC_EA_RDREQ_GMI_CREDIT_STALL[28] TCC_EA_RDREQ[29] TCC_EA_RDREQ_32B[29] TCC_EA_RDREQ_DRAM_CREDIT_STALL[29] TCC_EA_RDREQ_GMI_CREDIT_STALL[29] TCC_EA_RDREQ[30] TCC_EA_RDREQ_32B[30] TCC_EA_RDREQ_DRAM_CREDIT_STALL[30] TCC_EA_RDREQ_GMI_CREDIT_STALL[30] TCC_EA_RDREQ[31] TCC_EA_RDREQ_32B[31] TCC_EA_RDREQ_DRAM_CREDIT_STALL[31] TCC_EA_RDREQ_GMI_CREDIT_STALL[31]
|
||||
|
||||
gpu:
|
||||
range: 0:2
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: TCC_EA_RDREQ_IO_CREDIT_STALL[0] TCC_EA_RDREQ_LEVEL[0] TCC_EA_WRREQ[0] TCC_EA_WRREQ_64B[0] TCC_EA_RDREQ_IO_CREDIT_STALL[1] TCC_EA_RDREQ_LEVEL[1] TCC_EA_WRREQ[1] TCC_EA_WRREQ_64B[1] TCC_EA_RDREQ_IO_CREDIT_STALL[2] TCC_EA_RDREQ_LEVEL[2] TCC_EA_WRREQ[2] TCC_EA_WRREQ_64B[2] TCC_EA_RDREQ_IO_CREDIT_STALL[3] TCC_EA_RDREQ_LEVEL[3] TCC_EA_WRREQ[3] TCC_EA_WRREQ_64B[3] TCC_EA_RDREQ_IO_CREDIT_STALL[4] TCC_EA_RDREQ_LEVEL[4] TCC_EA_WRREQ[4] TCC_EA_WRREQ_64B[4] TCC_EA_RDREQ_IO_CREDIT_STALL[5] TCC_EA_RDREQ_LEVEL[5] TCC_EA_WRREQ[5] TCC_EA_WRREQ_64B[5] TCC_EA_RDREQ_IO_CREDIT_STALL[6] TCC_EA_RDREQ_LEVEL[6] TCC_EA_WRREQ[6] TCC_EA_WRREQ_64B[6] TCC_EA_RDREQ_IO_CREDIT_STALL[7] TCC_EA_RDREQ_LEVEL[7] TCC_EA_WRREQ[7] TCC_EA_WRREQ_64B[7] TCC_EA_RDREQ_IO_CREDIT_STALL[8] TCC_EA_RDREQ_LEVEL[8] TCC_EA_WRREQ[8] TCC_EA_WRREQ_64B[8] TCC_EA_RDREQ_IO_CREDIT_STALL[9] TCC_EA_RDREQ_LEVEL[9] TCC_EA_WRREQ[9] TCC_EA_WRREQ_64B[9] TCC_EA_RDREQ_IO_CREDIT_STALL[10] TCC_EA_RDREQ_LEVEL[10] TCC_EA_WRREQ[10] TCC_EA_WRREQ_64B[10] TCC_EA_RDREQ_IO_CREDIT_STALL[11] TCC_EA_RDREQ_LEVEL[11] TCC_EA_WRREQ[11] TCC_EA_WRREQ_64B[11] TCC_EA_RDREQ_IO_CREDIT_STALL[12] TCC_EA_RDREQ_LEVEL[12] TCC_EA_WRREQ[12] TCC_EA_WRREQ_64B[12] TCC_EA_RDREQ_IO_CREDIT_STALL[13] TCC_EA_RDREQ_LEVEL[13] TCC_EA_WRREQ[13] TCC_EA_WRREQ_64B[13] TCC_EA_RDREQ_IO_CREDIT_STALL[14] TCC_EA_RDREQ_LEVEL[14] TCC_EA_WRREQ[14] TCC_EA_WRREQ_64B[14] TCC_EA_RDREQ_IO_CREDIT_STALL[15] TCC_EA_RDREQ_LEVEL[15] TCC_EA_WRREQ[15] TCC_EA_WRREQ_64B[15] TCC_EA_RDREQ_IO_CREDIT_STALL[16] TCC_EA_RDREQ_LEVEL[16] TCC_EA_WRREQ[16] TCC_EA_WRREQ_64B[16] TCC_EA_RDREQ_IO_CREDIT_STALL[17] TCC_EA_RDREQ_LEVEL[17] TCC_EA_WRREQ[17] TCC_EA_WRREQ_64B[17] TCC_EA_RDREQ_IO_CREDIT_STALL[18] TCC_EA_RDREQ_LEVEL[18] TCC_EA_WRREQ[18] TCC_EA_WRREQ_64B[18] TCC_EA_RDREQ_IO_CREDIT_STALL[19] TCC_EA_RDREQ_LEVEL[19] TCC_EA_WRREQ[19] TCC_EA_WRREQ_64B[19] TCC_EA_RDREQ_IO_CREDIT_STALL[20] TCC_EA_RDREQ_LEVEL[20] TCC_EA_WRREQ[20] TCC_EA_WRREQ_64B[20] TCC_EA_RDREQ_IO_CREDIT_STALL[21] TCC_EA_RDREQ_LEVEL[21] TCC_EA_WRREQ[21] TCC_EA_WRREQ_64B[21] TCC_EA_RDREQ_IO_CREDIT_STALL[22] TCC_EA_RDREQ_LEVEL[22] TCC_EA_WRREQ[22] TCC_EA_WRREQ_64B[22] TCC_EA_RDREQ_IO_CREDIT_STALL[23] TCC_EA_RDREQ_LEVEL[23] TCC_EA_WRREQ[23] TCC_EA_WRREQ_64B[23] TCC_EA_RDREQ_IO_CREDIT_STALL[24] TCC_EA_RDREQ_LEVEL[24] TCC_EA_WRREQ[24] TCC_EA_WRREQ_64B[24] TCC_EA_RDREQ_IO_CREDIT_STALL[25] TCC_EA_RDREQ_LEVEL[25] TCC_EA_WRREQ[25] TCC_EA_WRREQ_64B[25] TCC_EA_RDREQ_IO_CREDIT_STALL[26] TCC_EA_RDREQ_LEVEL[26] TCC_EA_WRREQ[26] TCC_EA_WRREQ_64B[26] TCC_EA_RDREQ_IO_CREDIT_STALL[27] TCC_EA_RDREQ_LEVEL[27] TCC_EA_WRREQ[27] TCC_EA_WRREQ_64B[27] TCC_EA_RDREQ_IO_CREDIT_STALL[28] TCC_EA_RDREQ_LEVEL[28] TCC_EA_WRREQ[28] TCC_EA_WRREQ_64B[28] TCC_EA_RDREQ_IO_CREDIT_STALL[29] TCC_EA_RDREQ_LEVEL[29] TCC_EA_WRREQ[29] TCC_EA_WRREQ_64B[29] TCC_EA_RDREQ_IO_CREDIT_STALL[30] TCC_EA_RDREQ_LEVEL[30] TCC_EA_WRREQ[30] TCC_EA_WRREQ_64B[30] TCC_EA_RDREQ_IO_CREDIT_STALL[31] TCC_EA_RDREQ_LEVEL[31] TCC_EA_WRREQ[31] TCC_EA_WRREQ_64B[31]
|
||||
|
||||
gpu:
|
||||
range: 0:2
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: TCC_EA_WRREQ_DRAM_CREDIT_STALL[0] TCC_EA_WRREQ_GMI_CREDIT_STALL[0] TCC_EA_WRREQ_IO_CREDIT_STALL[0] TCC_EA_WRREQ_LEVEL[0] TCC_EA_WRREQ_DRAM_CREDIT_STALL[1] TCC_EA_WRREQ_GMI_CREDIT_STALL[1] TCC_EA_WRREQ_IO_CREDIT_STALL[1] TCC_EA_WRREQ_LEVEL[1] TCC_EA_WRREQ_DRAM_CREDIT_STALL[2] TCC_EA_WRREQ_GMI_CREDIT_STALL[2] TCC_EA_WRREQ_IO_CREDIT_STALL[2] TCC_EA_WRREQ_LEVEL[2] TCC_EA_WRREQ_DRAM_CREDIT_STALL[3] TCC_EA_WRREQ_GMI_CREDIT_STALL[3] TCC_EA_WRREQ_IO_CREDIT_STALL[3] TCC_EA_WRREQ_LEVEL[3] TCC_EA_WRREQ_DRAM_CREDIT_STALL[4] TCC_EA_WRREQ_GMI_CREDIT_STALL[4] TCC_EA_WRREQ_IO_CREDIT_STALL[4] TCC_EA_WRREQ_LEVEL[4] TCC_EA_WRREQ_DRAM_CREDIT_STALL[5] TCC_EA_WRREQ_GMI_CREDIT_STALL[5] TCC_EA_WRREQ_IO_CREDIT_STALL[5] TCC_EA_WRREQ_LEVEL[5] TCC_EA_WRREQ_DRAM_CREDIT_STALL[6] TCC_EA_WRREQ_GMI_CREDIT_STALL[6] TCC_EA_WRREQ_IO_CREDIT_STALL[6] TCC_EA_WRREQ_LEVEL[6] TCC_EA_WRREQ_DRAM_CREDIT_STALL[7] TCC_EA_WRREQ_GMI_CREDIT_STALL[7] TCC_EA_WRREQ_IO_CREDIT_STALL[7] TCC_EA_WRREQ_LEVEL[7] TCC_EA_WRREQ_DRAM_CREDIT_STALL[8] TCC_EA_WRREQ_GMI_CREDIT_STALL[8] TCC_EA_WRREQ_IO_CREDIT_STALL[8] TCC_EA_WRREQ_LEVEL[8] TCC_EA_WRREQ_DRAM_CREDIT_STALL[9] TCC_EA_WRREQ_GMI_CREDIT_STALL[9] TCC_EA_WRREQ_IO_CREDIT_STALL[9] TCC_EA_WRREQ_LEVEL[9] TCC_EA_WRREQ_DRAM_CREDIT_STALL[10] TCC_EA_WRREQ_GMI_CREDIT_STALL[10] TCC_EA_WRREQ_IO_CREDIT_STALL[10] TCC_EA_WRREQ_LEVEL[10] TCC_EA_WRREQ_DRAM_CREDIT_STALL[11] TCC_EA_WRREQ_GMI_CREDIT_STALL[11] TCC_EA_WRREQ_IO_CREDIT_STALL[11] TCC_EA_WRREQ_LEVEL[11] TCC_EA_WRREQ_DRAM_CREDIT_STALL[12] TCC_EA_WRREQ_GMI_CREDIT_STALL[12] TCC_EA_WRREQ_IO_CREDIT_STALL[12] TCC_EA_WRREQ_LEVEL[12] TCC_EA_WRREQ_DRAM_CREDIT_STALL[13] TCC_EA_WRREQ_GMI_CREDIT_STALL[13] TCC_EA_WRREQ_IO_CREDIT_STALL[13] TCC_EA_WRREQ_LEVEL[13] TCC_EA_WRREQ_DRAM_CREDIT_STALL[14] TCC_EA_WRREQ_GMI_CREDIT_STALL[14] TCC_EA_WRREQ_IO_CREDIT_STALL[14] TCC_EA_WRREQ_LEVEL[14] TCC_EA_WRREQ_DRAM_CREDIT_STALL[15] TCC_EA_WRREQ_GMI_CREDIT_STALL[15] TCC_EA_WRREQ_IO_CREDIT_STALL[15] TCC_EA_WRREQ_LEVEL[15] TCC_EA_WRREQ_DRAM_CREDIT_STALL[16] TCC_EA_WRREQ_GMI_CREDIT_STALL[16] TCC_EA_WRREQ_IO_CREDIT_STALL[16] TCC_EA_WRREQ_LEVEL[16] TCC_EA_WRREQ_DRAM_CREDIT_STALL[17] TCC_EA_WRREQ_GMI_CREDIT_STALL[17] TCC_EA_WRREQ_IO_CREDIT_STALL[17] TCC_EA_WRREQ_LEVEL[17] TCC_EA_WRREQ_DRAM_CREDIT_STALL[18] TCC_EA_WRREQ_GMI_CREDIT_STALL[18] TCC_EA_WRREQ_IO_CREDIT_STALL[18] TCC_EA_WRREQ_LEVEL[18] TCC_EA_WRREQ_DRAM_CREDIT_STALL[19] TCC_EA_WRREQ_GMI_CREDIT_STALL[19] TCC_EA_WRREQ_IO_CREDIT_STALL[19] TCC_EA_WRREQ_LEVEL[19] TCC_EA_WRREQ_DRAM_CREDIT_STALL[20] TCC_EA_WRREQ_GMI_CREDIT_STALL[20] TCC_EA_WRREQ_IO_CREDIT_STALL[20] TCC_EA_WRREQ_LEVEL[20] TCC_EA_WRREQ_DRAM_CREDIT_STALL[21] TCC_EA_WRREQ_GMI_CREDIT_STALL[21] TCC_EA_WRREQ_IO_CREDIT_STALL[21] TCC_EA_WRREQ_LEVEL[21] TCC_EA_WRREQ_DRAM_CREDIT_STALL[22] TCC_EA_WRREQ_GMI_CREDIT_STALL[22] TCC_EA_WRREQ_IO_CREDIT_STALL[22] TCC_EA_WRREQ_LEVEL[22] TCC_EA_WRREQ_DRAM_CREDIT_STALL[23] TCC_EA_WRREQ_GMI_CREDIT_STALL[23] TCC_EA_WRREQ_IO_CREDIT_STALL[23] TCC_EA_WRREQ_LEVEL[23] TCC_EA_WRREQ_DRAM_CREDIT_STALL[24] TCC_EA_WRREQ_GMI_CREDIT_STALL[24] TCC_EA_WRREQ_IO_CREDIT_STALL[24] TCC_EA_WRREQ_LEVEL[24] TCC_EA_WRREQ_DRAM_CREDIT_STALL[25] TCC_EA_WRREQ_GMI_CREDIT_STALL[25] TCC_EA_WRREQ_IO_CREDIT_STALL[25] TCC_EA_WRREQ_LEVEL[25] TCC_EA_WRREQ_DRAM_CREDIT_STALL[26] TCC_EA_WRREQ_GMI_CREDIT_STALL[26] TCC_EA_WRREQ_IO_CREDIT_STALL[26] TCC_EA_WRREQ_LEVEL[26] TCC_EA_WRREQ_DRAM_CREDIT_STALL[27] TCC_EA_WRREQ_GMI_CREDIT_STALL[27] TCC_EA_WRREQ_IO_CREDIT_STALL[27] TCC_EA_WRREQ_LEVEL[27] TCC_EA_WRREQ_DRAM_CREDIT_STALL[28] TCC_EA_WRREQ_GMI_CREDIT_STALL[28] TCC_EA_WRREQ_IO_CREDIT_STALL[28] TCC_EA_WRREQ_LEVEL[28] TCC_EA_WRREQ_DRAM_CREDIT_STALL[29] TCC_EA_WRREQ_GMI_CREDIT_STALL[29] TCC_EA_WRREQ_IO_CREDIT_STALL[29] TCC_EA_WRREQ_LEVEL[29] TCC_EA_WRREQ_DRAM_CREDIT_STALL[30] TCC_EA_WRREQ_GMI_CREDIT_STALL[30] TCC_EA_WRREQ_IO_CREDIT_STALL[30] TCC_EA_WRREQ_LEVEL[30] TCC_EA_WRREQ_DRAM_CREDIT_STALL[31] TCC_EA_WRREQ_GMI_CREDIT_STALL[31] TCC_EA_WRREQ_IO_CREDIT_STALL[31] TCC_EA_WRREQ_LEVEL[31]
|
||||
|
||||
gpu:
|
||||
range: 0:2
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: TCC_HIT[0] TCC_MISS[0] TCC_READ[0] TCC_REQ[0] TCC_HIT[1] TCC_MISS[1] TCC_READ[1] TCC_REQ[1] TCC_HIT[2] TCC_MISS[2] TCC_READ[2] TCC_REQ[2] TCC_HIT[3] TCC_MISS[3] TCC_READ[3] TCC_REQ[3] TCC_HIT[4] TCC_MISS[4] TCC_READ[4] TCC_REQ[4] TCC_HIT[5] TCC_MISS[5] TCC_READ[5] TCC_REQ[5] TCC_HIT[6] TCC_MISS[6] TCC_READ[6] TCC_REQ[6] TCC_HIT[7] TCC_MISS[7] TCC_READ[7] TCC_REQ[7] TCC_HIT[8] TCC_MISS[8] TCC_READ[8] TCC_REQ[8] TCC_HIT[9] TCC_MISS[9] TCC_READ[9] TCC_REQ[9] TCC_HIT[10] TCC_MISS[10] TCC_READ[10] TCC_REQ[10] TCC_HIT[11] TCC_MISS[11] TCC_READ[11] TCC_REQ[11] TCC_HIT[12] TCC_MISS[12] TCC_READ[12] TCC_REQ[12] TCC_HIT[13] TCC_MISS[13] TCC_READ[13] TCC_REQ[13] TCC_HIT[14] TCC_MISS[14] TCC_READ[14] TCC_REQ[14] TCC_HIT[15] TCC_MISS[15] TCC_READ[15] TCC_REQ[15] TCC_HIT[16] TCC_MISS[16] TCC_READ[16] TCC_REQ[16] TCC_HIT[17] TCC_MISS[17] TCC_READ[17] TCC_REQ[17] TCC_HIT[18] TCC_MISS[18] TCC_READ[18] TCC_REQ[18] TCC_HIT[19] TCC_MISS[19] TCC_READ[19] TCC_REQ[19] TCC_HIT[20] TCC_MISS[20] TCC_READ[20] TCC_REQ[20] TCC_HIT[21] TCC_MISS[21] TCC_READ[21] TCC_REQ[21] TCC_HIT[22] TCC_MISS[22] TCC_READ[22] TCC_REQ[22] TCC_HIT[23] TCC_MISS[23] TCC_READ[23] TCC_REQ[23] TCC_HIT[24] TCC_MISS[24] TCC_READ[24] TCC_REQ[24] TCC_HIT[25] TCC_MISS[25] TCC_READ[25] TCC_REQ[25] TCC_HIT[26] TCC_MISS[26] TCC_READ[26] TCC_REQ[26] TCC_HIT[27] TCC_MISS[27] TCC_READ[27] TCC_REQ[27] TCC_HIT[28] TCC_MISS[28] TCC_READ[28] TCC_REQ[28] TCC_HIT[29] TCC_MISS[29] TCC_READ[29] TCC_REQ[29] TCC_HIT[30] TCC_MISS[30] TCC_READ[30] TCC_REQ[30] TCC_HIT[31] TCC_MISS[31] TCC_READ[31] TCC_REQ[31]
|
||||
|
||||
gpu:
|
||||
range: 0:2
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: TCC_RW_REQ[0] TCC_TOO_MANY_EA_WRREQS_STALL[0] TCC_WRITE[0] TCC_RW_REQ[1] TCC_TOO_MANY_EA_WRREQS_STALL[1] TCC_WRITE[1] TCC_RW_REQ[2] TCC_TOO_MANY_EA_WRREQS_STALL[2] TCC_WRITE[2] TCC_RW_REQ[3] TCC_TOO_MANY_EA_WRREQS_STALL[3] TCC_WRITE[3] TCC_RW_REQ[4] TCC_TOO_MANY_EA_WRREQS_STALL[4] TCC_WRITE[4] TCC_RW_REQ[5] TCC_TOO_MANY_EA_WRREQS_STALL[5] TCC_WRITE[5] TCC_RW_REQ[6] TCC_TOO_MANY_EA_WRREQS_STALL[6] TCC_WRITE[6] TCC_RW_REQ[7] TCC_TOO_MANY_EA_WRREQS_STALL[7] TCC_WRITE[7] TCC_RW_REQ[8] TCC_TOO_MANY_EA_WRREQS_STALL[8] TCC_WRITE[8] TCC_RW_REQ[9] TCC_TOO_MANY_EA_WRREQS_STALL[9] TCC_WRITE[9] TCC_RW_REQ[10] TCC_TOO_MANY_EA_WRREQS_STALL[10] TCC_WRITE[10] TCC_RW_REQ[11] TCC_TOO_MANY_EA_WRREQS_STALL[11] TCC_WRITE[11] TCC_RW_REQ[12] TCC_TOO_MANY_EA_WRREQS_STALL[12] TCC_WRITE[12] TCC_RW_REQ[13] TCC_TOO_MANY_EA_WRREQS_STALL[13] TCC_WRITE[13] TCC_RW_REQ[14] TCC_TOO_MANY_EA_WRREQS_STALL[14] TCC_WRITE[14] TCC_RW_REQ[15] TCC_TOO_MANY_EA_WRREQS_STALL[15] TCC_WRITE[15] TCC_RW_REQ[16] TCC_TOO_MANY_EA_WRREQS_STALL[16] TCC_WRITE[16] TCC_RW_REQ[17] TCC_TOO_MANY_EA_WRREQS_STALL[17] TCC_WRITE[17] TCC_RW_REQ[18] TCC_TOO_MANY_EA_WRREQS_STALL[18] TCC_WRITE[18] TCC_RW_REQ[19] TCC_TOO_MANY_EA_WRREQS_STALL[19] TCC_WRITE[19] TCC_RW_REQ[20] TCC_TOO_MANY_EA_WRREQS_STALL[20] TCC_WRITE[20] TCC_RW_REQ[21] TCC_TOO_MANY_EA_WRREQS_STALL[21] TCC_WRITE[21] TCC_RW_REQ[22] TCC_TOO_MANY_EA_WRREQS_STALL[22] TCC_WRITE[22] TCC_RW_REQ[23] TCC_TOO_MANY_EA_WRREQS_STALL[23] TCC_WRITE[23] TCC_RW_REQ[24] TCC_TOO_MANY_EA_WRREQS_STALL[24] TCC_WRITE[24] TCC_RW_REQ[25] TCC_TOO_MANY_EA_WRREQS_STALL[25] TCC_WRITE[25] TCC_RW_REQ[26] TCC_TOO_MANY_EA_WRREQS_STALL[26] TCC_WRITE[26] TCC_RW_REQ[27] TCC_TOO_MANY_EA_WRREQS_STALL[27] TCC_WRITE[27] TCC_RW_REQ[28] TCC_TOO_MANY_EA_WRREQS_STALL[28] TCC_WRITE[28] TCC_RW_REQ[29] TCC_TOO_MANY_EA_WRREQS_STALL[29] TCC_WRITE[29] TCC_RW_REQ[30] TCC_TOO_MANY_EA_WRREQS_STALL[30] TCC_WRITE[30] TCC_RW_REQ[31] TCC_TOO_MANY_EA_WRREQS_STALL[31] TCC_WRITE[31]
|
||||
|
||||
gpu:
|
||||
range: 0:2
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQC_DCACHE_INPUT_VALID_READYB SQC_DCACHE_ATOMIC SQC_DCACHE_REQ_READ_8 SQC_DCACHE_REQ SQC_DCACHE_HITS SQC_DCACHE_MISSES SQC_DCACHE_MISSES_DUPLICATE SQC_DCACHE_REQ_READ_1 TCP_VOLATILE_sum TCP_TOTAL_ACCESSES_sum TCP_TOTAL_READ_sum TCP_TOTAL_WRITE_sum TA_BUFFER_ATOMIC_WAVEFRONTS_sum TA_BUFFER_TOTAL_CYCLES_sum TD_ATOMIC_WAVEFRONT_sum TD_STORE_WAVEFRONT_sum SPI_RA_REQ_NO_ALLOC SPI_RA_REQ_NO_ALLOC_CSN CPC_CPC_STAT_STALL CPC_UTCL1_STALL_ON_TRANSLATION CPF_CPF_STAT_IDLE CPF_CPF_TCIU_IDLE TCC_REQ_sum TCC_STREAMING_REQ_sum TCC_HIT_sum TCC_MISS_sum
|
||||
|
||||
gpu:
|
||||
range: 0:2
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQC_DCACHE_REQ_READ_2 SQC_DCACHE_REQ_READ_4 SQ_INSTS_VMEM_WR SQ_INSTS_VMEM_RD SQ_INSTS_VMEM SQ_INSTS_SALU SQ_INSTS_VSKIPPED SQ_INSTS_SMEM TCP_TOTAL_ATOMIC_WITH_RET_sum TCP_TOTAL_ATOMIC_WITHOUT_RET_sum TCP_TOTAL_WRITEBACK_INVALIDATES_sum TCP_TOTAL_CACHE_ACCESSES_sum TA_BUFFER_COALESCED_READ_CYCLES_sum TA_BUFFER_COALESCED_WRITE_CYCLES_sum SPI_RA_RES_STALL_CSN SPI_RA_TMP_STALL_CSN CPC_CPC_UTCL2IU_BUSY CPC_CPC_UTCL2IU_IDLE CPF_CMP_UTCL1_STALL_ON_TRANSLATION TCC_READ_sum TCC_WRITE_sum TCC_ATOMIC_sum TCC_WRITEBACK_sum
|
||||
|
||||
gpu:
|
||||
range: 0:2
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQ_INSTS_FLAT SQ_INSTS_LDS SQ_INSTS_GDS SQ_INSTS_EXP_GDS SQ_INSTS_BRANCH SQ_INSTS_SENDMSG SQ_INSTS SQ_WAIT_ANY TCP_UTCL1_TRANSLATION_MISS_sum TCP_UTCL1_TRANSLATION_HIT_sum TCP_UTCL1_PERMISSION_MISS_sum TCP_UTCL1_REQUEST_sum TA_ADDR_STALLED_BY_TC_CYCLES_sum TA_TOTAL_WAVEFRONTS_sum SPI_RA_WAVE_SIMD_FULL_CSN SPI_RA_VGPR_SIMD_FULL_CSN CPC_CPC_UTCL2IU_STALL CPC_ME1_BUSY_FOR_PACKET_DECODE TCC_EA_WRREQ_sum TCC_EA_WRREQ_64B_sum TCC_EA_WR_UNCACHED_32B_sum TCC_EA_WRREQ_DRAM_sum
|
||||
|
||||
gpu:
|
||||
range: 0:2
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQ_WAIT_INST_ANY SQ_ACTIVE_INST_ANY SQ_INSTS_VALU SQ_ACTIVE_INST_VMEM SQ_ACTIVE_INST_LDS SQ_ACTIVE_INST_VALU SQ_ACTIVE_INST_SCA SQ_ACTIVE_INST_EXP_GDS TCP_TCP_LATENCY_sum TCP_TCC_READ_REQ_LATENCY_sum TCP_TCC_WRITE_REQ_LATENCY_sum TCP_TCC_READ_REQ_sum TA_ADDR_STALLED_BY_TD_CYCLES_sum TA_DATA_STALLED_BY_TC_CYCLES_sum SPI_RA_SGPR_SIMD_FULL_CSN SPI_RA_LDS_CU_FULL_CSN CPC_ME1_DC0_SPI_BUSY TCC_EA_WRREQ_STALL_sum TCC_EA_WRREQ_IO_CREDIT_STALL_sum TCC_EA_WRREQ_GMI_CREDIT_STALL_sum TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum
|
||||
|
||||
gpu:
|
||||
range: 0:2
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQ_ACTIVE_INST_MISC SQ_ACTIVE_INST_FLAT SQ_INST_CYCLES_VMEM_WR SQ_INST_CYCLES_VMEM_RD SQ_INST_CYCLES_SMEM SQ_INST_CYCLES_SALU SQ_THREAD_CYCLES_VALU SQ_IFETCH TCP_TCC_WRITE_REQ_sum TCP_TCC_ATOMIC_WITH_RET_REQ_sum TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum TCP_TCC_NC_READ_REQ_sum TA_FLAT_WAVEFRONTS_sum TA_FLAT_READ_WAVEFRONTS_sum SPI_RA_BAR_CU_FULL_CSN SPI_RA_TGLIM_CU_FULL_CSN TCC_EA_RDREQ_sum TCC_EA_RDREQ_32B_sum TCC_EA_RD_UNCACHED_32B_sum TCC_EA_RDREQ_DRAM_sum
|
||||
|
||||
gpu:
|
||||
range: 0:2
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQ_LDS_BANK_CONFLICT SQ_LDS_ADDR_CONFLICT SQ_LDS_UNALIGNED_STALL SQ_WAVES_EQ_64 SQ_WAVES_LT_64 SQ_WAVES_LT_48 SQ_WAVES_LT_32 SQ_WAVES_LT_16 TCP_TCC_NC_WRITE_REQ_sum TCP_TCC_NC_ATOMIC_REQ_sum TCP_TCC_UC_READ_REQ_sum TCP_TCC_UC_WRITE_REQ_sum TA_FLAT_WRITE_WAVEFRONTS_sum TA_FLAT_ATOMIC_WAVEFRONTS_sum SPI_RA_WVLIM_STALL_CSN SPI_SWC_CSC_WR TCC_EA_RDREQ_IO_CREDIT_STALL_sum TCC_EA_RDREQ_GMI_CREDIT_STALL_sum TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum TCC_TAG_STALL_sum
|
||||
|
||||
gpu:
|
||||
range: 0:2
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQ_ITEMS SQ_LDS_MEM_VIOLATIONS SQ_LDS_ATOMIC_RETURN SQ_LDS_IDX_ACTIVE SQ_WAVES_RESTORED SQ_WAVES_SAVED SQ_INSTS_SMEM_NORM TCP_TCC_UC_ATOMIC_REQ_sum TCP_TCC_CC_READ_REQ_sum TCP_TCC_CC_WRITE_REQ_sum TCP_TCC_CC_ATOMIC_REQ_sum SPI_VWC_CSC_WR SPI_RA_BULKY_CU_FULL_CSN TCC_NORMAL_WRITEBACK_sum TCC_ALL_TC_OP_WB_WRITEBACK_sum TCC_NORMAL_EVICT_sum TCC_ALL_TC_OP_INV_EVICT_sum
|
||||
|
||||
gpu:
|
||||
range: 0:2
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: TCP_TCC_RW_READ_REQ_sum TCP_TCC_RW_WRITE_REQ_sum TCP_TCC_RW_ATOMIC_REQ_sum TCP_PENDING_STALL_CYCLES_sum TCC_TOO_MANY_EA_WRREQS_STALL_sum TCC_EA_ATOMIC_sum TCC_EA_RDREQ_LEVEL_sum TCC_EA_WRREQ_LEVEL_sum
|
||||
|
||||
gpu:
|
||||
range: 0:2
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc:
|
||||
|
||||
gpu:
|
||||
range: 0:2
|
||||
kernel:
|
||||
@@ -0,0 +1,3 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,obj,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],wave_size_1,obj_1,TCC_EA_WRREQ_DRAM_CREDIT_STALL[0],TCC_EA_WRREQ_GMI_CREDIT_STALL[0],TCC_EA_WRREQ_IO_CREDIT_STALL[0],TCC_EA_WRREQ_LEVEL[0],TCC_EA_WRREQ_DRAM_CREDIT_STALL[1],TCC_EA_WRREQ_GMI_CREDIT_STALL[1],TCC_EA_WRREQ_IO_CREDIT_STALL[1],TCC_EA_WRREQ_LEVEL[1],TCC_EA_WRREQ_DRAM_CREDIT_STALL[2],TCC_EA_WRREQ_GMI_CREDIT_STALL[2],TCC_EA_WRREQ_IO_CREDIT_STALL[2],TCC_EA_WRREQ_LEVEL[2],TCC_EA_WRREQ_DRAM_CREDIT_STALL[3],TCC_EA_WRREQ_GMI_CREDIT_STALL[3],TCC_EA_WRREQ_IO_CREDIT_STALL[3],TCC_EA_WRREQ_LEVEL[3],TCC_EA_WRREQ_DRAM_CREDIT_STALL[4],TCC_EA_WRREQ_GMI_CREDIT_STALL[4],TCC_EA_WRREQ_IO_CREDIT_STALL[4],TCC_EA_WRREQ_LEVEL[4],TCC_EA_WRREQ_DRAM_CREDIT_STALL[5],TCC_EA_WRREQ_GMI_CREDIT_STALL[5],TCC_EA_WRREQ_IO_CREDIT_STALL[5],TCC_EA_WRREQ_LEVEL[5],TCC_EA_WRREQ_DRAM_CREDIT_STALL[6],TCC_EA_WRREQ_GMI_CREDIT_STALL[6],TCC_EA_WRREQ_IO_CREDIT_STALL[6],TCC_EA_WRREQ_LEVEL[6],TCC_EA_WRREQ_DRAM_CREDIT_STALL[7],TCC_EA_WRREQ_GMI_CREDIT_STALL[7],TCC_EA_WRREQ_IO_CREDIT_STALL[7],TCC_EA_WRREQ_LEVEL[7],TCC_EA_WRREQ_DRAM_CREDIT_STALL[8],TCC_EA_WRREQ_GMI_CREDIT_STALL[8],TCC_EA_WRREQ_IO_CREDIT_STALL[8],TCC_EA_WRREQ_LEVEL[8],TCC_EA_WRREQ_DRAM_CREDIT_STALL[9],TCC_EA_WRREQ_GMI_CREDIT_STALL[9],TCC_EA_WRREQ_IO_CREDIT_STALL[9],TCC_EA_WRREQ_LEVEL[9],TCC_EA_WRREQ_DRAM_CREDIT_STALL[10],TCC_EA_WRREQ_GMI_CREDIT_STALL[10],TCC_EA_WRREQ_IO_CREDIT_STALL[10],TCC_EA_WRREQ_LEVEL[10],TCC_EA_WRREQ_DRAM_CREDIT_STALL[11],TCC_EA_WRREQ_GMI_CREDIT_STALL[11],TCC_EA_WRREQ_IO_CREDIT_STALL[11],TCC_EA_WRREQ_LEVEL[11],TCC_EA_WRREQ_DRAM_CREDIT_STALL[12],TCC_EA_WRREQ_GMI_CREDIT_STALL[12],TCC_EA_WRREQ_IO_CREDIT_STALL[12],TCC_EA_WRREQ_LEVEL[12],TCC_EA_WRREQ_DRAM_CREDIT_STALL[13],TCC_EA_WRREQ_GMI_CREDIT_STALL[13],TCC_EA_WRREQ_IO_CREDIT_STALL[13],TCC_EA_WRREQ_LEVEL[13],TCC_EA_WRREQ_DRAM_CREDIT_STALL[14],TCC_EA_WRREQ_GMI_CREDIT_STALL[14],TCC_EA_WRREQ_IO_CREDIT_STALL[14],TCC_EA_WRREQ_LEVEL[14],TCC_EA_WRREQ_DRAM_CREDIT_STALL[15],TCC_EA_WRREQ_GMI_CREDIT_STALL[15],TCC_EA_WRREQ_IO_CREDIT_STALL[15],TCC_EA_WRREQ_LEVEL[15],TCC_EA_WRREQ_DRAM_CREDIT_STALL[16],TCC_EA_WRREQ_GMI_CREDIT_STALL[16],TCC_EA_WRREQ_IO_CREDIT_STALL[16],TCC_EA_WRREQ_LEVEL[16],TCC_EA_WRREQ_DRAM_CREDIT_STALL[17],TCC_EA_WRREQ_GMI_CREDIT_STALL[17],TCC_EA_WRREQ_IO_CREDIT_STALL[17],TCC_EA_WRREQ_LEVEL[17],TCC_EA_WRREQ_DRAM_CREDIT_STALL[18],TCC_EA_WRREQ_GMI_CREDIT_STALL[18],TCC_EA_WRREQ_IO_CREDIT_STALL[18],TCC_EA_WRREQ_LEVEL[18],TCC_EA_WRREQ_DRAM_CREDIT_STALL[19],TCC_EA_WRREQ_GMI_CREDIT_STALL[19],TCC_EA_WRREQ_IO_CREDIT_STALL[19],TCC_EA_WRREQ_LEVEL[19],TCC_EA_WRREQ_DRAM_CREDIT_STALL[20],TCC_EA_WRREQ_GMI_CREDIT_STALL[20],TCC_EA_WRREQ_IO_CREDIT_STALL[20],TCC_EA_WRREQ_LEVEL[20],TCC_EA_WRREQ_DRAM_CREDIT_STALL[21],TCC_EA_WRREQ_GMI_CREDIT_STALL[21],TCC_EA_WRREQ_IO_CREDIT_STALL[21],TCC_EA_WRREQ_LEVEL[21],TCC_EA_WRREQ_DRAM_CREDIT_STALL[22],TCC_EA_WRREQ_GMI_CREDIT_STALL[22],TCC_EA_WRREQ_IO_CREDIT_STALL[22],TCC_EA_WRREQ_LEVEL[22],TCC_EA_WRREQ_DRAM_CREDIT_STALL[23],TCC_EA_WRREQ_GMI_CREDIT_STALL[23],TCC_EA_WRREQ_IO_CREDIT_STALL[23],TCC_EA_WRREQ_LEVEL[23],TCC_EA_WRREQ_DRAM_CREDIT_STALL[24],TCC_EA_WRREQ_GMI_CREDIT_STALL[24],TCC_EA_WRREQ_IO_CREDIT_STALL[24],TCC_EA_WRREQ_LEVEL[24],TCC_EA_WRREQ_DRAM_CREDIT_STALL[25],TCC_EA_WRREQ_GMI_CREDIT_STALL[25],TCC_EA_WRREQ_IO_CREDIT_STALL[25],TCC_EA_WRREQ_LEVEL[25],TCC_EA_WRREQ_DRAM_CREDIT_STALL[26],TCC_EA_WRREQ_GMI_CREDIT_STALL[26],TCC_EA_Line truncated
|
||||
0,"vecCopy(double*, double*, double*, int, int) ",2,1048576,256,0,0,8,8,16,64,0x7fa60a0bee80,0,8192,4096,8192,0,8192,4096,8192,141,8195,4240,8336,0,8192,4096,8192,0,8197,4101,8197,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8240,4144,8240,0,8192,4096,8192,0,8192,4096,8192,47,8193,4144,8240,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8242,4146,8242,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8360,4264,8360,64,0x7fa20f0d0e80,1702,0,0,1719740,7962,0,0,2367356,1813,0,0,1682111,4174,0,0,2059977,1812,0,0,1735455,2059,0,0,1820882,2228,0,0,1826548,1503,0,0,1832663,2208,0,0,1673719,3022,0,0,2011650,849,0,0,1676750,1486,0,0,1754130,884,0,0,1602921,1369,0,0,1692083,1511,0,0,1760530,978,0,0,1690457,567,0,0,1537905,891,0,0,1608514,2211,0,0,1855600,550,0,0,1576614,1147,0,0,1678056,1111,0,0,1713498,919,0,0,1679103,7020,0,0,2300285,1662,0,0,1775975,862,0,0,1635212,1516,0,0,1721473,4543,0,0,2101876,2041,0,0,1729683,2149,0,0,1839403,835,0,0,1673472,760,0,0,1686898,64,0x7fadad946e80,32768,0,0,0,16384,16384,393216,22494614,960.0,513961.0,0.0,524288.0,902516.0,32768.0,0,0,0,14994,131072.0,131072.0,0.0,131072.0,64,0x7fc9e4f16e80,188575,0,0,65536,64048,48,1440,32768,2097152.0,2097152.0,1048576.0,1048576.0,0.0,0.0,0.0,16384.0,10586,26970,9373,588,0,44803,262515.0,0.0,188.0,262327.0,64,0x7f8939bd2e80,1600702,360448,163840,0,0,180224,114688,0,69084961.0,191566858.0,77600155.0,131072.0,0.0,605821.0,0,0,25901,89611.0,0.0,0.0,89611.0,64,0x7fae20506e80,32768,0,16384,16384,32768,49152,0,65536,0.0,0.0,120.0,524288.0,0.0,0.0,0,0,913,46178,0,131495.0,131072.0,0.0,131104.0,64,0x7faf71fbce80,0,0,192,0,65536,64518,48,1273,31071,0.0,0.0,0.0,32768.0,0.0,0.0,0.0,32768.0,4096,16384,512,47162,1764,0,48.0,338.0,0.0,262288.0,64,0x7fcda68c2e80,0.0,64,0x7f553c3bae80,0,2583434,4096,4096,0,2661632,4096,4096,0,2414679,4096,4096,0,2739437,4096,4096,0,2917313,4096,4096,0,2717546,4096,4096,0,2839271,4096,4096,0,3065063,4096,4096,0,2536506,4096,4096,0,3139740,4096,4096,0,3318271,4096,4096,0,3565532,4096,4096,0,2469848,4096,4096,0,2758141,4096,4096,0,2904332,4096,4096,0,2749662,4096,4096,0,3557031,4096,4096,0,2731188,4096,4096,0,2458290,4096,4096,0,2807379,4096,4096,0,2428993,4096,4096,0,4082071,4096,4096,0,3132549,4096,4096,0,3590082,4096,4096,0,2481396,4096,4096,0,2116688,4096,4096,0,5439048,4096,4096,0,3236710,4096,4096,0,2627301,4096,4096,0,2026385,4096,4096,0,3445322,4096,4096,0,2947862,4096,4096,64,0x7f06658d2e80,1048576,0,0,0,0,0,131072,0.0,0.0,0.0,0.0,16384,0,87096.0,43976.0,131112.0,0.0,64,0x7f8bb3484e80,131072.0,131072.0,0.0,2423296.0,0.0,0.0,113076183.0,63585179.0,64,0x7f08c8c6ee80,377232,230257,3360996,16384,24549122,144,48,0,47153,47153,3806189.0,2991229.0,5194.0,1067106.0,2152951.0,0.0,2982418.0,2671847.0,375519,240188,47153,0,47153,0,1508896.0,959506.0,0.0,0.0,64,0x7f0b41e7ce80,4096,0,2925,0,4096,0,0,0,4099,0,0,0,4096,0,0,0,4096,0,2346,0,4264,0,728,0,4096,0,0,0,4096,0,0,0,4096,0,0,0,4097,0,729,0,4144,0,305,0,4096,0,144,0,4096,0,423,0,4096,0,0,0,4097,0,645,0,4096,0,377,0,4096,0,712,0,4096,0,9890,0,4096,0,1819,0,4096,0,0,0,4096,0,681,0,4096,0,0,0,4096,0,335,0,4096,0,876,0,4096,0,0,0,4096,0,0,0,4096,0,0,0,4096,0,0,0,4096,0,0,0,4096,0,1544,0,4144,0,0,0,4096,0,0,0,64,0x7f61d1a72e80,0,0,0,16384,0,0,0,0,0.0,0.0,0.0,0.0,16384.0,0.0,0,81920,0.0,0.0,40142.0,102709.0,64,0x7fc4fb86ae80,32768,32768,16384,16384,65536,49152,11534336,65536,131072.0,0.0,0.0,0.0,32768.0,16384.0,0,0,131414.0,0.0,676.0,131413.0,64,0x7fa068f46e80,8192,0,4096,8192,0,4096,8336,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,64,0x7f5cf2ffce80,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,0,47380,0,0,4896137259986,4896137284466
|
||||
1,"vecCopy(double*, double*, double*, int, int) ",2,1048576,256,0,0,8,8,16,64,0x7fa60a0bee80,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8197,4101,8197,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8241,4145,8241,0,8192,4096,8192,0,8192,4096,8192,47,8193,4144,8240,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8195,4099,8195,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8242,4146,8242,0,8193,4097,8193,0,8192,4096,8192,0,8192,4096,8192,0,8193,4097,8193,0,8192,4096,8192,0,8192,4096,8192,0,8192,4096,8192,0,8360,4264,8360,64,0x7fa20f0d0e80,703,0,0,1314581,1626,0,0,1411146,1341,0,0,1370964,4836,0,0,1731637,1024,0,0,1309194,1120,0,0,1431475,678,0,0,1348884,4387,0,0,1737711,1,0,0,1088934,3132,0,0,1604634,1043,0,0,1395819,1527,0,0,1499847,544,0,0,1186615,425,0,0,1215867,622,0,0,1287527,4774,0,0,1737759,402,0,0,1142761,1652,0,0,1414273,2670,0,0,1510005,2394,0,0,1536105,1492,0,0,1443618,2538,0,0,1490948,518,0,0,1365797,3729,0,0,1657440,775,0,0,1301207,403,0,0,1315041,711,0,0,1365433,6061,0,0,1791204,1067,0,0,1355112,3143,0,0,1609633,1084,0,0,1371101,4420,0,0,1670890,64,0x7fadad946e80,32768,0,0,0,16384,16384,393216,22837699,960.0,513930.0,0.0,524288.0,873696.0,32768.0,0,0,0,13937,86500.0,86500.0,0.0,86500.0,64,0x7fc9e4f16e80,119145,0,0,65536,64048,48,1440,32768,2097152.0,2097152.0,1048576.0,1048576.0,0.0,0.0,0.0,16384.0,13894,30278,7655,588,0,37776,262192.0,0.0,47.0,262145.0,64,0x7f8939bd2e80,1991511,360448,163840,0,0,180224,114688,0,64224164.0,180767688.0,89716576.0,131072.0,0.0,998830.0,0,0,29216,41226.0,0.0,0.0,41226.0,64,0x7fae20506e80,32768,0,16384,16384,32768,49152,0,65536,0.0,0.0,120.0,524288.0,0.0,0.0,0,0,3661,39636,0,131376.0,131072.0,0.0,87078.0,64,0x7faf71fbce80,0,0,48,0,65536,65536,0,0,31156,0.0,0.0,0.0,32768.0,0.0,0.0,0.0,32768.0,4096,16384,456,42855,1676,0,48.0,345.0,0.0,262144.0,64,0x7fcda68c2e80,0.0,64,0x7f553c3bae80,0,2603118,2652,2652,0,3227834,2702,2702,0,4376515,2678,2678,0,4755592,2713,2713,0,3240756,2664,2664,0,2918998,2736,2736,0,3360515,2722,2722,0,3918760,2712,2712,0,3308100,2680,2680,0,2923150,2704,2704,0,3288759,2704,2704,0,4056748,2744,2744,0,2798935,2674,2674,0,3813345,2696,2696,0,3569727,2700,2700,0,3581353,2708,2708,0,3307644,2688,2688,0,3555306,2700,2700,0,4250118,2702,2702,0,4011963,2712,2712,0,3515613,2682,2682,0,3364948,2743,2743,0,3352922,2696,2696,0,2908181,2700,2700,0,2433770,2660,2660,0,2801725,2713,2713,0,3368138,2750,2750,0,4798422,2720,2720,0,2674558,2654,2654,0,2944023,2702,2702,0,3378438,2746,2746,0,4740506,2702,2702,64,0x7f06658d2e80,1048576,0,0,0,0,0,131072,0.0,0.0,0.0,0.0,16384,0,86585.0,0.0,131112.0,0.0,64,0x7f8bb3484e80,131072.0,131072.0,0.0,2507694.0,0.0,0.0,116625128.0,46114905.0,64,0x7f08c8c6ee80,398816,253314,3699536,16384,26617376,0,96,0,49851,49851,4089209.0,3358735.0,5058.0,1371532.0,2528198.0,0.0,3342088.0,3028757.0,398808,263091,49851,0,49851,1133,1595232.0,892934.0,1.0,0.0,64,0x7f0b41e7ce80,4096,0,4109,0,4096,0,2628,0,4096,0,5212,0,4096,0,1096,0,4096,0,3532,0,4264,0,5388,0,4096,0,1527,0,4096,0,1219,0,4096,0,2403,0,4100,0,3629,0,4144,0,1511,0,4096,0,2390,0,4096,0,797,0,4096,0,4377,0,4097,0,1581,0,4097,0,1605,0,4096,0,2137,0,4096,0,3335,0,4096,0,2066,0,4096,0,2114,0,4097,0,5491,0,4096,0,6160,0,4096,0,3235,0,4097,0,2726,0,4096,0,725,0,4096,0,1832,0,4096,0,1195,0,4096,0,1637,0,4096,0,35,0,4096,0,187,0,4144,0,1075,0,4099,0,489,0,64,0x7f61d1a72e80,0,0,0,16384,0,0,0,0,0.0,0.0,0.0,0.0,16384.0,0.0,0,81920,0.0,0.0,54656.0,121442.0,64,0x7fc4fb86ae80,32768,32768,16384,16384,65536,49152,11534336,65536,131072.0,0.0,0.0,0.0,32768.0,16384.0,0,0,131089.0,0.0,32.0,131088.0,64,0x7fa068f46e80,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,8192,0,4096,64,0x7f5cf2ffce80,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,0,43156,0,0,4896137389586,4896137408466
|
||||
@@ -0,0 +1,2 @@
|
||||
workload_name,command,host_name,host_cpu,sbios,host_distro,host_kernel,host_rocmver,date,gpu_soc,vbios,numSE,numCU,numSIMD,waveSize,maxWavesPerCU,maxWorkgroupSize,L1,L2,sclk,mclk,cur_sclk,cur_mclk,L2Banks,totalL2Banks,LDSBanks,name,numSQC,numPipes,hbmBW,compute_partition,memory_partition,ip_blocks
|
||||
dispatch_0_1,./tests/vcopy -n 1048576 -b 256 -i 3,t007-002.hpcfund,AMD EPYC 7V13 64-Core Processor,American Megatrends Inc.0602,Rocky Linux 9.1 (Blue Onyx),5.14.0-162.18.1.el9_1.x86_64,5.7.1-98,Mon Feb 19 13:00:17 2024 (CST),gfx908,113-D3431401-100,8,120,4,64,40,1024,16,8192,1502,1200,1502,1200,32,32,32,MI100,30,4,1200,,,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF
|
||||
|
@@ -0,0 +1,3 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
|
||||
0,"vecCopy(double*, double*, double*, int, int) ",2,0,0,106919,106919,1048576,256,0,0,8,8,16,64,0x0,0x7f8475eece80,4896137232330,4896137259986,4896137284466,4896137296401
|
||||
1,"vecCopy(double*, double*, double*, int, int) ",2,0,2,106919,106919,1048576,256,0,0,8,8,16,64,0x0,0x7f8475eece80,4896137297253,4896137389586,4896137408466,4896137410026
|
||||
|
@@ -0,0 +1,2 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
|
||||
1,"vecCopy(double*, double*, double*, int, int) ",2,0,2,95615,95615,1048576,256,0,0,8,8,16,64,0x0,0x7f8cc503ee80,38738,38738,16384,65536,8147,1048608,4839256684968,4855077119856,4855077138416,4839264410295
|
||||
|
@@ -0,0 +1,2 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
|
||||
1,"vecCopy(double*, double*, double*, int, int) ",2,0,2,95412,95412,1048576,256,0,0,8,8,16,64,0x0,0x7f9b7976ee80,0,0,0,4838332549840,4855077119856,4855077138416,4838340188534
|
||||
|
@@ -0,0 +1,2 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
|
||||
1,"vecCopy(double*, double*, double*, int, int) ",2,0,2,96834,96834,1048576,256,0,0,8,8,16,64,0x0,0x7feee7c56e80,65536,86724,11090536,4845394358857,4855077119856,4855077138416,4845401906929
|
||||
|
@@ -0,0 +1,2 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
|
||||
1,"vecCopy(double*, double*, double*, int, int) ",2,0,2,98257,98257,1048576,256,0,0,8,8,16,64,0x0,0x7feaac5dce80,32768,648935,83060448,4851859046316,4855077119856,4855077138416,4851866625217
|
||||
|
@@ -0,0 +1,2 @@
|
||||
Dispatch_ID,Kernel_Name,GPU_ID,queue-id,queue-index,pid,tid,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,sig,obj,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES,DispatchNs,Start_Timestamp,End_Timestamp,CompleteNs
|
||||
1,"vecCopy(double*, double*, double*, int, int) ",2,0,2,96022,96022,1048576,256,0,0,8,8,16,64,0x0,0x7f9cc9a4ae80,39238,39238,12449,313912,16384,21856220,212342,0,87959476,4841278994784,4855077119856,4855077138416,4841286607339
|
||||
|
@@ -0,0 +1,5 @@
|
||||
pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_WAVES SQ_IFETCH SQ_IFETCH_LEVEL SQ_ACCUM_PREV_HIRES
|
||||
|
||||
gpu:
|
||||
range: 1
|
||||
kernel:
|
||||
@@ -0,0 +1,5 @@
|
||||
pmc: SQ_INSTS_LDS SQ_INST_LEVEL_LDS SQ_ACCUM_PREV_HIRES
|
||||
|
||||
gpu:
|
||||
range: 1
|
||||
kernel:
|
||||
Loaded 100 of 9701 files, more files were not shown because too many files have changed in this diff.
Show more
Reference in new issue
Block a user