Fix improper Min/Max operands.

Operands were relying on implicit type conversion which may result
in range errors.

Change-Id: I4b35ef92dcaf8b547aed02fea36aed75d392c6af

runtime/hsa-runtime/core/runtime/amd_aql_queue.cpp

@@ -791,7 +791,7 @@ bool AqlQueue::DynamicScratchHandler(hsa_signal_value_t error_code, void* arg) {
 #ifndef NDEBUG
       scratch.wanted_slots = ((uint64_t(pkt.dispatch.grid_size_x) * pkt.dispatch.grid_size_y) *
                               pkt.dispatch.grid_size_z) / scratch.lanes_per_wave;
-      scratch.wanted_slots = Min(scratch.wanted_slots, MaxScratchSlots);
+      scratch.wanted_slots = Min(scratch.wanted_slots, uint64_t(MaxScratchSlots));
 #endif
 
       queue->agent_->AcquireQueueScratch(scratch);

runtime/hsa-runtime/core/runtime/amd_blit_sdma.cpp

@@ -719,11 +719,11 @@ void BlitSdma<RingIndexTy, HwIndexMonotonic, SizeToCountOffset, useGCR>::BuildCo
   };
 
   // Limits in terms of element count
-  const uint max_pitch = 1 << SDMA_PKT_COPY_LINEAR_RECT::pitch_bits;
-  const uint max_slice = 1 << SDMA_PKT_COPY_LINEAR_RECT::slice_bits;
-  const uint max_x = 1 << SDMA_PKT_COPY_LINEAR_RECT::rect_xy_bits;
-  const uint max_y = 1 << SDMA_PKT_COPY_LINEAR_RECT::rect_xy_bits;
-  const uint max_z = 1 << SDMA_PKT_COPY_LINEAR_RECT::rect_z_bits;
+  const uint32_t max_pitch = 1 << SDMA_PKT_COPY_LINEAR_RECT::pitch_bits;
+  const uint32_t max_slice = 1 << SDMA_PKT_COPY_LINEAR_RECT::slice_bits;
+  const uint32_t max_x = 1 << SDMA_PKT_COPY_LINEAR_RECT::rect_xy_bits;
+  const uint32_t max_y = 1 << SDMA_PKT_COPY_LINEAR_RECT::rect_xy_bits;
+  const uint32_t max_z = 1 << SDMA_PKT_COPY_LINEAR_RECT::rect_z_bits;
 
   // Find maximum element that describes the pitch and slice.
   // Pitch and slice must both be represented in units of elements.  No element larger than this
@@ -764,11 +764,11 @@ void BlitSdma<RingIndexTy, HwIndexMonotonic, SizeToCountOffset, useGCR>::BuildCo
   }
 
   // Break copy into tiles
-  for (uint64_t z = 0; z < range->z; z += max_z) {
-    for (uint64_t y = 0; y < range->y; y += max_y) {
-      uint64_t x = 0;
+  for (uint32_t z = 0; z < range->z; z += max_z) {
+    for (uint32_t y = 0; y < range->y; y += max_y) {
+      uint32_t x = 0;
       while (x < range->x) {
-        uint64_t width = range->x - x;
+        uint32_t width = range->x - x;
 
         // Get largest element which describes the start of this tile after its base address has
         // been aligned.  Base addresses must be DWORD (4 byte) aligned.
@@ -833,7 +833,7 @@ void BlitSdma<RingIndexTy, HwIndexMonotonic, SizeToCountOffset, useGCR>::BuildFi
 
   for (uint32_t i = 0; i < num_fill_command; i++) {
     assert(count != 0 && "SDMA fill command count error.");
-    const uint32_t fill_count = Min(count, maxDwordCount);
+    const uint32_t fill_count = Min(count, size_t(maxDwordCount));
 
     memset(packet_addr, 0, sizeof(SDMA_PKT_CONSTANT_FILL));
 

runtime/hsa-runtime/core/runtime/runtime.cpp

@@ -808,7 +808,7 @@ hsa_status_t Runtime::PtrInfo(void* ptr, hsa_amd_pointer_info_t* info, void* (*a
     }
   }  // end lock scope
 
-  retInfo.size = Min(info->size, sizeof(hsa_amd_pointer_info_t));
+  retInfo.size = Min(size_t(info->size), sizeof(hsa_amd_pointer_info_t));
 
   // IPC and Graphics memory may come from a node that does not have an agent in this process.
   // Ex. ROCR_VISIBLE_DEVICES or peer GPU is not supported by ROCm.