Report managed memory capabilities

Change-Id: I241a42e26ee49fb47dcb3ba87c4bd8fb691dffdf


[ROCm/hip commit: d9f655f50e]
This commit is contained in:
German Andryeyev
2020-10-09 18:25:29 -04:00
parent f4be2fbc0b
commit 9c2eea15fb
4 changed files with 48 additions and 7 deletions
+17 -2
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@@ -139,7 +139,13 @@ typedef struct hipDeviceProp_t {
int cooperativeMultiDeviceUnmatchedSharedMem; ///< HIP device supports cooperative launch on multiple
///devices with unmatched shared memories
int isLargeBar; ///< 1: if it is a large PCI bar device, else 0
int asicRevision; ///< Revision of the GPU in this device.
int asicRevision; ///< Revision of the GPU in this device
int managedMemory; ///< Device supports allocating managed memory on this system
int directManagedMemAccessFromHost; ///< Host can directly access managed memory on the device without migration
int concurrentManagedAccess; ///< Device can coherently access managed memory concurrently with the CPU
int pageableMemoryAccess; ///< Device supports coherently accessing pageable memory
///< without calling hipHostRegister on it
int pageableMemoryAccessUsesHostPageTables; ///< Device accesses pageable memory via the host's page tables
} hipDeviceProp_t;
@@ -349,7 +355,16 @@ typedef enum hipDeviceAttribute_t {
///devices with unmatched block dimensions
hipDeviceAttributeCooperativeMultiDeviceUnmatchedSharedMem, ///< Supports cooperative launch on multiple
///devices with unmatched shared memories
hipDeviceAttributeAsicRevision ///< Revision of the GPU in this device
hipDeviceAttributeAsicRevision, ///< Revision of the GPU in this device
hipDeviceAttributeManagedMemory, ///< Device supports allocating managed memory on this system
hipDeviceAttributeDirectManagedMemAccessFromHost, ///< Host can directly access managed memory on
/// the device without migration
hipDeviceAttributeConcurrentManagedAccess, ///< Device can coherently access managed memory
/// concurrently with the CPU
hipDeviceAttributePageableMemoryAccess, ///< Device supports coherently accessing pageable memory
/// without calling hipHostRegister on it
hipDeviceAttributePageableMemoryAccessUsesHostPageTables, ///< Device accesses pageable memory via
/// the host's page tables
} hipDeviceAttribute_t;
enum hipComputeMode {
+7
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@@ -226,6 +226,13 @@ hipError_t hipGetDeviceProperties ( hipDeviceProp_t* props, hipDevice_t device )
deviceProps.isLargeBar = info.largeBar_ ? 1 : 0;
deviceProps.asicRevision = info.asicRevision_;
// HMM capabilities
deviceProps.managedMemory = info.hmmSupported_;
deviceProps.concurrentManagedAccess = info.hmmSupported_;
deviceProps.directManagedMemAccessFromHost = info.hmmDirectHostAccess_;
deviceProps.pageableMemoryAccess = info.hmmCpuMemoryAccessible_;
deviceProps.pageableMemoryAccessUsesHostPageTables = info.hostUnifiedMemory_;
*props = deviceProps;
HIP_RETURN(hipSuccess);
}
+16 -1
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@@ -298,7 +298,22 @@ hipError_t hipDeviceGetAttribute(int* pi, hipDeviceAttribute_t attr, int device)
break;
case hipDeviceAttributeAsicRevision:
*pi = prop.asicRevision;
break;
break;
case hipDeviceAttributeManagedMemory:
*pi = prop.managedMemory;
break;
case hipDeviceAttributeDirectManagedMemAccessFromHost:
*pi = prop.directManagedMemAccessFromHost;
break;
case hipDeviceAttributeConcurrentManagedAccess:
*pi = prop.concurrentManagedAccess;
break;
case hipDeviceAttributePageableMemoryAccess:
*pi = prop.pageableMemoryAccess;
break;
case hipDeviceAttributePageableMemoryAccessUsesHostPageTables:
*pi = prop.pageableMemoryAccessUsesHostPageTables;
break;
default:
HIP_RETURN(hipErrorInvalidValue);
}
+8 -4
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@@ -2031,6 +2031,7 @@ hipError_t hipHostGetDevicePointer(void** devicePointer, void* hostPointer, unsi
HIP_RETURN(hipSuccess);
}
// ================================================================================================
hipError_t hipPointerGetAttributes(hipPointerAttribute_t* attributes, const void* ptr) {
HIP_INIT_API(hipPointerGetAttributes, attributes, ptr);
@@ -2043,12 +2044,15 @@ hipError_t hipPointerGetAttributes(hipPointerAttribute_t* attributes, const void
memset(attributes, 0, sizeof(hipPointerAttribute_t));
if (memObj != nullptr) {
attributes->memoryType = ((CL_MEM_SVM_FINE_GRAIN_BUFFER | CL_MEM_USE_HOST_PTR) & memObj->getMemFlags())? hipMemoryTypeHost : hipMemoryTypeDevice;
attributes->memoryType = ((CL_MEM_SVM_FINE_GRAIN_BUFFER | CL_MEM_USE_HOST_PTR) &
memObj->getMemFlags())? hipMemoryTypeHost : hipMemoryTypeDevice;
if (attributes->memoryType == hipMemoryTypeHost) {
attributes->hostPointer = static_cast<char*>(memObj->getSvmPtr()) + offset;
}
attributes->devicePointer = static_cast<char*>(memObj->getSvmPtr()) + offset;
attributes->isManaged = 0;
constexpr uint32_t kManagedAlloc = (CL_MEM_SVM_FINE_GRAIN_BUFFER | CL_MEM_ALLOC_HOST_PTR);
attributes->isManaged =
((memObj->getMemFlags() & kManagedAlloc) == kManagedAlloc) ? true : false;
attributes->allocationFlags = memObj->getMemFlags() >> 16;
amd::Context* memObjCtx = &memObj->getContext();
@@ -2063,8 +2067,7 @@ hipError_t hipPointerGetAttributes(hipPointerAttribute_t* attributes, const void
}
++device;
}
DevLogPrintfError("Cannot find memory object context, memObjCtx: 0x%x \n",
memObjCtx);
DevLogPrintfError("Cannot find memory object context, memObjCtx: 0x%x \n", memObjCtx);
HIP_RETURN(hipErrorInvalidDevice);
}
@@ -2072,6 +2075,7 @@ hipError_t hipPointerGetAttributes(hipPointerAttribute_t* attributes, const void
HIP_RETURN(hipErrorInvalidValue);
}
// ================================================================================================
hipError_t hipArrayDestroy(hipArray* array) {
HIP_INIT_API(hipArrayDestroy, array);