Reset barrier and make barrier_next thread local (#1531)
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+9
-3
@@ -114,7 +114,6 @@ struct ncclShmemGroup {
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void* srcs[NCCL_MAX_ARITY+1];
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void* dsts[NCCL_MAX_ARITY+1];
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uint64_t barrier;
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uint64_t barrier_next[NCCL_MAX_GROUPS];
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union {
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unpackGroupShmem unpack;
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} devicePlugin;
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@@ -473,8 +472,6 @@ __device__ __forceinline__ void ncclKernelMain(struct ncclDevKernelArgs const* a
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ncclShmem.groups[tid-WARP_SIZE].barrier = 0;
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break;
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case 2:
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if (tid < 2*WARP_SIZE + NCCL_MAX_GROUPS*NCCL_MAX_GROUPS)
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ncclShmem.groups[(tid-2*WARP_SIZE)/NCCL_MAX_GROUPS].barrier_next[(tid-2*WARP_SIZE)%NCCL_MAX_GROUPS] = 0;
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break;
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case 3:
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/* set abort flag to 0 */
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@@ -551,6 +548,15 @@ __device__ __forceinline__ void ncclKernelMain(struct ncclDevKernelArgs const* a
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if (ncclShmem.nextBatchIx == -1) break;
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int batchIx = ncclShmem.nextBatchIx;
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__synclds();
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switch (tid/WARP_SIZE) {
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case 1:
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if (tid < WARP_SIZE + NCCL_MAX_GROUPS)
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ncclShmem.groups[tid-WARP_SIZE].barrier = 0;
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break;
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default:
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break;
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}
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__synclds();
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loadWorkBatchToShmem(tid%WARP_SIZE, tn, args, batchIx);
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// Check whether the last operation was aborted and make sure all threads exit
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@@ -28,12 +28,12 @@
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const int w = threadIdx.x/WARP_SIZE; \
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const int wid = threadIdx.x%WARP_SIZE; \
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if (wid == 0) { \
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barrier_next[w] += nthreads/WARP_SIZE; \
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barrier_next += nthreads/WARP_SIZE; \
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__hip_atomic_fetch_add(barriers, 1, __ATOMIC_RELEASE, __HIP_MEMORY_SCOPE_WORKGROUP); \
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int spins = 0; \
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int rate_limit = 50; \
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__THREAD_FENCE; \
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while (__hip_atomic_load(barriers, __ATOMIC_ACQUIRE, __HIP_MEMORY_SCOPE_WORKGROUP) < barrier_next[w]) { \
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while (__hip_atomic_load(barriers, __ATOMIC_ACQUIRE, __HIP_MEMORY_SCOPE_WORKGROUP) < barrier_next) { \
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spins++; \
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if (spins == NCCL_SPINS_BEFORE_CHECK_ABORT) { \
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if (__atomic_load_n(ncclShmem.comm.abortFlag, __ATOMIC_SEQ_CST)) { \
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@@ -44,7 +44,7 @@
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} \
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if (spins == 0 && rate_limit > 0) { \
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rate_limit --; \
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traceData(__LINE__, threadIdx.x, __hip_atomic_load(barriers, __ATOMIC_ACQUIRE, __HIP_MEMORY_SCOPE_WORKGROUP), barrier_next[w]); \
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traceData(__LINE__, threadIdx.x, __hip_atomic_load(barriers, __ATOMIC_ACQUIRE, __HIP_MEMORY_SCOPE_WORKGROUP), barrier_next); \
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} \
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__builtin_amdgcn_s_sleep(1); \
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} \
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@@ -66,7 +66,7 @@ private:
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inline __device__ uint32_t sendFlag(int i) { return NCCL_LL_FLAG(sendStep[i]+1); }
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uint64_t* barriers;
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uint64_t* barrier_next;
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uint64_t barrier_next = 0;
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inline __device__ void barrier() {
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#if defined(__HIP_PLATFORM_AMD__) || defined(__HIPCC__)
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@@ -622,7 +622,6 @@ private:
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stepLines(ncclShmem.comm.buffSizes[NCCL_PROTO_LL]/NCCL_STEPS/sizeof(ncclLLFifoLine)) {
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auto *channel = &ncclShmem.channel;
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barriers = &ncclShmem.groups[group].barrier;
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barrier_next = ncclShmem.groups[group].barrier_next;
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// If we are going to support oneshot collNet + LL, then we would need to add connector index here
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int nrecv=0, nsend=0;
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// We compare with Fan::MaxRecv here because this->MaxRecv is always at least 1
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@@ -62,7 +62,7 @@ class Primitives<T, RedOp, Fan, Direct, ProtoLL128, P2p>:
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inline __device__ uint64_t sendFlag(int i) { return sendStep[i]+1; }
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uint64_t* barriers;
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uint64_t* barrier_next;
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uint64_t barrier_next = 0;
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#if defined(ENABLE_NPKIT)
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public:
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@@ -508,7 +508,6 @@ public:
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stepSize(ncclShmem.comm.buffSizes[NCCL_PROTO_LL128]/NCCL_STEPS/sizeof(uint64_t)) {
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auto *channel = &ncclShmem.channel;
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barriers = &ncclShmem.groups[group].barrier;
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barrier_next = ncclShmem.groups[group].barrier_next;
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int nrecv=0, nsend=0;
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while (nrecv < MaxRecv && recvPeers[nrecv] >= 0) {
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loadRecvConn(&channel->peers[recvPeers[nrecv]]->recv[connIndexRecv], nrecv);
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@@ -54,7 +54,7 @@ class Primitives<
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void* netDeviceHandle;
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uint32_t* next_hdp_reg;
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uint64_t* barriers;
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uint64_t* barrier_next;
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uint64_t barrier_next = 0;
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int repeat;
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#if defined(ENABLE_NPKIT)
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@@ -671,7 +671,6 @@ private:
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// For send operations, we need an extra warp to overlap the threadfence and the copy
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barriers = &ncclShmem.groups[group].barrier;
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barrier_next = ncclShmem.groups[group].barrier_next;
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this->nworkers = nthreads;
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int nrecv=0, nsend=0;
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