P4 to Git Change 1250684 by gandryey@gera-w8 on 2016/03/23 17:59:05
SWDEV-86035 - Add PAL backend to OpenCL - Update PAL backend to match the latests PAL interfaces Affected files ... ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/Makefile#2 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/build/Makefile.pal#2 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palbe/build/Makefile#1 add ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palbe/build/Makefile.palbe#1 add ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palblit.cpp#2 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/paldevice.cpp#2 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/paldevice.hpp#2 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palkernel.cpp#2 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palkernel.hpp#2 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palprogram.cpp#2 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palprogram.hpp#2 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palvirtual.cpp#2 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palvirtual.hpp#2 edit
This commit is contained in:
foreman
@@ -937,6 +937,8 @@ KernelBlitManager::copyBufferToImage(
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static const bool CopyRect = false;
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// Flush DMA for ASYNC copy
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static const bool FlushDMA = true;
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size_t imgRowPitch = size[0] * gpuMem(dstMemory).elementSize();
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size_t imgSlicePitch = imgRowPitch * size[1];
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if (setup_.disableCopyBufferToImage_) {
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result = DmaBlitManager::copyBufferToImage(
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@@ -947,7 +949,9 @@ KernelBlitManager::copyBufferToImage(
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}
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// Check if buffer is in system memory with direct access
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else if (gpuMem(srcMemory).isHostMemDirectAccess() &&
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(rowPitch == 0) && (slicePitch == 0)) {
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(((rowPitch == 0) && (slicePitch == 0)) ||
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((rowPitch == imgRowPitch) &&
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((slicePitch == 0) || (slicePitch == imgSlicePitch))))) {
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// First attempt to do this all with DMA,
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// but there are restriciton with older hardware
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if (dev().settings().imageDMA_) {
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@@ -1327,6 +1331,8 @@ KernelBlitManager::copyImageToBuffer(
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static const bool CopyRect = false;
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// Flush DMA for ASYNC copy
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static const bool FlushDMA = true;
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size_t imgRowPitch = size[0] * gpuMem(srcMemory).elementSize();
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size_t imgSlicePitch = imgRowPitch * size[1];
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if (setup_.disableCopyImageToBuffer_) {
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result = HostBlitManager::copyImageToBuffer(
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@@ -1337,7 +1343,9 @@ KernelBlitManager::copyImageToBuffer(
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}
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// Check if buffer is in system memory with direct access
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else if (gpuMem(dstMemory).isHostMemDirectAccess() &&
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(rowPitch == 0) && (slicePitch == 0)) {
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(((rowPitch == 0) && (slicePitch == 0)) ||
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((rowPitch == imgRowPitch) &&
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((slicePitch == 0) || (slicePitch == imgSlicePitch))))) {
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// First attempt to do this all with DMA,
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// but there are restriciton with older hardware
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if (dev().settings().imageDMA_) {
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@@ -175,10 +175,10 @@ void NullDevice::fillDeviceInfo(
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info_.maxWorkItemDimensions_ = 3;
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info_.maxComputeUnits_ =
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palProp.gfxipProperties.engineCore.numOfShaderEngines *
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palProp.gfxipProperties.engineCore.numOfShaderArrays *
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palProp.gfxipProperties.engineCore.numOfCUsPerShaderArray;
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info_.numberOfShaderEngines = palProp.gfxipProperties.engineCore.numOfShaderEngines;
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palProp.gfxipProperties.shaderCore.numShaderEngines *
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palProp.gfxipProperties.shaderCore.numShaderArrays *
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palProp.gfxipProperties.shaderCore.numCusPerShaderArray;
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info_.numberOfShaderEngines = palProp.gfxipProperties.shaderCore.numShaderEngines;
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// SI parts are scalar. Also, reads don't need to be 128-bits to get peak rates.
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// For example, float4 is not faster than float as long as all threads fetch the same
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@@ -417,7 +417,7 @@ void NullDevice::fillDeviceInfo(
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info_.simdPerCU_ = hwInfo()->simdPerCU_;
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info_.simdWidth_ = hwInfo()->simdWidth_;
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info_.simdInstructionWidth_ = hwInfo()->simdInstructionWidth_;
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info_.wavefrontWidth_ = palProp.gfxipProperties.engineCore.wavefrontSize;
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info_.wavefrontWidth_ = palProp.gfxipProperties.shaderCore.wavefrontSize;
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//info_.globalMemChannels_ = calAttr.memBusWidth / 32;
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//info_.globalMemChannelBanks_ = calAttr.numMemBanks;
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info_.globalMemChannelBankWidth_ = hwInfo()->memChannelBankWidth_;
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@@ -1541,35 +1541,34 @@ Device::createView(amd::Memory& owner, const device::Memory& parent) const
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//! Attempt to bind with external graphics API's device/context
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bool
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Device::bindExternalDevice(intptr_t type, void* pDevice, void* pContext, bool validateOnly)
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Device::bindExternalDevice(uint flags, void* pDevice, void* pContext, bool validateOnly)
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{
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assert(pDevice);
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switch (type) {
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#ifdef _WIN32
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case CL_CONTEXT_D3D10_DEVICE_KHR:
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if (flags & amd::Context::Flags::D3D10DeviceKhr) {
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if (!associateD3D10Device(pDevice)) {
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LogError("Failed gslD3D10Associate()");
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return false;
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}
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break;
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case CL_CONTEXT_D3D11_DEVICE_KHR:
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}
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else if (flags & amd::Context::Flags::D3D11DeviceKhr) {
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if (!associateD3D11Device(pDevice)) {
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LogError("Failed gslD3D11Associate()");
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return false;
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}
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break;
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case CL_CONTEXT_ADAPTER_D3D9_KHR:
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case CL_CONTEXT_ADAPTER_D3D9EX_KHR:
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}
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else if (flags & (amd::Context::Flags::D3D9DeviceKhr |
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amd::Context::Flags::D3D9DeviceEXKhr)) {
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if (!associateD3D9Device(pDevice)) {
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LogWarning("D3D9<->OpenCL adapter mismatch or D3D9Associate() failure");
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return false;
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}
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break;
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case CL_CONTEXT_ADAPTER_DXVA_KHR:
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break;
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}
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else if (flags & amd::Context::Flags::D3D9DeviceVAKhr) {
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}
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#endif //_WIN32
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case CL_GL_CONTEXT_KHR:
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if (flags & amd::Context::Flags::GLDeviceKhr) {
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// Attempt to associate GSL-OGL
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if (!glAssociate(pContext, pDevice)) {
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if (!validateOnly) {
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@@ -1577,20 +1576,15 @@ Device::bindExternalDevice(intptr_t type, void* pDevice, void* pContext, bool va
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}
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return false;
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}
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break;
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default:
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LogError("Unknown external device!");
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return false;
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break;
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}
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return true;
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}
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bool
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Device::unbindExternalDevice(intptr_t type, void* pDevice, void* pContext, bool validateOnly)
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Device::unbindExternalDevice(uint flags, void* pDevice, void* pContext, bool validateOnly)
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{
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if (type != CL_GL_CONTEXT_KHR) {
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if ((flags & amd::Context::Flags::GLDeviceKhr) == 0) {
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return true;
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}
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@@ -1820,8 +1814,8 @@ Device::allocScratch(uint regNum, const VirtualGPU* vgpu)
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// Calculate the size of the scratch buffer for a queue
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uint32_t numTotalCUs = info().maxComputeUnits_;
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uint32_t numMaxWaves =
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properties().gfxipProperties.engineCore.maxScratchWavesPerCU * numTotalCUs;
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scratchBuf->size_ = properties().gfxipProperties.engineCore.wavefrontSize *
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properties().gfxipProperties.shaderCore.maxScratchWavesPerCu * numTotalCUs;
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scratchBuf->size_ = properties().gfxipProperties.shaderCore.wavefrontSize *
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scratchBuf->regNum_ * numMaxWaves * sizeof(uint32_t);
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scratchBuf->size_ = amd::alignUp(scratchBuf->size_, 0xFFFF);
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scratchBuf->offset_ = offset;
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@@ -1920,8 +1914,7 @@ Device::fillHwSampler(
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samplerInfo.borderColorType = Pal::BorderColorType::TransparentBlack;
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// Assign defaults
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samplerInfo.filter = Pal::TexFilter::MagPointMinPointMipBase;
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samplerInfo.filter.zFilter = Pal::XyFilterPoint;
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samplerInfo.flags.unnormalizedCoords = !(state & amd::Sampler::StateNormalizedCoordsMask);
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@@ -1956,24 +1949,16 @@ Device::fillHwSampler(
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// Program texture filter mode
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if (state == amd::Sampler::StateFilterLinear) {
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samplerInfo.filter = Pal::TexFilter::MagLinearMinLinearMipBase;
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samplerInfo.filter.magnification = Pal::XyFilterLinear;
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samplerInfo.filter.minification = Pal::XyFilterLinear;
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samplerInfo.filter.zFilter = Pal::ZFilterLinear;
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}
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if (mipFilter == CL_FILTER_NEAREST) {
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if (state == amd::Sampler::StateFilterLinear) {
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samplerInfo.filter = Pal::TexFilter::MagLinearMinLinearMipPoint;
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}
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else {
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samplerInfo.filter = Pal::TexFilter::MagPointMinPointMipPoint;
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}
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samplerInfo.filter.mipFilter = Pal::MipFilterPoint;
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}
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else if (mipFilter == CL_FILTER_LINEAR) {
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if (state == amd::Sampler::StateFilterLinear) {
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samplerInfo.filter = Pal::TexFilter::MagLinearMinLinearMipLinear;
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}
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else {
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samplerInfo.filter = Pal::TexFilter::MagPointMinPointMipLinear;
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}
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samplerInfo.filter.mipFilter = Pal::MipFilterLinear;
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}
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iDev()->CreateSamplerSrds(1, &samplerInfo, hwState);
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@@ -91,10 +91,10 @@ public:
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//! Needed for OpenGL objects on CPU device
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virtual bool bindExternalDevice(
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intptr_t type, void* pDevice, void* pContext, bool validateOnly) { return true; }
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uint flags, void* pDevice, void* pContext, bool validateOnly) { return true; }
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virtual bool unbindExternalDevice(
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intptr_t type, void* pDevice, void* pContext, bool validateOnly) { return true; }
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uint flags, void* pDevice, void* pContext, bool validateOnly) { return true; }
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//! Releases non-blocking map target memory
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virtual void freeMapTarget(amd::Memory& mem, void* target) {}
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@@ -369,17 +369,11 @@ public:
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//! Attempt to bind with external graphics API's device/context
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virtual bool bindExternalDevice(
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intptr_t type,
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void* pDevice,
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void* pContext,
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bool validateOnly);
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uint flags, void* pDevice, void* pContext, bool validateOnly);
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//! Attempt to unbind with external graphics API's device/context
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virtual bool unbindExternalDevice(
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intptr_t type,
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void* pDevice,
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void* pContext,
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bool validateOnly);
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uint flags, void* pDevice, void* pContext, bool validateOnly);
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//! Validates kernel before execution
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virtual bool validateKernel(
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@@ -387,40 +387,49 @@ HSAILKernel::aqlCreateHWInfo(amd::hsa::loader::Symbol *sym)
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if (!sym->GetInfo(HSA_EXT_EXECUTABLE_SYMBOL_INFO_KERNEL_OBJECT_ALIGN, reinterpret_cast<void*>(&akc_align))) {
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return false;
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}
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code_ = new Memory(dev(), amd::alignUp(codeSize_, akc_align));
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Resource::MemoryType type = Resource::RemoteUSWC;
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if (flags_.internalKernel_) {
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type = Resource::RemoteUSWC;
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}
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// Initialize kernel ISA code
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if (code_ && code_->create(type)) {
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address cpuCodePtr = static_cast<address>(code_->map(nullptr, Resource::WriteOnly));
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// Copy only amd_kernel_code_t
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memcpy(cpuCodePtr, reinterpret_cast<address>(akc), codeSize_);
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code_->unmap(nullptr);
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}
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else {
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LogError("Failed to allocate ISA code!");
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return false;
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// Allocate HW resources for the real program only
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if (!prog().isNull()) {
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code_ = new Memory(dev(), amd::alignUp(codeSize_, akc_align));
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Resource::MemoryType type = Resource::RemoteUSWC;
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if (flags_.internalKernel_) {
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type = Resource::RemoteUSWC;
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}
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// Initialize kernel ISA code
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if (code_ && code_->create(type)) {
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address cpuCodePtr = static_cast<address>(code_->map(nullptr, Resource::WriteOnly));
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// Copy only amd_kernel_code_t
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memcpy(cpuCodePtr, reinterpret_cast<address>(akc), codeSize_);
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code_->unmap(nullptr);
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}
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else {
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LogError("Failed to allocate ISA code!");
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return false;
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}
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}
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assert((akc->workitem_private_segment_byte_size & 3) == 0 &&
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"Scratch must be DWORD aligned");
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workGroupInfo_.scratchRegs_ =
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amd::alignUp(akc->workitem_private_segment_byte_size, 16) / sizeof(uint);
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/*
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workGroupInfo_.availableSGPRs_ = dev().gslCtx()->getNumSGPRsAvailable();
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workGroupInfo_.availableVGPRs_ = dev().gslCtx()->getNumVGPRsAvailable();
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workGroupInfo_.preferredSizeMultiple_ = dev().getAttribs().wavefrontSize;
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workGroupInfo_.wavefrontPerSIMD_ = dev().getAttribs().wavefrontSize;
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*/
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workGroupInfo_.privateMemSize_ = akc->workitem_private_segment_byte_size;
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workGroupInfo_.localMemSize_ =
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workGroupInfo_.usedLDSSize_ = akc->workgroup_group_segment_byte_size;
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workGroupInfo_.usedSGPRs_ = akc->wavefront_sgpr_count;
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workGroupInfo_.usedStackSize_ = 0;
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workGroupInfo_.usedVGPRs_ = akc->workitem_vgpr_count;
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if (!prog().isNull()) {
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workGroupInfo_.availableSGPRs_ = dev().properties().gfxipProperties.shaderCore.numAvailableSgprs;
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workGroupInfo_.availableVGPRs_ = dev().properties().gfxipProperties.shaderCore.numAvailableVgprs;
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workGroupInfo_.preferredSizeMultiple_ =
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workGroupInfo_.wavefrontPerSIMD_ = dev().properties().gfxipProperties.shaderCore.wavefrontSize;
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}
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else {
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workGroupInfo_.availableSGPRs_ = 104;
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workGroupInfo_.availableVGPRs_ = 256;
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workGroupInfo_.preferredSizeMultiple_ =
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workGroupInfo_.wavefrontPerSIMD_ = 64;
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}
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return true;
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}
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@@ -633,10 +642,7 @@ HSAILKernel::init(amd::hsa::loader::Symbol *sym, bool finalize)
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}
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}
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// Allocate HW resources for the real program only
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if (!prog().isNull()) {
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aqlCreateHWInfo(sym);
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}
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aqlCreateHWInfo(sym);
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// Pull out metadata from the ELF
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size_t sizeOfArgList;
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@@ -153,7 +153,7 @@ public:
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{ return cpuAqlCode_->workgroup_group_segment_byte_size; }
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//! Returns pointer on CPU to AQL code info
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const void* cpuAqlCode() const { return cpuAqlCode_; }
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const amd_kernel_code_t* cpuAqlCode() const { return cpuAqlCode_; }
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//! Returns memory object with AQL code
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pal::Memory* gpuAqlCode() const { return code_; }
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@@ -505,7 +505,7 @@ HSAILProgram::linkImpl(amd::option::Options* options)
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hsa_agent_t agent;
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agent.handle = 1;
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if (!isNull() && hsaLoad) {
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executable_ = loader_->CreateExecutable(HSA_PROFILE_BASE, nullptr);
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executable_ = loader_->CreateExecutable(HSA_PROFILE_FULL, NULL);
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if (executable_ == nullptr) {
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buildLog_ += "Error: Executable for AMD HSA Code Object isn't created.\n";
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return false;
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@@ -55,6 +55,11 @@ public:
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void* SegmentAddress(amdgpu_hsa_elf_segment_t segment,
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hsa_agent_t agent, void* seg, size_t offset) override;
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void* SegmentHostAddress(amdgpu_hsa_elf_segment_t segment,
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hsa_agent_t agent, void* seg, size_t offset) override {
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return nullptr;
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}
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bool SegmentFreeze(amdgpu_hsa_elf_segment_t segment,
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hsa_agent_t agent, void* seg, size_t size) override { return false; }
|
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|
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@@ -43,6 +43,7 @@ VirtualGPU::Queue::Create(
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Pal::QueueCreateInfo qCreateInfo = {};
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qCreateInfo.engineType = queueType;
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qCreateInfo.engineIndex = engineIdx;
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qCreateInfo.aqlQueue = true;
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// Find queue object size
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size_t qSize = palDev->GetQueueSize(qCreateInfo, &result);
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@@ -181,8 +182,10 @@ VirtualGPU::Queue::flush()
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memRef.push_back(it->first);
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}
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}
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if (memRef.size() != 0) {
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iDev_->AddGpuMemoryReferences(memRef.size(), &memRef[0], iQueue_);
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iDev_->AddGpuMemoryReferences(memRef.size(), &memRef[0], iQueue_,
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Pal::GpuMemoryRefCantTrim);
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}
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// Submit command buffer to OS
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@@ -1982,12 +1985,12 @@ VirtualGPU::submitKernelInternal(
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eventBegin(MainEngine);
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if (nullptr == scratch) {
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iCmd()->CmdDispatchAql(aqlPkt, 0, 0, 0,
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hsaKernel.cpuAqlCode(), hsaQueueMem_->vmAddress(), pKernelInfo, 0x3ff);
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hsaKernel.cpuAqlCode(), hsaQueueMem_->vmAddress(), 0x3ff);
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}
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else {
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iCmd()->CmdDispatchAql(aqlPkt, scratch->memObj_->vmAddress(),
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scratch->size_, scratch->offset_,
|
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hsaKernel.cpuAqlCode(), hsaQueueMem_->vmAddress(), pKernelInfo, 0x3ff);
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hsaKernel.cpuAqlCode(), hsaQueueMem_->vmAddress(), 0x3ff);
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}
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eventEnd(MainEngine, gpuEvent);
|
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|
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|
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@@ -69,7 +69,8 @@ public:
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void addMemRef(Pal::IGpuMemory* iMem) const
|
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{
|
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iDev_->AddGpuMemoryReferences(1, &iMem, NULL);
|
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iDev_->AddGpuMemoryReferences(1, &iMem, NULL,
|
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Pal::GpuMemoryRefCantTrim);
|
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}
|
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void removeMemRef(Pal::IGpuMemory* iMem) const
|
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{
|
||||
|
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