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P4 to Git Change 1449513 by skudchad@skudchad_test_win_opencl2 on 2017/08/20 12:41:18

Sfoglia il codice sorgente 
SWDEV-107271 - Add Raven IDs.
	- Refactor PAL backend code

Affected files ...

... //depot/stg/opencl/drivers/opencl/compiler/legacy-lib/utils/v0_8/libUtils.cpp#6 edit
... //depot/stg/opencl/drivers/opencl/compiler/legacy-lib/utils/v0_8/target_mappings.h#19 edit
... //depot/stg/opencl/drivers/opencl/compiler/legacy-lib/utils/v0_8/target_mappings_hsail.h#22 edit
... //depot/stg/opencl/drivers/opencl/compiler/legacy-lib/utils/v0_8/target_mappings_hsail64.h#22 edit
... //depot/stg/opencl/drivers/opencl/compiler/lib/backends/common/linker.cpp#155 edit
... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/libUtils.cpp#26 edit
... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings.h#51 edit
... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings_hsail.h#47 edit
... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings_hsail64.h#42 edit
... //depot/stg/opencl/drivers/opencl/compiler/tools/driver/driver.cpp#66 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/paldefs.hpp#17 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/paldevice.cpp#49 edit
... //depot/stg/opencl/drivers/opencl/tests/ocltst/module/math/OCLMathFunc.cpp#29 edit
... //depot/stg/opencl/drivers/opencl/tests/ocltst/module/runtime/OCLDeviceQueries.cpp#45 edit
... //depot/stg/opencl/drivers/opencl/tests/ocltst/module/runtime/OCLPerfCounters.cpp#39 edit
This commit is contained in:
foreman
2017-08-20 12:49:56 -04:00
parent aa2a61f18a
commit a643fcf3d1
7 ha cambiato i file con 109 aggiunte e 71 eliminazioni
Scarica il file Patch Scarica il file Diff Expand all files Collapse all files
rocclr/compiler/lib/backends/common/linker.cpp
+3 -1
Vedi File
@@ -583,7 +583,9 @@ amdcl::OCLLinker::link(llvm::Module* input, std::vector<std::unique_ptr<llvm::Mo
|| chip == "Hawaii"
|| chip == "Carrizo"
|| chip == "gfx900"
|| chip == "gfx901");
|| chip == "gfx901"
|| chip == "gfx902"
|| chip == "gfx903");
setISAVersion(getIsaType(aclutGetTargetInfo(Elf())));
LLVMBinary()->getContext().setAMDLLVMContextHook(&hookup_);
rocclr/compiler/lib/utils/v0_8/libUtils.cpp
+7 -3
Vedi File
@@ -24,6 +24,8 @@ static const std::string sgfx804 = "AMD:AMDGPU:8:0:4";
static const std::string sgfx810 = "AMD:AMDGPU:8:1:0";
static const std::string sgfx900 = "AMD:AMDGPU:9:0:0";
static const std::string sgfx901 = "AMD:AMDGPU:9:0:1";
static const std::string sgfx902 = "AMD:AMDGPU:9:0:2";
static const std::string sgfx903 = "AMD:AMDGPU:9:0:3";
// Utility function to set a flag in option structure
// of the aclDevCaps.
@@ -526,6 +528,8 @@ const std::string &getIsaTypeName(const aclTargetInfo *target)
case 810: return sgfx810;
case 900: return sgfx900;
case 901: return sgfx901;
case 902: return sgfx902;
case 903: return sgfx903;
}
}
@@ -587,12 +591,12 @@ int getIsaType(const aclTargetInfo *target)
case FAMILY_AI:
switch (Mapping.chip_enum) {
default: return 900;
case AI_GREENLAND_P_A0: return 900;
case AI_GREENLAND_P_A0: return Mapping.xnack_supported ? 901 : 900;
}
case FAMILY_RV:
switch (Mapping.chip_enum) {
default: return 901;
case RAVEN_A0: return 901;
default: return 902;
case RAVEN_A0: return Mapping.xnack_supported ? 903 : 902;
}
}
}
rocclr/compiler/lib/utils/v0_8/target_mappings.h
+3
Vedi File
@@ -30,6 +30,7 @@ typedef struct _target_mappings_rec {
bool supported; // a false value means this device is not supported.
bool default_chip; // Chip to select if multiple chips with the same name exist.
unsigned family_enum; // Only used for GPU devices currently, for CPU we should put features.
bool xnack_supported; // XNACK support as per http://confluence.amd.com/pages/viewpage.action?spaceKey=ASLC&title=AMDGPU+Target+Names
} TargetMapping;
const TargetMapping UnknownTarget = { "UnknownFamily", "UnknownChip", "UnknownCodeGen",
@@ -210,6 +211,8 @@ static const char* calTargetMapping[] = {
"Stoney",
IF(IS_BRAHMA,"","gfx804"),
IF(IS_BRAHMA,"","gfx901"),
IF(IS_BRAHMA,"","gfx902"),
IF(IS_BRAHMA,"","gfx903"),
};
#include "utils/v0_8/target_mappings_amdil.h"
rocclr/compiler/lib/utils/v0_8/target_mappings_hsail.h
+21 -17
Vedi File
@@ -14,33 +14,37 @@
static const TargetMapping HSAILTargetMapping_0_8[] = {
UnknownTarget,
{ "KV", "Spectre", "GFX7", amd::GPU_Library_HSAIL, KV_SPECTRE_A0, F_CI_BASE, true, true, FAMILY_KV },
{ "KV", "Spooky", "GFX7", amd::GPU_Library_HSAIL, KV_SPOOKY_A0, F_CI_BASE, true, true, FAMILY_KV },
{ "KV", "Kalindi", "GFX7", amd::GPU_Library_HSAIL, KB_KALINDI_A0, F_CI_BASE, true, true, FAMILY_KV },
{ "KV", "Mullins", "GFX7", amd::GPU_Library_HSAIL, ML_GODAVARI_A0, F_CI_BASE, true, true, FAMILY_KV },
{ "CI", "Bonaire", "GFX7", amd::GPU_Library_HSAIL, CI_BONAIRE_M_A0, F_CI_BASE, true, false, FAMILY_CI },
{ "CI", "Bonaire", "GFX7", amd::GPU_Library_HSAIL, CI_BONAIRE_M_A1, F_CI_BASE, true, true, FAMILY_CI },
{ "CI", "Hawaii", "GFX7", amd::GPU_Library_HSAIL, CI_HAWAII_P_A0, F_CI_BASE, true, true, FAMILY_CI },
{ "VI", "Iceland", "GFX8", amd::GPU_Library_HSAIL, VI_ICELAND_M_A0, F_VI_BASE, true, true, FAMILY_VI },
{ "VI", "Tonga", "GFX8", amd::GPU_Library_HSAIL, VI_TONGA_P_A0, F_VI_BASE, true, true, FAMILY_VI },
{ "KV", "Spectre", "GFX7", amd::GPU_Library_HSAIL, KV_SPECTRE_A0, F_CI_BASE, true, true, FAMILY_KV, false },
{ "KV", "Spooky", "GFX7", amd::GPU_Library_HSAIL, KV_SPOOKY_A0, F_CI_BASE, true, true, FAMILY_KV, false },
{ "KV", "Kalindi", "GFX7", amd::GPU_Library_HSAIL, KB_KALINDI_A0, F_CI_BASE, true, true, FAMILY_KV, false },
{ "KV", "Mullins", "GFX7", amd::GPU_Library_HSAIL, ML_GODAVARI_A0, F_CI_BASE, true, true, FAMILY_KV, false },
{ "CI", "Bonaire", "GFX7", amd::GPU_Library_HSAIL, CI_BONAIRE_M_A0, F_CI_BASE, true, false, FAMILY_CI, false },
{ "CI", "Bonaire", "GFX7", amd::GPU_Library_HSAIL, CI_BONAIRE_M_A1, F_CI_BASE, true, true, FAMILY_CI, false },
{ "CI", "Hawaii", "GFX7", amd::GPU_Library_HSAIL, CI_HAWAII_P_A0, F_CI_BASE, true, true, FAMILY_CI, false },
{ "VI", "Iceland", "GFX8", amd::GPU_Library_HSAIL, VI_ICELAND_M_A0, F_VI_BASE, true, true, FAMILY_VI, false },
{ "VI", "Tonga", "GFX8", amd::GPU_Library_HSAIL, VI_TONGA_P_A0, F_VI_BASE, true, true, FAMILY_VI, false },
UnknownTarget,
UnknownTarget,
{ "CZ", "Carrizo", "GFX8", amd::GPU_Library_HSAIL, CARRIZO_A0, F_VI_BASE, true, true, FAMILY_CZ },
{ "VI", "Fiji", "GFX8", amd::GPU_Library_HSAIL, VI_FIJI_P_A0, F_VI_BASE, true, true, FAMILY_VI },
{ "CZ", "Stoney", "GFX8", amd::GPU_Library_HSAIL, STONEY_A0, F_VI_BASE, true, true, FAMILY_CZ },
{ "VI", "Baffin", "GFX8", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A0, F_VI_BASE, true, false, FAMILY_VI },
{ "VI", "Baffin", "GFX8", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A1, F_VI_BASE, true, true, FAMILY_VI },
{ "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A0, F_VI_BASE, true, false, FAMILY_VI },
{ "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A1, F_VI_BASE, true, true, FAMILY_VI },
{ "CZ", "Carrizo", "GFX8", amd::GPU_Library_HSAIL, CARRIZO_A0, F_VI_BASE, true, true, FAMILY_CZ, false },
{ "VI", "Fiji", "GFX8", amd::GPU_Library_HSAIL, VI_FIJI_P_A0, F_VI_BASE, true, true, FAMILY_VI, false },
{ "CZ", "Stoney", "GFX8", amd::GPU_Library_HSAIL, STONEY_A0, F_VI_BASE, true, true, FAMILY_CZ, false },
{ "VI", "Baffin", "GFX8", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A0, F_VI_BASE, true, false, FAMILY_VI, false },
{ "VI", "Baffin", "GFX8", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A1, F_VI_BASE, true, true, FAMILY_VI, false },
{ "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A0, F_VI_BASE, true, false, FAMILY_VI, false },
{ "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A1, F_VI_BASE, true, true, FAMILY_VI, false },
#ifndef BRAHMA
{ "AI", "gfx900", "GFX9", amd::GPU_Library_HSAIL, AI_GREENLAND_P_A0, F_AI_BASE, true, true, FAMILY_AI },
{ "VI", "gfx804", "GFX8", amd::GPU_Library_HSAIL, VI_LEXA_V_A0, F_VI_BASE, true, true, FAMILY_VI },
{ "RV", "gfx901", "GFX9", amd::GPU_Library_HSAIL, RAVEN_A0, F_AI_BASE, true, true, FAMILY_RV },
{ "AI", "gfx901", "GFX9", amd::GPU_Library_HSAIL, AI_GREENLAND_P_A0, F_AI_BASE, true, true, FAMILY_AI ,true },
{ "RV", "gfx902", "GFX9", amd::GPU_Library_HSAIL, RAVEN_A0, F_AI_BASE, true, true, FAMILY_RV, false },
{ "RV", "gfx903", "GFX9", amd::GPU_Library_HSAIL, RAVEN_A0, F_AI_BASE, true, true, FAMILY_RV, true },
#else
UnknownTarget,
UnknownTarget,
UnknownTarget,
UnknownTarget,
UnknownTarget,
#endif
InvalidTarget
};
rocclr/compiler/lib/utils/v0_8/target_mappings_hsail64.h
+23 -19
Vedi File
@@ -13,33 +13,37 @@
static const TargetMapping HSAIL64TargetMapping_0_8[] = {
UnknownTarget,
{ "KV", "Spectre", "GFX7", amd::GPU_Library_HSAIL, KV_SPECTRE_A0, F_CI_BASE, true, true, FAMILY_KV },
{ "KV", "Spooky", "GFX7", amd::GPU_Library_HSAIL, KV_SPOOKY_A0, F_CI_BASE, true, true, FAMILY_KV },
{ "KV", "Kalindi", "GFX7", amd::GPU_Library_HSAIL, KB_KALINDI_A0, F_CI_BASE, true, true, FAMILY_KV },
{ "KV", "Mullins", "GFX7", amd::GPU_Library_HSAIL, ML_GODAVARI_A0, F_CI_BASE, true, true, FAMILY_KV },
{ "CI", "Bonaire", "GFX7", amd::GPU_Library_HSAIL, CI_BONAIRE_M_A0, F_CI_BASE, true, false, FAMILY_CI },
{ "CI", "Bonaire", "GFX7", amd::GPU_Library_HSAIL, CI_BONAIRE_M_A1, F_CI_BASE, true, true, FAMILY_CI },
{ "CI", "Hawaii", "GFX7", amd::GPU_Library_HSAIL, CI_HAWAII_P_A0, F_CI_BASE, true, true, FAMILY_CI },
{ "VI", "Iceland", "GFX8", amd::GPU_Library_HSAIL, VI_ICELAND_M_A0, F_VI_BASE, true, true, FAMILY_VI },
{ "VI", "Tonga", "GFX8", amd::GPU_Library_HSAIL, VI_TONGA_P_A0, F_VI_BASE, true, true, FAMILY_VI },
{ "KV", "Spectre", "GFX7", amd::GPU_Library_HSAIL, KV_SPECTRE_A0, F_CI_BASE, true, true, FAMILY_KV, false },
{ "KV", "Spooky", "GFX7", amd::GPU_Library_HSAIL, KV_SPOOKY_A0, F_CI_BASE, true, true, FAMILY_KV, false },
{ "KV", "Kalindi", "GFX7", amd::GPU_Library_HSAIL, KB_KALINDI_A0, F_CI_BASE, true, true, FAMILY_KV, false },
{ "KV", "Mullins", "GFX7", amd::GPU_Library_HSAIL, ML_GODAVARI_A0, F_CI_BASE, true, true, FAMILY_KV, false },
{ "CI", "Bonaire", "GFX7", amd::GPU_Library_HSAIL, CI_BONAIRE_M_A0, F_CI_BASE, true, false, FAMILY_CI, false },
{ "CI", "Bonaire", "GFX7", amd::GPU_Library_HSAIL, CI_BONAIRE_M_A1, F_CI_BASE, true, true, FAMILY_CI, false },
{ "CI", "Hawaii", "GFX7", amd::GPU_Library_HSAIL, CI_HAWAII_P_A0, F_CI_BASE, true, true, FAMILY_CI, false },
{ "VI", "Iceland", "GFX8", amd::GPU_Library_HSAIL, VI_ICELAND_M_A0, F_VI_BASE, true, true, FAMILY_VI, false },
{ "VI", "Tonga", "GFX8", amd::GPU_Library_HSAIL, VI_TONGA_P_A0, F_VI_BASE, true, true, FAMILY_VI, false },
UnknownTarget,
UnknownTarget,
{ "CZ", "Carrizo", "GFX8", amd::GPU_Library_HSAIL, CARRIZO_A0, F_VI_BASE, true, true, FAMILY_CZ },
{ "VI", "Fiji", "GFX8", amd::GPU_Library_HSAIL, VI_FIJI_P_A0, F_VI_BASE, true, true, FAMILY_VI },
{ "CZ", "Stoney", "GFX8", amd::GPU_Library_HSAIL, STONEY_A0, F_VI_BASE, true, true, FAMILY_CZ },
{ "VI", "Baffin", "GFX8", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A0, F_VI_BASE, true, false, FAMILY_VI },
{ "VI", "Baffin", "GFX8", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A1, F_VI_BASE, true, true, FAMILY_VI },
{ "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A0, F_VI_BASE, true, false, FAMILY_VI },
{ "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A1, F_VI_BASE, true, true, FAMILY_VI },
{ "CZ", "Carrizo", "GFX8", amd::GPU_Library_HSAIL, CARRIZO_A0, F_VI_BASE, true, true, FAMILY_CZ, false },
{ "VI", "Fiji", "GFX8", amd::GPU_Library_HSAIL, VI_FIJI_P_A0, F_VI_BASE, true, true, FAMILY_VI, false },
{ "CZ", "Stoney", "GFX8", amd::GPU_Library_HSAIL, STONEY_A0, F_VI_BASE, true, true, FAMILY_CZ, false },
{ "VI", "Baffin", "GFX8", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A0, F_VI_BASE, true, false, FAMILY_VI, false },
{ "VI", "Baffin", "GFX8", amd::GPU_Library_HSAIL, VI_BAFFIN_M_A1, F_VI_BASE, true, true, FAMILY_VI, false },
{ "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A0, F_VI_BASE, true, false, FAMILY_VI, false },
{ "VI", "Ellesmere", "GFX8", amd::GPU_Library_HSAIL, VI_ELLESMERE_P_A1, F_VI_BASE, true, true, FAMILY_VI, false },
#ifndef BRAHMA
{ "AI", "gfx900", "GFX9", amd::GPU_Library_HSAIL, AI_GREENLAND_P_A0, F_AI_BASE, true, true, FAMILY_AI },
{ "VI", "gfx804", "GFX8", amd::GPU_Library_HSAIL, VI_LEXA_V_A0, F_VI_BASE, true, true, FAMILY_VI },
{ "RV", "gfx901", "GFX9", amd::GPU_Library_HSAIL, RAVEN_A0, F_AI_BASE, true, true, FAMILY_RV },
{ "AI", "gfx900", "GFX9", amd::GPU_Library_HSAIL, AI_GREENLAND_P_A0, F_AI_BASE, true, true, FAMILY_AI, false },
{ "VI", "gfx804", "GFX8", amd::GPU_Library_HSAIL, VI_LEXA_V_A0, F_VI_BASE, true, true, FAMILY_VI, false },
{ "AI", "gfx901", "GFX9", amd::GPU_Library_HSAIL, AI_GREENLAND_P_A0, F_AI_BASE, true, true, FAMILY_AI, true },
{ "RV", "gfx902", "GFX9", amd::GPU_Library_HSAIL, RAVEN_A0, F_AI_BASE, true, true, FAMILY_RV, false },
{ "RV", "gfx903", "GFX9", amd::GPU_Library_HSAIL, RAVEN_A0, F_AI_BASE, true, true, FAMILY_RV, true },
#else
UnknownTarget,
UnknownTarget,
UnknownTarget,
UnknownTarget,
UnknownTarget,
#endif
InvalidTarget
};
rocclr/runtime/device/pal/paldefs.hpp
+43 -25
Vedi File
@@ -147,37 +147,55 @@ static const AMDDeviceInfo DeviceInfo[] = {
// The GfxIpDeviceInfo table must match with GfxIpLevel enum
// (located in //depot/stg/pal/inc/core/palDevice.h).
static const AMDDeviceInfo GfxIpDeviceInfo[] = {
/* Unknown */ {"unknown", "unknown", 4, 16, 1, 256, 64 * Ki, 32, 000},
/* GFX600 */ {"gfx600", "gfx600", 4, 16, 1, 256, 64 * Ki, 32, 600},
/* GFX700 */ {"gfx700", "gfx700", 4, 16, 1, 256, 64 * Ki, 32, 700},
/* GFX800 */ {"gfx800", "gfx800", 4, 16, 1, 256, 64 * Ki, 32, 800},
/* GFX801 */ {"gfx801", "gfx801", 4, 16, 1, 256, 64 * Ki, 32, 801},
/* GFX900 */ {"gfx900", "gfx900", 4, 16, 1, 256, 64 * Ki, 32, 900},
/* Unknown */ {"unknown", "unknown", 4, 16, 1, 256, 64 * Ki, 32, 000},
/* GFX600 */ {"gfx600", "gfx600", 4, 16, 1, 256, 64 * Ki, 32, 600},
/* GFX700 */ {"gfx700", "gfx700", 4, 16, 1, 256, 64 * Ki, 32, 700},
/* GFX800 */ {"gfx800", "gfx800", 4, 16, 1, 256, 64 * Ki, 32, 800},
/* GFX801 */ {"gfx801", "gfx801", 4, 16, 1, 256, 64 * Ki, 32, 801},
/* GFX900 */ {"gfx900", "gfx900", 4, 16, 1, 256, 64 * Ki, 32, 900},
};
static const AMDDeviceInfo Gfx901DeviceInfo =
/* GFX901 */ {"gfx901", "gfx901", 4, 16, 1, 256, 64 * Ki, 32, 901};
// Ordering as per AsicRevision# in //depot/stg/pal/inc/core/palDevice.h and
// http://confluence.amd.com/pages/viewpage.action?spaceKey=ASLC&title=AMDGPU+Target+Names
static const AMDDeviceInfo Gfx9PlusSubDeviceInfo[] = {
/* Vega10 */{"gfx900", "gfx900", 4, 16, 1, 256, 64 * Ki, 32, 900},
/* Vega10 XNACK */{"gfx901", "gfx901", 4, 16, 1, 256, 64 * Ki, 32, 901},
/* Vega12 */{0},
/* Vega12 XNACK */{0},
/* Vega20 */{0},
/* Vega20 XNACK */{0},
/* Raven */{"gfx902", "gfx902", 4, 16, 1, 256, 64 * Ki, 32, 902},
/* Raven XNACK */{"gfx903", "gfx903", 4, 16, 1, 256, 64 * Ki, 32, 903},
/* Raven2 */{0},
/* Raven2 XNACK */{0},
/* Navi10 */{0},
/* Navi10 XNACK */{0},
};
enum gfx_handle {
gfx700 = 700,
gfx701 = 701,
gfx702 = 702,
gfx800 = 800,
gfx801 = 801,
gfx804 = 804,
gfx810 = 810,
gfx900 = 900,
gfx901 = 901
gfx700 = 700,
gfx701 = 701,
gfx702 = 702,
gfx800 = 800,
gfx801 = 801,
gfx804 = 804,
gfx810 = 810,
gfx900 = 900,
gfx901 = 901,
gfx902 = 902,
gfx903 = 903
};
static const char* Gfx700 = "AMD:AMDGPU:7:0:0";
static const char* Gfx701 = "AMD:AMDGPU:7:0:1";
static const char* Gfx800 = "AMD:AMDGPU:8:0:0";
static const char* Gfx801 = "AMD:AMDGPU:8:0:1";
static const char* Gfx804 = "AMD:AMDGPU:8:0:4";
static const char* Gfx810 = "AMD:AMDGPU:8:1:0";
static const char* Gfx900 = "AMD:AMDGPU:9:0:0";
static const char* Gfx901 = "AMD:AMDGPU:9:0:1";
static const char* Gfx700 = "AMD:AMDGPU:7:0:0";
static const char* Gfx701 = "AMD:AMDGPU:7:0:1";
static const char* Gfx800 = "AMD:AMDGPU:8:0:0";
static const char* Gfx801 = "AMD:AMDGPU:8:0:1";
static const char* Gfx804 = "AMD:AMDGPU:8:0:4";
static const char* Gfx810 = "AMD:AMDGPU:8:1:0";
static const char* Gfx900 = "AMD:AMDGPU:9:0:0";
static const char* Gfx901 = "AMD:AMDGPU:9:0:1";
static const char* Gfx902 = "AMD:AMDGPU:9:0:2";
static const char* Gfx903 = "AMD:AMDGPU:9:0:3";
// Supported OpenCL versions
enum OclVersion { OpenCL10, OpenCL11, OpenCL12, OpenCL20 };
rocclr/runtime/device/pal/paldevice.cpp
+9 -6
Vedi File
@@ -651,16 +651,19 @@ bool Device::create(Pal::IDevice* device) {
ipLevel_ = properties().gfxLevel;
asicRevision_ = properties().revision;
// XNACK flag should be set for PageMigration | IOMMUv2 Support
uint isXNACKSupported = static_cast<uint>(properties_.gpuMemoryProperties.flags.pageMigrationEnabled
|| properties_.gpuMemoryProperties.flags.iommuv2Support);
uint subtarget = isXNACKSupported;
// Update HW info for the device
if ((GPU_ENABLE_PAL == 1) && (properties().revision <= Pal::AsicRevision::Baffin)) {
hwInfo_ = &DeviceInfo[static_cast<uint>(properties().revision)];
} else if (ipLevel_ >= Pal::GfxIpLevel::GfxIp9) {
if (properties().gpuType == Pal::GpuType::Integrated ||
properties_.gpuMemoryProperties.flags.pageMigrationEnabled) {
hwInfo_ = &Gfx901DeviceInfo;
} else {
hwInfo_ = &GfxIpDeviceInfo[static_cast<uint>(ipLevel_)];
}
// For compiler sub targets
subtarget = (static_cast<uint>(asicRevision_) % static_cast<uint>(Pal::AsicRevision::Vega10)) << 1 |
subtarget;
hwInfo_ = &Gfx9PlusSubDeviceInfo[subtarget];
} else {
return false;
}