P4 to Git Change 1270658 by gandryey@gera-w8 on 2016/05/18 17:53:45

SWDEV-86035 - Add PAL backend to OpenCL
	- Fix a crash in the pipe test. Device layer can't use device blit queue directly, but requires a blit manager call, which will perform correct wait for idle sequence.

Affected files ...

... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palblit.cpp#3 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palblit.hpp#3 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/paldevice.cpp#6 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palkernel.cpp#5 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palmemory.cpp#5 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palprogram.cpp#3 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palvirtual.cpp#8 edit
... //depot/stg/opencl/drivers/opencl/tests/ocltst/module/runtime/OCLRTQueue.cpp#2 edit

rocclr/runtime/device/pal/paldevice.cpp

@@ -987,8 +987,8 @@ Device::init()
     acl_error   error;
     compiler_ = aclCompilerInit(&opts, &error);
     if (error != ACL_SUCCESS) {
-            LogError("Error initializing the compiler");
-            return false;
+        LogError("Error initializing the compiler");
+        return false;
     }
 
     size_t size = Pal::GetPlatformSize();
@@ -1210,7 +1210,8 @@ Device::createBuffer(
                 // Pipe initialize in order read_idx, write_idx, end_idx. Refer clk_pipe_t structure.
                 // Init with 3 DWORDS for 32bit addressing and 6 DWORDS for 64bit
                 size_t pipeInit[3] = {0 , 0, owner.asPipe()->getMaxNumPackets()};
-                gpuMemory->writeRawData(*xferQueue_, sizeof(pipeInit), pipeInit, true);
+                static_cast<const KernelBlitManager&>(xferMgr()).writeRawData(
+                    *gpuMemory, sizeof(pipeInit), pipeInit);
             }
             // If memory has direct access from host, then get CPU address
             if (gpuMemory->isHostMemDirectAccess() &&