P4 to Git Change 1376394 by jatang@jatang-opencl-hsa-stg2 on 2017/02/22 11:02:43
SWDEV-99150 - Convert PerfCounter indexing scheme from ORCA to PAL.
PAL is using a different PerfCounter indexing scheme, so need to make the conversion to make CodeXL behave the same.
Affected files ...
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palcounters.cpp#9 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palcounters.hpp#8 edit
[ROCm/clr commit: 1fe7c40048]
This commit is contained in:
foreman
@@ -61,25 +61,30 @@ PalCounterReference::~PalCounterReference()
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}
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}
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uint64_t PalCounterReference::result(int index)
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uint64_t PalCounterReference::result(const std::vector<int>& index)
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{
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if (index < 0) {
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if (index.size() == 0) {
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// These are counters that have no corresponding PalSample created
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return 0;
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}
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if (layout_ != nullptr) {
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assert(index <= static_cast<int>(layout_->sampleCount) && "index not in range");
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const Pal::GlobalSampleLayout& sample = layout_->samples[index];
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if (layout_ == nullptr) {
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return 0;
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}
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uint64_t result = 0;
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for (auto const& i: index) {
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assert(i <= static_cast<int>(layout_->sampleCount) && "index not in range");
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const Pal::GlobalSampleLayout& sample = layout_->samples[i];
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if (sample.dataType == Pal::PerfCounterDataType::Uint32) {
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uint32_t beginVal = *reinterpret_cast<uint32_t*>(reinterpret_cast<char*>(cpuAddr_) + sample.beginValueOffset);
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uint32_t endVal = *reinterpret_cast<uint32_t*>(reinterpret_cast<char*>(cpuAddr_) + sample.endValueOffset);
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return (endVal - beginVal);
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result += (endVal - beginVal);
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}
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else if (sample.dataType == Pal::PerfCounterDataType::Uint64) {
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uint64_t beginVal = *reinterpret_cast<uint64_t*>(reinterpret_cast<char*>(cpuAddr_) + sample.beginValueOffset);
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uint64_t endVal = *reinterpret_cast<uint64_t*>(reinterpret_cast<char*>(cpuAddr_) + sample.endValueOffset);
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return (endVal - beginVal);
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result += (endVal - beginVal);
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}
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else {
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assert(0 && "dataType should be either Uint32 or Uint64");
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@@ -87,7 +92,7 @@ uint64_t PalCounterReference::result(int index)
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}
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}
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return 0;
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return result;
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}
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bool PalCounterReference::finalize()
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@@ -140,304 +145,304 @@ bool PalCounterReference::finalize()
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// Converting from ORCA cmndefs.h to PAL palPerfExperiment.h
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static const
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std::array<std::pair<int, int>, 83> ciBlockIdOrcaToPal =
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std::array<std::tuple<int, int, PCIndexSelect>, 83> ciBlockIdOrcaToPal =
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{{
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{0x0E, 0}, // CB0
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{0x0E, 1}, // CB1
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{0x0E, 2}, // CB2
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{0x0E, 3}, // CB3
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{0x00, 0}, // CPF
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{0x0D, 0}, // DB0
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{0x0D, 1}, // DB1
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{0x0D, 2}, // DB2
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{0x0D, 3}, // DB3
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{0x11, 0}, // GRBM
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{0x12, 0}, // GRBMSE
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{0x03, 0}, // PA_SU
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{0x03, 0}, // PA_SC
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{0x05, 0}, // SPI
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{0x06, 0}, // SQ
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{0x06, 0}, // SQ_ES
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{0x06, 0}, // SQ_GS
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{0x06, 0}, // SQ_VS
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{0x06, 0}, // SQ_PS
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{0x06, 0}, // SQ_LS
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{0x06, 0}, // SQ_HS
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{0x06, 0}, // SQ_CS
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{0x07, 0}, // SX
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{0x08, 0}, // TA0
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{0x08, 1}, // TA1
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{0x08, 2}, // TA2
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{0x08, 3}, // TA3
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{0x08, 4}, // TA4
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{0x08, 5}, // TA5
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{0x08, 6}, // TA6
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{0x08, 7}, // TA7
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{0x08, 8}, // TA8
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{0x08, 9}, // TA9
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{0x08, 0x0a}, // TA10
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{0x0C, 0}, // TCA0
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{0x0C, 1}, // TCA1
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{0x0B, 0}, // TCC0
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{0x0B, 1}, // TCC1
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{0x0B, 2}, // TCC2
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{0x0B, 3}, // TCC3
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{0x0B, 4}, // TCC4
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{0x0B, 5}, // TCC5
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{0x0B, 6}, // TCC6
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{0x0B, 7}, // TCC7
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{0x0B, 8}, // TCC8
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{0x0B, 9}, // TCC9
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{0x0B, 0x0a}, // TCC10
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{0x0B, 0x0b}, // TCC11
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{0x0B, 0x0c}, // TCC12
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{0x0B, 0x0d}, // TCC13
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{0x0B, 0x0e}, // TCC14
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{0x0B, 0x0f}, // TCC15
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{0x09, 0}, // TD0
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{0x09, 1}, // TD1
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{0x09, 2}, // TD2
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{0x09, 3}, // TD3
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{0x09, 4}, // TD4
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{0x09, 5}, // TD5
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{0x09, 6}, // TD6
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{0x09, 7}, // TD7
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{0x09, 8}, // TD8
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{0x09, 9}, // TD9
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{0x09, 0x0a}, // TD10
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{0x0A, 0}, // TCP0
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{0x0A, 1}, // TCP1
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{0x0A, 2}, // TCP2
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{0x0A, 3}, // TCP3
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{0x0A, 4}, // TCP4
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{0x0A, 5}, // TCP5
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{0x0A, 6}, // TCP6
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{0x0A, 7}, // TCP7
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{0x0A, 8}, // TCP8
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{0x0A, 9}, // TCP9
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{0x0A, 0x0a}, // TCP10
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{0x0F, 0}, // GDS
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{0x02, 0}, // VGT
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{0x01, 0}, // IA
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{0x15, 0}, // MC
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{0x10, 0}, // SRBM
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{0x19, 0}, // TCS
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{0x18, 0}, // WD
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{0x16, 0}, // CPG
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{0x17, 0}, // CPC
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{0x0E, 0, PCIndexSelect::ShaderEngineAndInstance}, // CB0
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{0x0E, 1, PCIndexSelect::ShaderEngineAndInstance}, // CB1
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{0x0E, 2, PCIndexSelect::ShaderEngineAndInstance}, // CB2
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{0x0E, 3, PCIndexSelect::ShaderEngineAndInstance}, // CB3
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{0x00, 0, PCIndexSelect::None}, // CPF
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{0x0D, 0, PCIndexSelect::ShaderEngineAndInstance}, // DB0
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{0x0D, 1, PCIndexSelect::ShaderEngineAndInstance}, // DB1
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{0x0D, 2, PCIndexSelect::ShaderEngineAndInstance}, // DB2
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{0x0D, 3, PCIndexSelect::ShaderEngineAndInstance}, // DB3
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{0x11, 0, PCIndexSelect::None}, // GRBM
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{0x12, 0, PCIndexSelect::None}, // GRBMSE
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{0x03, 0, PCIndexSelect::ShaderEngine}, // PA_SU
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{0x03, 0, PCIndexSelect::ShaderEngine}, // PA_SC
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{0x05, 0, PCIndexSelect::ShaderEngine}, // SPI
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{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ
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{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ_ES
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{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ_GS
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{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ_VS
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{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ_PS
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{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ_LS
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{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ_HS
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{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ_CS
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{0x07, 0, PCIndexSelect::ShaderEngine}, // SX
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{0x08, 0, PCIndexSelect::ShaderEngineAndInstance}, // TA0
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{0x08, 1, PCIndexSelect::ShaderEngineAndInstance}, // TA1
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{0x08, 2, PCIndexSelect::ShaderEngineAndInstance}, // TA2
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{0x08, 3, PCIndexSelect::ShaderEngineAndInstance}, // TA3
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{0x08, 4, PCIndexSelect::ShaderEngineAndInstance}, // TA4
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{0x08, 5, PCIndexSelect::ShaderEngineAndInstance}, // TA5
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{0x08, 6, PCIndexSelect::ShaderEngineAndInstance}, // TA6
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{0x08, 7, PCIndexSelect::ShaderEngineAndInstance}, // TA7
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{0x08, 8, PCIndexSelect::ShaderEngineAndInstance}, // TA8
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{0x08, 9, PCIndexSelect::ShaderEngineAndInstance}, // TA9
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{0x08, 0x0a, PCIndexSelect::ShaderEngineAndInstance}, // TA10
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{0x0C, 0, PCIndexSelect::Instance}, // TCA0
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{0x0C, 1, PCIndexSelect::Instance}, // TCA1
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{0x0B, 0, PCIndexSelect::Instance}, // TCC0
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{0x0B, 1, PCIndexSelect::Instance}, // TCC1
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{0x0B, 2, PCIndexSelect::Instance}, // TCC2
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{0x0B, 3, PCIndexSelect::Instance}, // TCC3
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{0x0B, 4, PCIndexSelect::Instance}, // TCC4
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{0x0B, 5, PCIndexSelect::Instance}, // TCC5
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{0x0B, 6, PCIndexSelect::Instance}, // TCC6
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{0x0B, 7, PCIndexSelect::Instance}, // TCC7
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{0x0B, 8, PCIndexSelect::Instance}, // TCC8
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{0x0B, 9, PCIndexSelect::Instance}, // TCC9
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{0x0B, 0x0a, PCIndexSelect::Instance}, // TCC10
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{0x0B, 0x0b, PCIndexSelect::Instance}, // TCC11
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{0x0B, 0x0c, PCIndexSelect::Instance}, // TCC12
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{0x0B, 0x0d, PCIndexSelect::Instance}, // TCC13
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{0x0B, 0x0e, PCIndexSelect::Instance}, // TCC14
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{0x0B, 0x0f, PCIndexSelect::Instance}, // TCC15
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{0x09, 0, PCIndexSelect::ShaderEngineAndInstance}, // TD0
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{0x09, 1, PCIndexSelect::ShaderEngineAndInstance}, // TD1
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{0x09, 2, PCIndexSelect::ShaderEngineAndInstance}, // TD2
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{0x09, 3, PCIndexSelect::ShaderEngineAndInstance}, // TD3
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{0x09, 4, PCIndexSelect::ShaderEngineAndInstance}, // TD4
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{0x09, 5, PCIndexSelect::ShaderEngineAndInstance}, // TD5
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{0x09, 6, PCIndexSelect::ShaderEngineAndInstance}, // TD6
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{0x09, 7, PCIndexSelect::ShaderEngineAndInstance}, // TD7
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{0x09, 8, PCIndexSelect::ShaderEngineAndInstance}, // TD8
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{0x09, 9, PCIndexSelect::ShaderEngineAndInstance}, // TD9
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{0x09, 0x0a, PCIndexSelect::ShaderEngineAndInstance}, // TD10
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{0x0A, 0, PCIndexSelect::ShaderEngineAndInstance}, // TCP0
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{0x0A, 1, PCIndexSelect::ShaderEngineAndInstance}, // TCP1
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{0x0A, 2, PCIndexSelect::ShaderEngineAndInstance}, // TCP2
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{0x0A, 3, PCIndexSelect::ShaderEngineAndInstance}, // TCP3
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{0x0A, 4, PCIndexSelect::ShaderEngineAndInstance}, // TCP4
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{0x0A, 5, PCIndexSelect::ShaderEngineAndInstance}, // TCP5
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{0x0A, 6, PCIndexSelect::ShaderEngineAndInstance}, // TCP6
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{0x0A, 7, PCIndexSelect::ShaderEngineAndInstance}, // TCP7
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{0x0A, 8, PCIndexSelect::ShaderEngineAndInstance}, // TCP8
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{0x0A, 9, PCIndexSelect::ShaderEngineAndInstance}, // TCP9
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{0x0A, 0x0a, PCIndexSelect::ShaderEngineAndInstance}, // TCP10
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{0x0F, 0, PCIndexSelect::None}, // GDS
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{0x02, 0, PCIndexSelect::ShaderEngine}, // VGT
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{0x01, 0, PCIndexSelect::ShaderEngine}, // IA
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{0x15, 0, PCIndexSelect::None}, // MC
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{0x10, 0, PCIndexSelect::None}, // SRBM
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{0x19, 0, PCIndexSelect::None}, // TCS
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{0x18, 0, PCIndexSelect::None}, // WD
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{0x16, 0, PCIndexSelect::None}, // CPG
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{0x17, 0, PCIndexSelect::None}, // CPC
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}};
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static const
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std::array<std::pair<int, int>, 97> viBlockIdOrcaToPal =
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std::array<std::tuple<int, int, PCIndexSelect>, 97> viBlockIdOrcaToPal =
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{{
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{0x0E, 0}, // CB0
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{0x0E, 1}, // CB1
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{0x0E, 2}, // CB2
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{0x0E, 3}, // CB3
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{0x00, 0}, // CPF
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{0x0D, 0}, // DB0
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{0x0D, 1}, // DB1
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{0x0D, 2}, // DB2
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{0x0D, 3}, // DB3
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{0x11, 0}, // GRBM
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{0x12, 0}, // GRBMSE
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{0x03, 0}, // PA_SU
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{0x03, 0}, // PA_SC
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{0x05, 0}, // SPI
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{0x06, 0}, // SQ
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{0x06, 0}, // SQ_ES
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{0x06, 0}, // SQ_GS
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{0x06, 0}, // SQ_VS
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{0x06, 0}, // SQ_PS
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{0x06, 0}, // SQ_LS
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{0x06, 0}, // SQ_HS
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{0x06, 0}, // SQ_CS
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{0x07, 0}, // SX
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{0x08, 0}, // TA0
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{0x08, 1}, // TA1
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{0x08, 2}, // TA2
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{0x08, 3}, // TA3
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{0x08, 4}, // TA4
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{0x08, 5}, // TA5
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{0x08, 6}, // TA6
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{0x08, 7}, // TA7
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{0x08, 8}, // TA8
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{0x08, 9}, // TA9
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{0x08, 0x0a}, // TA10
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{0x08, 0x0b}, // TA11
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{0x08, 0x0c}, // TA12
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{0x08, 0x0d}, // TA13
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{0x08, 0x0e}, // TA14
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{0x08, 0x0f}, // TA15
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{0x0C, 0}, // TCA0
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{0x0C, 1}, // TCA1
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{0x0B, 0}, // TCC0
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{0x0B, 1}, // TCC1
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{0x0B, 2}, // TCC2
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{0x0B, 3}, // TCC3
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{0x0B, 4}, // TCC4
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{0x0B, 5}, // TCC5
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{0x0B, 6}, // TCC6
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{0x0B, 7}, // TCC7
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{0x0B, 8}, // TCC8
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{0x0B, 9}, // TCC9
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{0x0B, 0x0a}, // TCC10
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{0x0B, 0x0b}, // TCC11
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{0x0B, 0x0c}, // TCC12
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{0x0B, 0x0d}, // TCC13
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{0x0B, 0x0e}, // TCC14
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{0x0B, 0x0f}, // TCC15
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{0x09, 0}, // TD0
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{0x09, 1}, // TD1
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{0x09, 2}, // TD2
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{0x09, 3}, // TD3
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{0x09, 4}, // TD4
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{0x09, 5}, // TD5
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{0x09, 6}, // TD6
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{0x09, 7}, // TD7
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{0x09, 8}, // TD8
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{0x09, 9}, // TD9
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{0x09, 0x0a}, // TD10
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{0x09, 0x0b}, // TD11
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{0x09, 0x0c}, // TD12
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{0x09, 0x0d}, // TD13
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{0x09, 0x0e}, // TD14
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{0x09, 0x0f}, // TD15
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{0x0A, 0}, // TCP0
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{0x0A, 1}, // TCP1
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{0x0A, 2}, // TCP2
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{0x0A, 3}, // TCP3
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{0x0A, 4}, // TCP4
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{0x0A, 5}, // TCP5
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{0x0A, 6}, // TCP6
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{0x0A, 7}, // TCP7
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{0x0A, 8}, // TCP8
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{0x0A, 9}, // TCP9
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{0x0A, 0x0a}, // TCP10
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{0x0A, 0x0b}, // TCP11
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{0x0A, 0x0c}, // TCP12
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{0x0A, 0x0d}, // TCP13
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{0x0A, 0x0e}, // TCP14
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{0x0A, 0x0f}, // TCP15
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{0x0F, 0}, // GDS
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{0x02, 0}, // VGT
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{0x01, 0}, // IA
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{0x15, 0}, // MC
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{0x10, 0}, // SRBM
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{0x18, 0}, // WD
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{0x16, 0}, // CPG
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{0x17, 0}, // CPC
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{0x0E, 0, PCIndexSelect::ShaderEngineAndInstance}, // CB0
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{0x0E, 1, PCIndexSelect::ShaderEngineAndInstance}, // CB1
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{0x0E, 2, PCIndexSelect::ShaderEngineAndInstance}, // CB2
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{0x0E, 3, PCIndexSelect::ShaderEngineAndInstance}, // CB3
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{0x00, 0, PCIndexSelect::None}, // CPF
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{0x0D, 0, PCIndexSelect::ShaderEngineAndInstance}, // DB0
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{0x0D, 1, PCIndexSelect::ShaderEngineAndInstance}, // DB1
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{0x0D, 2, PCIndexSelect::ShaderEngineAndInstance}, // DB2
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{0x0D, 3, PCIndexSelect::ShaderEngineAndInstance}, // DB3
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{0x11, 0, PCIndexSelect::None}, // GRBM
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{0x12, 0, PCIndexSelect::None}, // GRBMSE
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{0x03, 0, PCIndexSelect::ShaderEngine}, // PA_SU
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{0x03, 0, PCIndexSelect::ShaderEngine}, // PA_SC
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{0x05, 0, PCIndexSelect::ShaderEngine}, // SPI
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{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ
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{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ_ES
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{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ_GS
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{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ_VS
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{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ_PS
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{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ_LS
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{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ_HS
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{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ_CS
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{0x07, 0, PCIndexSelect::ShaderEngine}, // SX
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{0x08, 0, PCIndexSelect::ShaderEngineAndInstance}, // TA0
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{0x08, 1, PCIndexSelect::ShaderEngineAndInstance}, // TA1
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{0x08, 2, PCIndexSelect::ShaderEngineAndInstance}, // TA2
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{0x08, 3, PCIndexSelect::ShaderEngineAndInstance}, // TA3
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{0x08, 4, PCIndexSelect::ShaderEngineAndInstance}, // TA4
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{0x08, 5, PCIndexSelect::ShaderEngineAndInstance}, // TA5
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{0x08, 6, PCIndexSelect::ShaderEngineAndInstance}, // TA6
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{0x08, 7, PCIndexSelect::ShaderEngineAndInstance}, // TA7
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{0x08, 8, PCIndexSelect::ShaderEngineAndInstance}, // TA8
|
||||
{0x08, 9, PCIndexSelect::ShaderEngineAndInstance}, // TA9
|
||||
{0x08, 0x0a, PCIndexSelect::ShaderEngineAndInstance}, // TA10
|
||||
{0x08, 0x0b, PCIndexSelect::ShaderEngineAndInstance}, // TA11
|
||||
{0x08, 0x0c, PCIndexSelect::ShaderEngineAndInstance}, // TA12
|
||||
{0x08, 0x0d, PCIndexSelect::ShaderEngineAndInstance}, // TA13
|
||||
{0x08, 0x0e, PCIndexSelect::ShaderEngineAndInstance}, // TA14
|
||||
{0x08, 0x0f, PCIndexSelect::ShaderEngineAndInstance}, // TA15
|
||||
{0x0C, 0, PCIndexSelect::Instance}, // TCA0
|
||||
{0x0C, 1, PCIndexSelect::Instance}, // TCA1
|
||||
{0x0B, 0, PCIndexSelect::Instance}, // TCC0
|
||||
{0x0B, 1, PCIndexSelect::Instance}, // TCC1
|
||||
{0x0B, 2, PCIndexSelect::Instance}, // TCC2
|
||||
{0x0B, 3, PCIndexSelect::Instance}, // TCC3
|
||||
{0x0B, 4, PCIndexSelect::Instance}, // TCC4
|
||||
{0x0B, 5, PCIndexSelect::Instance}, // TCC5
|
||||
{0x0B, 6, PCIndexSelect::Instance}, // TCC6
|
||||
{0x0B, 7, PCIndexSelect::Instance}, // TCC7
|
||||
{0x0B, 8, PCIndexSelect::Instance}, // TCC8
|
||||
{0x0B, 9, PCIndexSelect::Instance}, // TCC9
|
||||
{0x0B, 0x0a, PCIndexSelect::Instance}, // TCC10
|
||||
{0x0B, 0x0b, PCIndexSelect::Instance}, // TCC11
|
||||
{0x0B, 0x0c, PCIndexSelect::Instance}, // TCC12
|
||||
{0x0B, 0x0d, PCIndexSelect::Instance}, // TCC13
|
||||
{0x0B, 0x0e, PCIndexSelect::Instance}, // TCC14
|
||||
{0x0B, 0x0f, PCIndexSelect::Instance}, // TCC15
|
||||
{0x09, 0, PCIndexSelect::ShaderEngineAndInstance}, // TD0
|
||||
{0x09, 1, PCIndexSelect::ShaderEngineAndInstance}, // TD1
|
||||
{0x09, 2, PCIndexSelect::ShaderEngineAndInstance}, // TD2
|
||||
{0x09, 3, PCIndexSelect::ShaderEngineAndInstance}, // TD3
|
||||
{0x09, 4, PCIndexSelect::ShaderEngineAndInstance}, // TD4
|
||||
{0x09, 5, PCIndexSelect::ShaderEngineAndInstance}, // TD5
|
||||
{0x09, 6, PCIndexSelect::ShaderEngineAndInstance}, // TD6
|
||||
{0x09, 7, PCIndexSelect::ShaderEngineAndInstance}, // TD7
|
||||
{0x09, 8, PCIndexSelect::ShaderEngineAndInstance}, // TD8
|
||||
{0x09, 9, PCIndexSelect::ShaderEngineAndInstance}, // TD9
|
||||
{0x09, 0x0a, PCIndexSelect::ShaderEngineAndInstance}, // TD10
|
||||
{0x09, 0x0b, PCIndexSelect::ShaderEngineAndInstance}, // TD11
|
||||
{0x09, 0x0c, PCIndexSelect::ShaderEngineAndInstance}, // TD12
|
||||
{0x09, 0x0d, PCIndexSelect::ShaderEngineAndInstance}, // TD13
|
||||
{0x09, 0x0e, PCIndexSelect::ShaderEngineAndInstance}, // TD14
|
||||
{0x09, 0x0f, PCIndexSelect::ShaderEngineAndInstance}, // TD15
|
||||
{0x0A, 0, PCIndexSelect::ShaderEngineAndInstance}, // TCP0
|
||||
{0x0A, 1, PCIndexSelect::ShaderEngineAndInstance}, // TCP1
|
||||
{0x0A, 2, PCIndexSelect::ShaderEngineAndInstance}, // TCP2
|
||||
{0x0A, 3, PCIndexSelect::ShaderEngineAndInstance}, // TCP3
|
||||
{0x0A, 4, PCIndexSelect::ShaderEngineAndInstance}, // TCP4
|
||||
{0x0A, 5, PCIndexSelect::ShaderEngineAndInstance}, // TCP5
|
||||
{0x0A, 6, PCIndexSelect::ShaderEngineAndInstance}, // TCP6
|
||||
{0x0A, 7, PCIndexSelect::ShaderEngineAndInstance}, // TCP7
|
||||
{0x0A, 8, PCIndexSelect::ShaderEngineAndInstance}, // TCP8
|
||||
{0x0A, 9, PCIndexSelect::ShaderEngineAndInstance}, // TCP9
|
||||
{0x0A, 0x0a, PCIndexSelect::ShaderEngineAndInstance}, // TCP10
|
||||
{0x0A, 0x0b, PCIndexSelect::ShaderEngineAndInstance}, // TCP11
|
||||
{0x0A, 0x0c, PCIndexSelect::ShaderEngineAndInstance}, // TCP12
|
||||
{0x0A, 0x0d, PCIndexSelect::ShaderEngineAndInstance}, // TCP13
|
||||
{0x0A, 0x0e, PCIndexSelect::ShaderEngineAndInstance}, // TCP14
|
||||
{0x0A, 0x0f, PCIndexSelect::ShaderEngineAndInstance}, // TCP15
|
||||
{0x0F, 0, PCIndexSelect::None}, // GDS
|
||||
{0x02, 0, PCIndexSelect::ShaderEngine}, // VGT
|
||||
{0x01, 0, PCIndexSelect::ShaderEngine}, // IA
|
||||
{0x15, 0, PCIndexSelect::None}, // MC
|
||||
{0x10, 0, PCIndexSelect::None}, // SRBM
|
||||
{0x18, 0, PCIndexSelect::None}, // WD
|
||||
{0x16, 0, PCIndexSelect::None}, // CPG
|
||||
{0x17, 0, PCIndexSelect::None}, // CPC
|
||||
}};
|
||||
|
||||
// The number of counters per block has been increased for gfx9 but this table may not reflect all of them
|
||||
// as compute may not use all of them.
|
||||
static const
|
||||
std::array<std::pair<int, int>, 104> gfx9BlockIdPal =
|
||||
std::array<std::tuple<int, int, PCIndexSelect>, 104> gfx9BlockIdPal =
|
||||
{{
|
||||
{ 0x0E, 0 }, // CB0
|
||||
{ 0x0E, 1 }, // CB1
|
||||
{ 0x0E, 2 }, // CB2
|
||||
{ 0x0E, 3 }, // CB3
|
||||
{ 0x00, 0 }, // CPF0
|
||||
{ 0x00, 1 }, // CPF1
|
||||
{ 0x0D, 0 }, // DB0
|
||||
{ 0x0D, 1 }, // DB1
|
||||
{ 0x0D, 2 }, // DB2
|
||||
{ 0x0D, 3 }, // DB3
|
||||
{ 0x11, 0 }, // GRBM0
|
||||
{ 0x11, 1 }, // GRBM1
|
||||
{ 0x12, 0 }, // GRBMSE0
|
||||
{ 0x03, 0 }, // PA_SU
|
||||
{ 0x03, 0 }, // PA_SC
|
||||
{ 0x05, 0 }, // SPI
|
||||
{ 0x06, 0 }, // SQ0
|
||||
{ 0x06, 1 }, // SQ1
|
||||
{ 0x06, 0 }, // SQ_ES
|
||||
{ 0x06, 0 }, // SQ_GS
|
||||
{ 0x06, 0 }, // SQ_VS
|
||||
{ 0x06, 0 }, // SQ_PS
|
||||
{ 0x06, 0 }, // SQ_LS
|
||||
{ 0x06, 0 }, // SQ_HS
|
||||
{ 0x06, 0 }, // SQ_CS0
|
||||
{ 0x06, 1 }, // SQ_CS1
|
||||
{ 0x07, 0 }, // SX
|
||||
{ 0x08, 0 }, // TA0
|
||||
{ 0x08, 1 }, // TA1
|
||||
{ 0x08, 2 }, // TA2
|
||||
{ 0x08, 3 }, // TA3
|
||||
{ 0x08, 4 }, // TA4
|
||||
{ 0x08, 5 }, // TA5
|
||||
{ 0x08, 6 }, // TA6
|
||||
{ 0x08, 7 }, // TA7
|
||||
{ 0x08, 8 }, // TA8
|
||||
{ 0x08, 9 }, // TA9
|
||||
{ 0x08, 0x0a }, // TA10
|
||||
{ 0x08, 0x0b }, // TA11
|
||||
{ 0x08, 0x0c }, // TA12
|
||||
{ 0x08, 0x0d }, // TA13
|
||||
{ 0x08, 0x0e }, // TA14
|
||||
{ 0x08, 0x0f }, // TA15
|
||||
{ 0x0C, 0 }, // TCA0
|
||||
{ 0x0C, 1 }, // TCA1
|
||||
{ 0x0B, 0 }, // TCC0
|
||||
{ 0x0B, 1 }, // TCC1
|
||||
{ 0x0B, 2 }, // TCC2
|
||||
{ 0x0B, 3 }, // TCC3
|
||||
{ 0x0B, 4 }, // TCC4
|
||||
{ 0x0B, 5 }, // TCC5
|
||||
{ 0x0B, 6 }, // TCC6
|
||||
{ 0x0B, 7 }, // TCC7
|
||||
{ 0x0B, 8 }, // TCC8
|
||||
{ 0x0B, 9 }, // TCC9
|
||||
{ 0x0B, 0x0a }, // TCC10
|
||||
{ 0x0B, 0x0b }, // TCC11
|
||||
{ 0x0B, 0x0c }, // TCC12
|
||||
{ 0x0B, 0x0d }, // TCC13
|
||||
{ 0x0B, 0x0e }, // TCC14
|
||||
{ 0x0B, 0x0f }, // TCC15
|
||||
{ 0x09, 0 }, // TD0
|
||||
{ 0x09, 1 }, // TD1
|
||||
{ 0x09, 2 }, // TD2
|
||||
{ 0x09, 3 }, // TD3
|
||||
{ 0x09, 4 }, // TD4
|
||||
{ 0x09, 5 }, // TD5
|
||||
{ 0x09, 6 }, // TD6
|
||||
{ 0x09, 7 }, // TD7
|
||||
{ 0x09, 8 }, // TD8
|
||||
{ 0x09, 9 }, // TD9
|
||||
{ 0x09, 0x0a }, // TD10
|
||||
{ 0x09, 0x0b }, // TD11
|
||||
{ 0x09, 0x0c }, // TD12
|
||||
{ 0x09, 0x0d }, // TD13
|
||||
{ 0x09, 0x0e }, // TD14
|
||||
{ 0x09, 0x0f }, // TD15
|
||||
{ 0x0A, 0 }, // TCP0
|
||||
{ 0x0A, 1 }, // TCP1
|
||||
{ 0x0A, 2 }, // TCP2
|
||||
{ 0x0A, 3 }, // TCP3
|
||||
{ 0x0A, 4 }, // TCP4
|
||||
{ 0x0A, 5 }, // TCP5
|
||||
{ 0x0A, 6 }, // TCP6
|
||||
{ 0x0A, 7 }, // TCP7
|
||||
{ 0x0A, 8 }, // TCP8
|
||||
{ 0x0A, 9 }, // TCP9
|
||||
{ 0x0A, 0x0a }, // TCP10
|
||||
{ 0x0A, 0x0b }, // TCP11
|
||||
{ 0x0A, 0x0c }, // TCP12
|
||||
{ 0x0A, 0x0d }, // TCP13
|
||||
{ 0x0A, 0x0e }, // TCP14
|
||||
{ 0x0A, 0x0f }, // TCP15
|
||||
{ 0x0F, 0 }, // GDS0
|
||||
{ 0x0F, 1 }, // GDS1
|
||||
{ 0x02, 0 }, // VGT
|
||||
{ 0x01, 0 }, // IA
|
||||
{ 0x15, 0 }, // MC
|
||||
{ 0x10, 0 }, // SRBM
|
||||
{ 0x18, 0 }, // WD
|
||||
{ 0x16, 0 }, // CPG0
|
||||
{ 0x16, 1 }, // CPG1
|
||||
{ 0x17, 0 }, // CPC0
|
||||
{ 0x17, 1 }, // CPC1
|
||||
{0x0E, 0, PCIndexSelect::ShaderEngineAndInstance}, // CB0
|
||||
{0x0E, 1, PCIndexSelect::ShaderEngineAndInstance}, // CB1
|
||||
{0x0E, 2, PCIndexSelect::ShaderEngineAndInstance}, // CB2
|
||||
{0x0E, 3, PCIndexSelect::ShaderEngineAndInstance}, // CB3
|
||||
{0x00, 0, PCIndexSelect::Instance}, // CPF0
|
||||
{0x00, 1, PCIndexSelect::Instance}, // CPF1
|
||||
{0x0D, 0, PCIndexSelect::ShaderEngineAndInstance}, // DB0
|
||||
{0x0D, 1, PCIndexSelect::ShaderEngineAndInstance}, // DB1
|
||||
{0x0D, 2, PCIndexSelect::ShaderEngineAndInstance}, // DB2
|
||||
{0x0D, 3, PCIndexSelect::ShaderEngineAndInstance}, // DB3
|
||||
{0x11, 0, PCIndexSelect::Instance}, // GRBM0
|
||||
{0x11, 1, PCIndexSelect::Instance}, // GRBM1
|
||||
{0x12, 0, PCIndexSelect::Instance}, // GRBMSE0
|
||||
{0x03, 0, PCIndexSelect::ShaderEngine}, // PA_SU
|
||||
{0x03, 0, PCIndexSelect::ShaderEngine}, // PA_SC
|
||||
{0x05, 0, PCIndexSelect::ShaderEngine}, // SPI
|
||||
{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ0
|
||||
{0x06, 1, PCIndexSelect::ShaderEngine}, // SQ1
|
||||
{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ_ES
|
||||
{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ_GS
|
||||
{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ_VS
|
||||
{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ_PS
|
||||
{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ_LS
|
||||
{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ_HS
|
||||
{0x06, 0, PCIndexSelect::ShaderEngine}, // SQ_CS0
|
||||
{0x06, 1, PCIndexSelect::ShaderEngine}, // SQ_CS1
|
||||
{0x07, 0, PCIndexSelect::ShaderEngine}, // SX
|
||||
{0x08, 0, PCIndexSelect::ShaderEngineAndInstance}, // TA0
|
||||
{0x08, 1, PCIndexSelect::ShaderEngineAndInstance}, // TA1
|
||||
{0x08, 2, PCIndexSelect::ShaderEngineAndInstance}, // TA2
|
||||
{0x08, 3, PCIndexSelect::ShaderEngineAndInstance}, // TA3
|
||||
{0x08, 4, PCIndexSelect::ShaderEngineAndInstance}, // TA4
|
||||
{0x08, 5, PCIndexSelect::ShaderEngineAndInstance}, // TA5
|
||||
{0x08, 6, PCIndexSelect::ShaderEngineAndInstance}, // TA6
|
||||
{0x08, 7, PCIndexSelect::ShaderEngineAndInstance}, // TA7
|
||||
{0x08, 8, PCIndexSelect::ShaderEngineAndInstance}, // TA8
|
||||
{0x08, 9, PCIndexSelect::ShaderEngineAndInstance}, // TA9
|
||||
{0x08, 0x0a, PCIndexSelect::ShaderEngineAndInstance}, // TA10
|
||||
{0x08, 0x0b, PCIndexSelect::ShaderEngineAndInstance}, // TA11
|
||||
{0x08, 0x0c, PCIndexSelect::ShaderEngineAndInstance}, // TA12
|
||||
{0x08, 0x0d, PCIndexSelect::ShaderEngineAndInstance}, // TA13
|
||||
{0x08, 0x0e, PCIndexSelect::ShaderEngineAndInstance}, // TA14
|
||||
{0x08, 0x0f, PCIndexSelect::ShaderEngineAndInstance}, // TA15
|
||||
{0x0C, 0, PCIndexSelect::Instance}, // TCA0
|
||||
{0x0C, 1, PCIndexSelect::Instance}, // TCA1
|
||||
{0x0B, 0, PCIndexSelect::Instance}, // TCC0
|
||||
{0x0B, 1, PCIndexSelect::Instance}, // TCC1
|
||||
{0x0B, 2, PCIndexSelect::Instance}, // TCC2
|
||||
{0x0B, 3, PCIndexSelect::Instance}, // TCC3
|
||||
{0x0B, 4, PCIndexSelect::Instance}, // TCC4
|
||||
{0x0B, 5, PCIndexSelect::Instance}, // TCC5
|
||||
{0x0B, 6, PCIndexSelect::Instance}, // TCC6
|
||||
{0x0B, 7, PCIndexSelect::Instance}, // TCC7
|
||||
{0x0B, 8, PCIndexSelect::Instance}, // TCC8
|
||||
{0x0B, 9, PCIndexSelect::Instance}, // TCC9
|
||||
{0x0B, 0x0a, PCIndexSelect::Instance}, // TCC10
|
||||
{0x0B, 0x0b, PCIndexSelect::Instance}, // TCC11
|
||||
{0x0B, 0x0c, PCIndexSelect::Instance}, // TCC12
|
||||
{0x0B, 0x0d, PCIndexSelect::Instance}, // TCC13
|
||||
{0x0B, 0x0e, PCIndexSelect::Instance}, // TCC14
|
||||
{0x0B, 0x0f, PCIndexSelect::Instance}, // TCC15
|
||||
{0x09, 0, PCIndexSelect::ShaderEngineAndInstance}, // TD0
|
||||
{0x09, 1, PCIndexSelect::ShaderEngineAndInstance}, // TD1
|
||||
{0x09, 2, PCIndexSelect::ShaderEngineAndInstance}, // TD2
|
||||
{0x09, 3, PCIndexSelect::ShaderEngineAndInstance}, // TD3
|
||||
{0x09, 4, PCIndexSelect::ShaderEngineAndInstance}, // TD4
|
||||
{0x09, 5, PCIndexSelect::ShaderEngineAndInstance}, // TD5
|
||||
{0x09, 6, PCIndexSelect::ShaderEngineAndInstance}, // TD6
|
||||
{0x09, 7, PCIndexSelect::ShaderEngineAndInstance}, // TD7
|
||||
{0x09, 8, PCIndexSelect::ShaderEngineAndInstance}, // TD8
|
||||
{0x09, 9, PCIndexSelect::ShaderEngineAndInstance}, // TD9
|
||||
{0x09, 0x0a, PCIndexSelect::ShaderEngineAndInstance}, // TD10
|
||||
{0x09, 0x0b, PCIndexSelect::ShaderEngineAndInstance}, // TD11
|
||||
{0x09, 0x0c, PCIndexSelect::ShaderEngineAndInstance}, // TD12
|
||||
{0x09, 0x0d, PCIndexSelect::ShaderEngineAndInstance}, // TD13
|
||||
{0x09, 0x0e, PCIndexSelect::ShaderEngineAndInstance}, // TD14
|
||||
{0x09, 0x0f, PCIndexSelect::ShaderEngineAndInstance}, // TD15
|
||||
{0x0A, 0, PCIndexSelect::ShaderEngineAndInstance}, // TCP0
|
||||
{0x0A, 1, PCIndexSelect::ShaderEngineAndInstance}, // TCP1
|
||||
{0x0A, 2, PCIndexSelect::ShaderEngineAndInstance}, // TCP2
|
||||
{0x0A, 3, PCIndexSelect::ShaderEngineAndInstance}, // TCP3
|
||||
{0x0A, 4, PCIndexSelect::ShaderEngineAndInstance}, // TCP4
|
||||
{0x0A, 5, PCIndexSelect::ShaderEngineAndInstance}, // TCP5
|
||||
{0x0A, 6, PCIndexSelect::ShaderEngineAndInstance}, // TCP6
|
||||
{0x0A, 7, PCIndexSelect::ShaderEngineAndInstance}, // TCP7
|
||||
{0x0A, 8, PCIndexSelect::ShaderEngineAndInstance}, // TCP8
|
||||
{0x0A, 9, PCIndexSelect::ShaderEngineAndInstance}, // TCP9
|
||||
{0x0A, 0x0a, PCIndexSelect::ShaderEngineAndInstance}, // TCP10
|
||||
{0x0A, 0x0b, PCIndexSelect::ShaderEngineAndInstance}, // TCP11
|
||||
{0x0A, 0x0c, PCIndexSelect::ShaderEngineAndInstance}, // TCP12
|
||||
{0x0A, 0x0d, PCIndexSelect::ShaderEngineAndInstance}, // TCP13
|
||||
{0x0A, 0x0e, PCIndexSelect::ShaderEngineAndInstance}, // TCP14
|
||||
{0x0A, 0x0f, PCIndexSelect::ShaderEngineAndInstance}, // TCP15
|
||||
{0x0F, 0, PCIndexSelect::Instance}, // GDS0
|
||||
{0x0F, 1, PCIndexSelect::Instance}, // GDS1
|
||||
{0x02, 0, PCIndexSelect::ShaderEngine}, // VGT
|
||||
{0x01, 0, PCIndexSelect::ShaderEngine}, // IA
|
||||
{0x15, 0, PCIndexSelect::None}, // MC
|
||||
{0x10, 0, PCIndexSelect::None}, // SRBM
|
||||
{0x18, 0, PCIndexSelect::None}, // WD
|
||||
{0x16, 0, PCIndexSelect::Instance}, // CPG0
|
||||
{0x16, 1, PCIndexSelect::Instance}, // CPG1
|
||||
{0x17, 0, PCIndexSelect::Instance}, // CPC0
|
||||
{0x17, 1, PCIndexSelect::Instance}, // CPC1
|
||||
}};
|
||||
|
||||
void PerfCounter::convertInfo()
|
||||
@@ -448,6 +453,7 @@ void PerfCounter::convertInfo()
|
||||
auto p = ciBlockIdOrcaToPal[info_.blockIndex_];
|
||||
info_.blockIndex_ = std::get<0>(p);
|
||||
info_.counterIndex_ = std::get<1>(p);
|
||||
info_.indexSelect_ = std::get<2>(p);
|
||||
}
|
||||
break;
|
||||
case Pal::GfxIpLevel::GfxIp8:
|
||||
@@ -455,6 +461,7 @@ void PerfCounter::convertInfo()
|
||||
auto p = viBlockIdOrcaToPal[info_.blockIndex_];
|
||||
info_.blockIndex_ = std::get<0>(p);
|
||||
info_.counterIndex_ = std::get<1>(p);
|
||||
info_.indexSelect_ = std::get<2>(p);
|
||||
}
|
||||
break;
|
||||
case Pal::GfxIpLevel::GfxIp9:
|
||||
@@ -462,6 +469,7 @@ void PerfCounter::convertInfo()
|
||||
auto p = gfx9BlockIdPal[info_.blockIndex_];
|
||||
info_.blockIndex_ = std::get<0>(p);
|
||||
info_.counterIndex_ = std::get<1>(p);
|
||||
info_.indexSelect_ = std::get<2>(p);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
@@ -489,18 +497,56 @@ PerfCounter::create()
|
||||
Pal::PerfCounterInfo counterInfo = {};
|
||||
counterInfo.counterType = Pal::PerfCounterType::Global;
|
||||
counterInfo.block = static_cast<Pal::GpuBlock>(info_.blockIndex_);
|
||||
counterInfo.instance = info_.counterIndex_;
|
||||
counterInfo.eventId = info_.eventIndex_;
|
||||
Pal::Result result = iPerf()->AddCounter(counterInfo);
|
||||
if (result == Pal::Result::Success) {
|
||||
index_ = palRef_->getPalCounterIndex();
|
||||
return true;
|
||||
}
|
||||
else {
|
||||
// Get here when there's no HW PerfCounter matching the counterInfo
|
||||
index_ = -1;
|
||||
|
||||
Pal::PerfExperimentProperties perfExpProps;
|
||||
Pal::Result result;
|
||||
result = dev().iDev()->GetPerfExperimentProperties(&perfExpProps);
|
||||
if (result != Pal::Result::Success) {
|
||||
return false;
|
||||
}
|
||||
|
||||
const auto& blockProps = perfExpProps.blocks[static_cast<uint32_t>(counterInfo.block)];
|
||||
uint32_t counter_start, counter_step;
|
||||
|
||||
switch (info_.indexSelect_) {
|
||||
case PCIndexSelect::ShaderEngine:
|
||||
case PCIndexSelect::None:
|
||||
counter_start = 0;
|
||||
counter_step = 1;
|
||||
break;
|
||||
|
||||
case PCIndexSelect::ShaderEngineAndInstance:
|
||||
if (info_.counterIndex_ >=
|
||||
dev().properties().gfxipProperties.shaderCore.maxCusPerShaderArray) {
|
||||
return true;
|
||||
}
|
||||
counter_start = info_.counterIndex_;
|
||||
counter_step = dev().properties().gfxipProperties.shaderCore.maxCusPerShaderArray;
|
||||
break;
|
||||
|
||||
case PCIndexSelect::Instance:
|
||||
counter_start = info_.counterIndex_;
|
||||
counter_step = blockProps.instanceCount;
|
||||
break;
|
||||
|
||||
default:
|
||||
assert(0 && "Unknown indexSelect_");
|
||||
return true;
|
||||
}
|
||||
|
||||
for (uint32_t i = counter_start; i < blockProps.instanceCount; i += counter_step) {
|
||||
counterInfo.instance = i;
|
||||
result = iPerf()->AddCounter(counterInfo);
|
||||
if (result == Pal::Result::Success) {
|
||||
index_.push_back(palRef_->getPalCounterIndex());
|
||||
}
|
||||
else {
|
||||
// Get here when there's no HW PerfCounter matching the counterInfo
|
||||
assert(0 && "AddCounter() failed");
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
uint64_t
|
||||
|
||||
@@ -10,6 +10,14 @@
|
||||
|
||||
namespace pal {
|
||||
|
||||
enum class PCIndexSelect : uint
|
||||
{
|
||||
None = 0, ///< no index
|
||||
Instance, ///< index by block instance
|
||||
ShaderEngine, ///< index by shader engine
|
||||
ShaderEngineAndInstance, ///< index by shader and instance
|
||||
};
|
||||
|
||||
class VirtualGPU;
|
||||
|
||||
class PalCounterReference : public amd::ReferenceCountedObject
|
||||
@@ -38,7 +46,7 @@ public:
|
||||
bool finalize();
|
||||
|
||||
//! Returns the PAL counter results
|
||||
uint64_t result(int index);
|
||||
uint64_t result(const std::vector<int>& index);
|
||||
|
||||
//! Get the latest Experiment Counter index
|
||||
uint getPalCounterIndex() { return numExpCounters_++; };
|
||||
@@ -69,9 +77,10 @@ public:
|
||||
//! The performance counter info
|
||||
struct Info : public amd::EmbeddedObject
|
||||
{
|
||||
uint blockIndex_; //!< Index of the block to configure
|
||||
uint counterIndex_; //!< Index of the hardware counter
|
||||
uint eventIndex_; //!< Event you wish to count with the counter
|
||||
uint blockIndex_; //!< Index of the block to configure
|
||||
uint counterIndex_; //!< Index of the hardware counter
|
||||
uint eventIndex_; //!< Event you wish to count with the counter
|
||||
PCIndexSelect indexSelect_; //!< IndexSelect type of the counter
|
||||
};
|
||||
|
||||
//! Constructor for the GPU PerfCounter object
|
||||
@@ -83,7 +92,6 @@ public:
|
||||
cl_uint eventIndex) //!< Event index for profiling
|
||||
: gpuDevice_(device)
|
||||
, palRef_(palRef)
|
||||
, index_(0)
|
||||
{
|
||||
info_.blockIndex_ = blockIndex;
|
||||
info_.counterIndex_ = counterIndex;
|
||||
@@ -127,7 +135,7 @@ private:
|
||||
const Device& gpuDevice_; //!< The backend device
|
||||
PalCounterReference* palRef_; //!< Reference counter
|
||||
Info info_; //!< The info structure for perfcounter
|
||||
int index_; //!< Counter index in the PAL container
|
||||
std::vector<int> index_; //!< Counter index in the PAL container
|
||||
};
|
||||
|
||||
} // namespace pal
|
||||
|
||||
Reference in New Issue
Block a user