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Support ptrace access invisible vram

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Invisible device memory is mmapped as PROT_NONE.
Normal CPU access to the memory is still not allowed but
struct vm_area_struct will be created for the memory address
so ptrace can access the memory via the vma.

Change-Id: I07c69208716c920ccce33e6b494b610b61a0a7c1
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>


[ROCm/ROCR-Runtime commit: 25170c3c57]
This commit is contained in:
Oak Zeng
2017-12-08 15:59:01 -05:00
parent 1a9af8b82d
commit ad1f1ee5dc
1 changed files with 13 additions and 6 deletions
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projects/rocr-runtime/src/fmm.c
+13 -6
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@@ -150,7 +150,7 @@ typedef struct {
*/
static gpu_mem_t *gpu_mem;
static unsigned int gpu_mem_count;
static bool hsa_debug;
static void *dgpu_shared_aperture_base;
static void *dgpu_shared_aperture_limit;
@@ -1044,13 +1044,16 @@ void *fmm_allocate_device(uint32_t gpu_id, uint64_t MemorySizeInBytes, HsaMemFla
pthread_mutex_unlock(&aperture->fmm_mutex);
}
if (mem && flags.ui32.HostAccess) {
if (mem && (flags.ui32.HostAccess || hsa_debug)) {
int map_fd = mmap_offset >= (1ULL<<40) ? kfd_fd :
get_drm_render_fd_by_gpu_id(gpu_id);
void *ret = mmap(mem, MemorySizeInBytes,
PROT_READ | PROT_WRITE,
MAP_SHARED | MAP_FIXED,
map_fd, mmap_offset);
int prot = flags.ui32.HostAccess ? PROT_READ | PROT_WRITE :
PROT_NONE;
int flag = flags.ui32.HostAccess ? MAP_SHARED | MAP_FIXED :
MAP_PRIVATE|MAP_FIXED;
void *ret = mmap(mem, MemorySizeInBytes, prot, flag,
map_fd, mmap_offset);
if (ret == MAP_FAILED) {
__fmm_release(mem, aperture);
return NULL;
@@ -1455,9 +1458,13 @@ HSAKMT_STATUS fmm_init_process_apertures(unsigned int NumNodes)
uint32_t num_of_nodes;
HSAKMT_STATUS ret = HSAKMT_STATUS_SUCCESS;
char *disableCache, *pagedUserptr, *checkUserptr, *guardPagesStr;
char *hsaDebug;
unsigned int guardPages = 1;
struct pci_access *pacc;
hsaDebug = getenv("HSA_DEBUG");
hsa_debug = hsaDebug && strcmp(hsaDebug, "0");
/* If HSA_DISABLE_CACHE is set to a non-0 value, disable caching */
disableCache = getenv("HSA_DISABLE_CACHE");
if (disableCache && strcmp(disableCache, "0") == 0)