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P4 to Git Change 1226780 by nhaustov@nhaustov_hsa on 2016/01/12 07:20:04

Przeglądaj źródła 
SWDEV-77584 - ORCA RT/Compiler Lib: Add 8:0:4, 8:1:0 and 9:0:1 compute capabilities.

	Changes by Evgeniy Mankov.

	Also cherry-pick CL 1226741 for 8:1:0 compute capability.

	Testing: smoke, pre-checkin

	[Reviewers] Nikolay Haustov, German Andryeyev

Affected files ...

... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/libUtils.cpp#14 edit
... //depot/stg/opencl/drivers/opencl/compiler/sc/HSAIL/ext/finalizer/program.cpp#20 integrate
... //depot/stg/opencl/drivers/opencl/compiler/sc/HSAIL/ext/loader/loaders.cpp#7 integrate
... //depot/stg/opencl/drivers/opencl/compiler/sc/HSAIL/ext/loader/loaders.hpp#7 integrate
... //depot/stg/opencl/drivers/opencl/compiler/sc/HSAIL/tests/tlst/finalizer_offline.tlst#15 integrate
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpudefs.hpp#131 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuprogram.cpp#219 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuprogram.hpp#63 edit


[ROCm/clr commit: 6a0e72acc5]
This commit is contained in:
foreman
2016-01-12 07:27:39 -05:00
rodzic e7716dbb03
commit ae8bbd60ae
4 zmienionych plików z 44 dodań i 17 usunięć
Ściągnij plik aktualizacji Ściągnij plik porównania Expand all files Collapse all files
projects/clr/rocclr/compiler/lib/utils/v0_8/libUtils.cpp
+5 -1
Wyświetl plik
@@ -18,7 +18,10 @@ static const std::string sgfx700 = "AMD:AMDGPU:7:0:0";
static const std::string sgfx701 = "AMD:AMDGPU:7:0:1";
static const std::string sgfx800 = "AMD:AMDGPU:8:0:0";
static const std::string sgfx801 = "AMD:AMDGPU:8:0:1";
static const std::string sgfx804 = "AMD:AMDGPU:8:0:4";
static const std::string sgfx810 = "AMD:AMDGPU:8:1:0";
static const std::string sgfx900 = "AMD:AMDGPU:9:0:0";
static const std::string sgfx901 = "AMD:AMDGPU:9:0:1";
// Utility function to set a flag in option structure
// of the aclDevCaps.
@@ -537,12 +540,13 @@ const std::string &getIsaTypeName(const aclTargetInfo *target)
case VI_TONGA_P_A0: return sgfx800;
case VI_ELLESMERE_P_A0:
case VI_BAFFIN_M_A0:
case VI_FIJI_P_A0: return sgfx801;
case VI_FIJI_P_A0: return sgfx804;
}
case FAMILY_CZ:
switch (Mapping.chip_enum) {
default: return sgfx801;
case CARRIZO_A0: return sgfx801;
case STONEY_A0: return sgfx810;
}
case FAMILY_AI:
switch (Mapping.chip_enum) {
projects/clr/rocclr/runtime/device/gpu/gpudefs.hpp
+14
Wyświetl plik
@@ -129,12 +129,26 @@ static const AMDDeviceInfo DeviceInfo[] = {
/* CAL_TARGET_STONEY */ { ED_ATI_CAL_MACHINE_STONEY_ISA, "Stoney", "stoney", 4, 16, 1, 256, 64 * Ki, 32, 800 },
};
enum gfx_handle {
gfx700 = 700,
gfx701 = 701,
gfx702 = 702,
gfx800 = 800,
gfx801 = 801,
gfx804 = 804,
gfx810 = 810,
gfx900 = 900,
gfx901 = 901
};
static const char* Gfx700 = "AMD:AMDGPU:7:0:0";
static const char* Gfx701 = "AMD:AMDGPU:7:0:1";
static const char* Gfx800 = "AMD:AMDGPU:8:0:0";
static const char* Gfx801 = "AMD:AMDGPU:8:0:1";
static const char* Gfx804 = "AMD:AMDGPU:8:0:4";
static const char* Gfx810 = "AMD:AMDGPU:8:1:0";
static const char* Gfx900 = "AMD:AMDGPU:9:0:0";
static const char* Gfx901 = "AMD:AMDGPU:9:0:1";
// Supported OpenCL versions
enum OclVersion {
projects/clr/rocclr/runtime/device/gpu/gpuprogram.cpp
+25 -6
Wyświetl plik
@@ -2351,8 +2351,10 @@ hsa_isa_t ORCAHSALoaderContext::IsaFromName(const char *name) {
if (!strcmp(Gfx701, name)) { isa.handle = gfx701; return isa; }
if (!strcmp(Gfx800, name)) { isa.handle = gfx800; return isa; }
if (!strcmp(Gfx801, name)) { isa.handle = gfx801; return isa; }
if (!strcmp(Gfx804, name)) { isa.handle = gfx804; return isa; }
if (!strcmp(Gfx810, name)) { isa.handle = gfx810; return isa; }
if (!strcmp(Gfx900, name)) { isa.handle = gfx900; return isa; }
if (!strcmp(Gfx901, name)) { isa.handle = gfx901; return isa; }
return isa;
}
@@ -2367,15 +2369,32 @@ bool ORCAHSALoaderContext::IsaSupportedByAgent(hsa_agent_t agent, hsa_isa_t isa)
// gfx701 only differs from gfx700 by faster fp operations and can be loaded on either device.
return isa.handle == gfx700 || isa.handle == gfx701;
case gfx800:
if (ED_ATI_CAL_MACHINE_ICELAND_ISA == program_->dev().hwInfo()->machine_ ||
ED_ATI_CAL_MACHINE_TONGA_ISA == program_->dev().hwInfo()->machine_ ) {
switch (program_->dev().hwInfo()->machine_) {
case ED_ATI_CAL_MACHINE_ICELAND_ISA:
case ED_ATI_CAL_MACHINE_TONGA_ISA:
return isa.handle == gfx800;
} else {
// gfx800 has only sgrps limited and can be loaded on later chips.
return isa.handle == gfx800 || isa.handle == gfx801;
case ED_ATI_CAL_MACHINE_CARRIZO_ISA:
return isa.handle == gfx801;
case ED_ATI_CAL_MACHINE_FIJI_ISA:
case ED_ATI_CAL_MACHINE_ELLESMERE_ISA:
case ED_ATI_CAL_MACHINE_BAFFIN_ISA:
// gfx800 ISA has only sgrps limited and can be loaded.
// gfx801 ISA has XNACK limitations and can be loaded.
return isa.handle == gfx800 || isa.handle == gfx801 || isa.handle == gfx804;
case ED_ATI_CAL_MACHINE_STONEY_ISA:
return isa.handle == gfx810;
default:
assert(0);
return false;
}
case gfx900:
return isa.handle == gfx900;
switch (program_->dev().hwInfo()->machine_) {
case ED_ATI_CAL_MACHINE_GREENLAND_ISA:
return isa.handle == gfx900 || isa.handle == gfx901;
default:
assert(0);
return false;
}
}
}
projects/clr/rocclr/runtime/device/gpu/gpuprogram.hpp
-10
Wyświetl plik
@@ -483,16 +483,6 @@ private:
ORCAHSALoaderContext& operator=(const ORCAHSALoaderContext &c);
enum gfx_handle {
gfx700 = 700,
gfx701 = 701,
gfx702 = 702,
gfx800 = 800,
gfx801 = 801,
gfx810 = 810,
gfx900 = 900
};
gpu::HSAILProgram* program_;
};