P4 to Git Change 1128279 by gandryey@gera-w8 on 2015/03/06 12:37:59
ECR #304775 - Mip levels implementation - Initial change. Update the runtime interfaces to allow a mipmap allocation. Affected files ... ... //depot/stg/opencl/drivers/opencl/api/opencl/amdocl/cl_memobj.cpp#74 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/device.hpp#240 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpublit.cpp#113 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpudevice.cpp#499 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpudevice.hpp#138 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpumemory.cpp#119 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpumemory.hpp#47 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuresource.cpp#210 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuresource.hpp#79 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpusettings.cpp#305 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gslbe/src/rt/GSLDevice.cpp#110 edit ... //depot/stg/opencl/drivers/opencl/runtime/platform/memory.cpp#118 edit ... //depot/stg/opencl/drivers/opencl/runtime/platform/memory.hpp#89 edit ... //depot/stg/opencl/drivers/opencl/runtime/utils/flags.hpp#225 edit
Этот коммит содержится в:
@@ -111,6 +111,8 @@ enum OclExtensions {
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ClKhrSubGroups,
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ClKhrGlEvent,
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ClKhrDepthImages,
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ClKhrMipMapImage,
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ClKhrMipMapImageWrites,
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ClExtTotal
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};
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@@ -152,6 +154,8 @@ OclExtensionsString[] = {
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"cl_khr_subgroups ",
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"cl_khr_gl_event ",
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"cl_khr_depth_images ",
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"cl_khr_mipmap_image ",
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"cl_khr_mipmap_image_writes ",
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NULL
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};
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@@ -2826,7 +2826,8 @@ KernelBlitManager::createView(
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parent.cal()->depth_,
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format.type_,
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format.channelOrder_,
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parent.cal()->imageType_);
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parent.cal()->imageType_,
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1);
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// Create resource
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if (NULL != gpuImage) {
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@@ -276,13 +276,12 @@ Device::Engines::getRequested(uint engines, gslEngineDescriptor* desc) const
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Device::XferBuffers::~XferBuffers()
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{
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// Destroy temporary buffer for reads
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for (std::list<Resource*>::const_iterator i = freeBuffers_.begin();
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i != freeBuffers_.end(); ++i) {
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for (const auto& buf : freeBuffers_) {
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// CPU optimization: unmap staging buffer just once
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if (!(*i)->cal()->cardMemory_) {
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(*i)->unmap(NULL);
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if (!buf->cal()->cardMemory_) {
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buf->unmap(NULL);
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}
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delete (*i);
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delete buf;
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}
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freeBuffers_.clear();
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}
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@@ -1748,7 +1747,8 @@ Device::createImage(amd::Memory& owner, bool directAccess) const
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image.getDepth(),
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format.type_,
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format.channelOrder_,
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image.getType());
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image.getType(),
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image.getMipLevels());
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// Create resource
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if (NULL != gpuImage) {
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@@ -2001,7 +2001,8 @@ Device::createView(amd::Memory& owner, const device::Memory& parent) const
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image.getDepth(),
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format.type_,
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format.channelOrder_,
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image.getType());
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image.getType(),
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image.getMipLevels());
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// Create resource
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if (NULL != gpuImage) {
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@@ -2223,13 +2224,11 @@ Device::removeVACache(const Memory* memory) const
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void* end = reinterpret_cast<address>(start) + memory->owner()->getSize();
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// Find VA cache entry for the specified memory
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std::list<VACacheEntry*>::const_iterator it;
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for (it = vaCacheList_->begin(); it != vaCacheList_->end(); ++it) {
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VACacheEntry* entry = *it;
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for (const auto& entry : *vaCacheList_) {
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if (entry->startAddress_ == start) {
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CondLog((entry->endAddress_ != end), "Incorrect VA range");
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vaCacheList_->remove(entry);
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delete entry;
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vaCacheList_->remove(entry);
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break;
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}
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}
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@@ -2241,9 +2240,7 @@ Device::findMemoryFromVA(const void* ptr, size_t* offset) const
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{
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// VA cache access must be serialised
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amd::ScopedLock lk(*vaCacheAccess_);
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std::list<VACacheEntry*>::const_iterator it;
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for (it = vaCacheList_->begin(); it != vaCacheList_->end(); ++it) {
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VACacheEntry* entry = *it;
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for (const auto& entry : *vaCacheList_) {
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if ((entry->startAddress_ <= ptr) && (entry->endAddress_ > ptr)) {
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*offset = static_cast<size_t>(reinterpret_cast<const char*>(ptr) -
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reinterpret_cast<char*>(entry->startAddress_));
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@@ -105,10 +105,11 @@ Memory::Memory(
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size_t depth,
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cmSurfFmt format,
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gslChannelOrder chOrder,
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cl_mem_object_type imageType
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cl_mem_object_type imageType,
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uint mipLevels
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)
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: device::Memory(owner)
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, Resource(gpuDev, width, height, depth, format, chOrder, imageType)
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, Resource(gpuDev, width, height, depth, format, chOrder, imageType, mipLevels)
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, hb_(NULL)
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{
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init();
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@@ -126,10 +127,11 @@ Memory::Memory(
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size_t depth,
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cmSurfFmt format,
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gslChannelOrder chOrder,
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cl_mem_object_type imageType
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cl_mem_object_type imageType,
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uint mipLevels
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)
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: device::Memory(size)
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, Resource(gpuDev, width, height, depth, format, chOrder, imageType)
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, Resource(gpuDev, width, height, depth, format, chOrder, imageType, mipLevels)
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, hb_(NULL)
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{
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init();
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@@ -602,7 +604,6 @@ Memory::syncCacheFromHost(VirtualGPU& gpu, device::Memory::SyncFlags syncFlags)
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// Update all available views, since we sync the parent
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if ((owner()->subBuffers().size() != 0) &&
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(hasUpdates || !syncFlags.skipViews_)) {
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std::list<amd::Memory*>::const_iterator it;
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device::Memory::SyncFlags syncFlagsTmp;
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// Sync views from parent, so parent has to be skipped
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@@ -619,14 +620,13 @@ Memory::syncCacheFromHost(VirtualGPU& gpu, device::Memory::SyncFlags syncFlags)
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}
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amd::ScopedLock lock(owner()->lockMemoryOps());
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for (it = owner()->subBuffers().begin();
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it != owner()->subBuffers().end(); ++it) {
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for (auto& sub : owner()->subBuffers()) {
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//! \note Don't allow subbuffer's allocation in the worker thread.
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//! It may cause a system lock, because possible resource
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//! destruction, heap reallocation or subbuffer allocation
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static const bool AllocSubBuffer = false;
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device::Memory* devSub =
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(*it)->getDeviceMemory(dev(), AllocSubBuffer);
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sub->getDeviceMemory(dev(), AllocSubBuffer);
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if (NULL != devSub) {
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gpu::Memory* gpuSub = reinterpret_cast<gpu::Memory*>(devSub);
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gpuSub->syncCacheFromHost(gpu, syncFlagsTmp);
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@@ -728,7 +728,6 @@ Memory::syncHostFromCache(device::Memory::SyncFlags syncFlags)
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// Update all available views, since we sync the parent
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if ((owner()->subBuffers().size() != 0) &&
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(hasUpdates || !syncFlags.skipViews_)) {
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std::list<amd::Memory*>::const_iterator it;
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device::Memory::SyncFlags syncFlagsTmp;
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// Sync views from parent, so parent has to be skipped
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@@ -745,14 +744,13 @@ Memory::syncHostFromCache(device::Memory::SyncFlags syncFlags)
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}
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amd::ScopedLock lock(owner()->lockMemoryOps());
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for (it = owner()->subBuffers().begin();
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it != owner()->subBuffers().end(); ++it) {
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for (auto& sub : owner()->subBuffers()) {
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//! \note Don't allow subbuffer's allocation in the worker thread.
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//! It may cause a system lock, because possible resource
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//! destruction, heap reallocation or subbuffer allocation
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static const bool AllocSubBuffer = false;
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device::Memory* devSub =
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(*it)->getDeviceMemory(dev(), AllocSubBuffer);
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sub->getDeviceMemory(dev(), AllocSubBuffer);
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if (NULL != devSub) {
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gpu::Memory* gpuSub = reinterpret_cast<gpu::Memory*>(devSub);
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gpuSub->syncHostFromCache(syncFlagsTmp);
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@@ -82,7 +82,8 @@ public:
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size_t depth, //!< Allocated memory depth
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cmSurfFmt format, //!< Memory format
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gslChannelOrder chOrder, //!< Channel order
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cl_mem_object_type imageType //!< CL image type
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cl_mem_object_type imageType, //!< CL image type
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uint mipLevels //!< The number of mip levels
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);
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//! Constructor memory for images (without global heap allocaton)
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@@ -94,7 +95,8 @@ public:
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size_t depth, //!< Allocated memory depth
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cmSurfFmt format, //!< Memory format
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gslChannelOrder chOrder, //!< Channel order
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cl_mem_object_type imageType //!< CL image type
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cl_mem_object_type imageType, //!< CL image type
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uint mipLevels //!< The number of mip levels
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);
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//! Default destructor
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@@ -276,9 +278,10 @@ public:
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size_t depth, //!< Allocated memory depth
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cmSurfFmt format, //!< Memory format
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gslChannelOrder chOrder, //!< Channel order
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cl_mem_object_type imageType //!< CL image type
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cl_mem_object_type imageType, //!< CL image type
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uint mipLevels //!< The number of mip levels
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)
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: gpu::Memory(gpuDev, owner, width, height, depth, format, chOrder, imageType)
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: gpu::Memory(gpuDev, owner, width, height, depth, format, chOrder, imageType, mipLevels)
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{}
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//! Image constructor
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@@ -290,9 +293,10 @@ public:
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size_t depth, //!< Allocated memory depth
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cmSurfFmt format, //!< Memory format
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gslChannelOrder chOrder, //!< Channel order
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cl_mem_object_type imageType //!< CL image type
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cl_mem_object_type imageType, //!< CL image type
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uint mipLevels //!< The number of mip levels
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)
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: gpu::Memory(gpuDev, size, width, height, depth, format, chOrder, imageType)
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: gpu::Memory(gpuDev, size, width, height, depth, format, chOrder, imageType, mipLevels)
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{}
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//! Allocate memory for API-level maps
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@@ -77,6 +77,7 @@ Resource::Resource(
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cal_.width_ = width;
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cal_.height_ = 1;
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cal_.depth_ = 1;
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cal_.mipLevels_ = 1;
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cal_.format_ = format;
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cal_.flags_ = 0;
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cal_.pitch_ = 0;
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@@ -99,7 +100,8 @@ Resource::Resource(
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size_t depth,
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cmSurfFmt format,
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gslChannelOrder chOrder,
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cl_mem_object_type imageType)
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cl_mem_object_type imageType,
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uint mipLevels)
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: elementSize_(0)
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, gpuDevice_(gpuDev)
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, mapCount_(0)
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@@ -121,6 +123,7 @@ Resource::Resource(
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cal_.width_ = width;
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cal_.height_ = height;
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cal_.depth_ = depth;
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cal_.mipLevels_ = mipLevels;
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cal_.format_ = format;
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cal_.flags_ = 0;
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cal_.pitch_ = 0;
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@@ -435,7 +438,7 @@ Resource::create(MemoryType memType, CreateParams* params, bool heap)
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desc.format = cal()->format_;
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desc.channelOrder = cal()->channelOrder_;
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desc.flags = cal()->flags_;
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desc.mipLevels = 0;
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desc.mipLevels = cal()->mipLevels_;
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desc.systemMemory = NULL;
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do {
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@@ -2023,7 +2026,6 @@ GslResourceReference*
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ResourceCache::findCalResource(Resource::CalResourceDesc* desc)
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{
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amd::ScopedLock l(&lockCacheOps_);
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bool found = false;
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GslResourceReference* ref = NULL;
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size_t size = getResourceSize(desc);
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@@ -2034,10 +2036,8 @@ ResourceCache::findCalResource(Resource::CalResourceDesc* desc)
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}
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// Serach the right resource through the cache list
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std::list<std::pair<Resource::CalResourceDesc*,
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GslResourceReference*> >::const_iterator it;
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for (it = resCache_.begin(); it != resCache_.end(); ++it) {
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Resource::CalResourceDesc* entry = it->first;
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for (const auto& it: resCache_) {
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Resource::CalResourceDesc* entry = it.first;
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// Find if we can reuse this entry
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if ((entry->dimension_ == desc->dimension_) &&
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(entry->type_ == desc->type_) &&
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@@ -2047,19 +2047,15 @@ ResourceCache::findCalResource(Resource::CalResourceDesc* desc)
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(entry->channelOrder_ == desc->channelOrder_) &&
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(entry->format_ == desc->format_) &&
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(entry->flags_ == desc->flags_)) {
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ref = it->second;
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delete it->first;
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found = true;
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ref = it.second;
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delete it.first;
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// Remove the found etry from the cache
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resCache_.remove(it);
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cacheSize_ -= size;
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break;
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}
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}
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if (found) {
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// Remove the found etry from the cache
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resCache_.remove(*it);
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cacheSize_ -= size;
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}
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return ref;
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}
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@@ -158,6 +158,7 @@ public:
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size_t width_; //!< CAL resource width
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size_t height_; //!< CAL resource height
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size_t depth_; //!< CAL resource depth
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uint mipLevels_; //!< Number of mip levels
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cmSurfFmt format_; //!< GSL resource format
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CALuint flags_; //!< CAL resource flags, used in creation
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size_t pitch_; //!< CAL resource pitch, valid if locked
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@@ -194,7 +195,8 @@ public:
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size_t depth, //!< resource depth
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cmSurfFmt format, //!< resource format
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gslChannelOrder chOrder, //!< resource channel order
|
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cl_mem_object_type imageType //!< CL image type
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cl_mem_object_type imageType, //!< CL image type
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uint mipLevels = 1 //!< Number of mip levels
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);
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//! Destructor of the resource
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@@ -134,7 +134,6 @@ Settings::Settings()
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// Use host queue for device enqueuing by default
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useDeviceQueue_ = GPU_USE_DEVICE_QUEUE;
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}
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bool
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@@ -282,11 +281,13 @@ Settings::create(
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if (ciPlus_) {
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libSelector_ = amd::GPU_Library_CI;
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#if defined(_LP64)
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oclVersion_ = !reportAsOCL12Device && calAttr.isOpenCL200Device ? XCONCAT(OpenCL, XCONCAT(OPENCL_MAJOR, OPENCL_MINOR)) : OpenCL12;
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oclVersion_ = !reportAsOCL12Device && calAttr.isOpenCL200Device ?
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XCONCAT(OpenCL, XCONCAT(OPENCL_MAJOR, OPENCL_MINOR)) : OpenCL12;
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#endif
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if (GPU_FORCE_OCL20_32BIT) {
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force32BitOcl20_ = true;
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oclVersion_ = !reportAsOCL12Device && calAttr.isOpenCL200Device ? XCONCAT(OpenCL, XCONCAT(OPENCL_MAJOR, OPENCL_MINOR)) : OpenCL12;
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oclVersion_ = !reportAsOCL12Device && calAttr.isOpenCL200Device ?
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XCONCAT(OpenCL, XCONCAT(OPENCL_MAJOR, OPENCL_MINOR)) : OpenCL12;
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}
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if (hsail_ || (OPENCL_VERSION < 200)) {
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oclVersion_ = OpenCL12;
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@@ -432,6 +433,11 @@ Settings::create(
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enableExtension(ClKhrSubGroups);
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enableExtension(ClKhrDepthImages);
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|
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if (GPU_MIPMAP) {
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enableExtension(ClKhrMipMapImage);
|
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enableExtension(ClKhrMipMapImageWrites);
|
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}
|
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|
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// Enable HW debug
|
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if (GPU_ENABLE_HW_DEBUG) {
|
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enableHwDebug_ = true;
|
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|
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@@ -780,6 +780,10 @@ CALGSLDevice::resAlloc(const CALresourceDesc* desc) const
|
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|
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attribs.channelOrder = desc->channelOrder;
|
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attribs.type = desc->dimension;
|
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if (desc->mipLevels > 1) {
|
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attribs.levels = desc->mipLevels;
|
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attribs.mipmap = true;
|
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}
|
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switch (desc->dimension)
|
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{
|
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case GSL_MOA_BUFFER:
|
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|
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@@ -550,9 +550,15 @@ Pipe::initDeviceMemory()
|
||||
|
||||
Image::Image(
|
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const Format& format,
|
||||
Image& parent) :
|
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Memory(parent, 0, 0, parent.getWidth() * parent.getHeight() * parent.getDepth() * format.getElementSize()) ,
|
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impl_(format, Coord3D(parent.getWidth() * parent.getImageFormat().getElementSize() / format.getElementSize(), parent.getHeight(), parent.getDepth()), parent.getRowPitch(), parent.getSlicePitch(), parent.getBytePitch())
|
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Image& parent)
|
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: Memory(parent, 0, 0, parent.getWidth() * parent.getHeight() *
|
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parent.getDepth() * format.getElementSize())
|
||||
, impl_(format, Coord3D(parent.getWidth() *
|
||||
parent.getImageFormat().getElementSize() /
|
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format.getElementSize(), parent.getHeight(),
|
||||
parent.getDepth()), parent.getRowPitch(),
|
||||
parent.getSlicePitch(), parent.getBytePitch())
|
||||
, mipLevels_(1)
|
||||
{
|
||||
initDimension();
|
||||
}
|
||||
@@ -566,10 +572,11 @@ Image::Image(
|
||||
size_t height,
|
||||
size_t depth,
|
||||
size_t rowPitch,
|
||||
size_t slicePitch) :
|
||||
Memory(context, type, flags,
|
||||
width * height * depth * format.getElementSize()) ,
|
||||
impl_(format, Coord3D(width, height, depth), rowPitch, slicePitch)
|
||||
size_t slicePitch,
|
||||
uint mipLevels)
|
||||
: Memory(context, type, flags, width * height * depth * format.getElementSize())
|
||||
, impl_(format, Coord3D(width, height, depth), rowPitch, slicePitch)
|
||||
, mipLevels_(mipLevels)
|
||||
{
|
||||
initDimension();
|
||||
}
|
||||
@@ -583,10 +590,10 @@ Image::Image(
|
||||
size_t height,
|
||||
size_t depth,
|
||||
size_t rowPitch,
|
||||
size_t slicePitch) :
|
||||
Memory(buffer, flags, 0,
|
||||
buffer.getSize(), type) ,
|
||||
impl_(format, Coord3D(width, height, depth), rowPitch, slicePitch)
|
||||
size_t slicePitch)
|
||||
: Memory(buffer, flags, 0, buffer.getSize(), type)
|
||||
, impl_(format, Coord3D(width, height, depth), rowPitch, slicePitch)
|
||||
, mipLevels_(1)
|
||||
{
|
||||
initDimension();
|
||||
}
|
||||
@@ -600,17 +607,16 @@ Image::validateDimensions(
|
||||
size_t depth,
|
||||
size_t arraySize)
|
||||
{
|
||||
std::vector<amd::Device*>::const_iterator it;
|
||||
bool sizePass = false;
|
||||
switch (type) {
|
||||
case CL_MEM_OBJECT_IMAGE3D:
|
||||
if ((width == 0) || (height == 0) || (depth < 1)) {
|
||||
return false;
|
||||
}
|
||||
for (it = devices.begin(); it != devices.end(); ++it) {
|
||||
if (((*it)->info().image3DMaxWidth_ >= width) &&
|
||||
((*it)->info().image3DMaxHeight_ >= height) &&
|
||||
((*it)->info().image3DMaxDepth_ >= depth)) {
|
||||
for (const auto& dev : devices) {
|
||||
if ((dev->info().image3DMaxWidth_ >= width) &&
|
||||
(dev->info().image3DMaxHeight_ >= height) &&
|
||||
(dev->info().image3DMaxDepth_ >= depth)) {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
@@ -619,8 +625,8 @@ Image::validateDimensions(
|
||||
if (arraySize == 0) {
|
||||
return false;
|
||||
}
|
||||
for (it = devices.begin(); it != devices.end(); ++it) {
|
||||
if ((*it)->info().imageMaxArraySize_ >= arraySize) {
|
||||
for (const auto& dev : devices) {
|
||||
if (dev->info().imageMaxArraySize_ >= arraySize) {
|
||||
sizePass = true;
|
||||
break;
|
||||
}
|
||||
@@ -633,9 +639,9 @@ Image::validateDimensions(
|
||||
if ((width == 0) || (height == 0)) {
|
||||
return false;
|
||||
}
|
||||
for (it = devices.begin(); it != devices.end(); ++it) {
|
||||
if (((*it)->info().image2DMaxHeight_ >= height) &&
|
||||
((*it)->info().image2DMaxWidth_ >= width)) {
|
||||
for (const auto dev : devices) {
|
||||
if ((dev->info().image2DMaxHeight_ >= height) &&
|
||||
(dev->info().image2DMaxWidth_ >= width)) {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
@@ -645,8 +651,8 @@ Image::validateDimensions(
|
||||
return false;
|
||||
}
|
||||
|
||||
for (it = devices.begin(); it != devices.end(); ++it) {
|
||||
if ((*it)->info().imageMaxArraySize_ >= arraySize) {
|
||||
for (const auto& dev : devices) {
|
||||
if (dev->info().imageMaxArraySize_ >= arraySize) {
|
||||
sizePass = true;
|
||||
break;
|
||||
}
|
||||
@@ -659,8 +665,8 @@ Image::validateDimensions(
|
||||
if (width == 0) {
|
||||
return false;
|
||||
}
|
||||
for (it = devices.begin(); it != devices.end(); ++it) {
|
||||
if ((*it)->info().image2DMaxWidth_ >= width) {
|
||||
for (const auto& dev : devices) {
|
||||
if (dev->info().image2DMaxWidth_ >= width) {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
@@ -669,8 +675,8 @@ Image::validateDimensions(
|
||||
if (width == 0) {
|
||||
return false;
|
||||
}
|
||||
for (it = devices.begin(); it != devices.end(); ++it) {
|
||||
if ((*it)->info().imageMaxBufferSize_ >= width) {
|
||||
for (const auto& dev : devices) {
|
||||
if (dev->info().imageMaxBufferSize_ >= width) {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
@@ -1488,7 +1494,7 @@ bool
|
||||
SvmBuffer::Contains(uintptr_t ptr)
|
||||
{
|
||||
ScopedLock lock(AllocatedLock_);
|
||||
std::map<uintptr_t, uintptr_t>::iterator it = Allocated_.upper_bound(ptr);
|
||||
auto it = Allocated_.upper_bound(ptr);
|
||||
if (it == Allocated_.begin()) {
|
||||
return false;
|
||||
}
|
||||
|
||||
@@ -490,10 +490,10 @@ public:
|
||||
|
||||
struct Impl
|
||||
{
|
||||
const amd::Coord3D region_;
|
||||
size_t rp_;
|
||||
size_t sp_;
|
||||
const Format format_;
|
||||
const amd::Coord3D region_; //!< Image size
|
||||
size_t rp_; //!< Image row pitch
|
||||
size_t sp_; //!< Image slice pitch
|
||||
const Format format_; //!< Image format
|
||||
void* reserved_;
|
||||
size_t bp_;
|
||||
|
||||
@@ -505,6 +505,7 @@ public:
|
||||
private:
|
||||
Impl impl_; //!< Image object description
|
||||
size_t dim_; //!< Image dimension
|
||||
uint mipLevels_; //!< The number of mip levels
|
||||
|
||||
protected:
|
||||
Image(
|
||||
@@ -532,7 +533,8 @@ public:
|
||||
size_t height,
|
||||
size_t depth,
|
||||
size_t rowPitch,
|
||||
size_t slicePitch);
|
||||
size_t slicePitch,
|
||||
uint mipLevels = 1);
|
||||
|
||||
Image(
|
||||
Buffer& buffer,
|
||||
@@ -612,10 +614,13 @@ public:
|
||||
//! Returns image's slice pitch in bytes
|
||||
size_t getSlicePitch() const { return impl_.sp_; }
|
||||
|
||||
//! Returns image's slice pitch in bytes
|
||||
uint getMipLevels() const { return mipLevels_; }
|
||||
|
||||
//! Get the image covered region
|
||||
const Coord3D& getRegion() const { return impl_.region_; }
|
||||
|
||||
//! Sets the byte pitch obtained from HWL.
|
||||
//! Sets the byte pitch obtained from HWL
|
||||
void setBytePitch(size_t bytePitch) { impl_.bp_ = bytePitch; }
|
||||
|
||||
//! Creates and initializes device (cache) memory for all devices
|
||||
|
||||
@@ -168,8 +168,8 @@ release(bool, HSA_ENABLE_ATOMICS_32B, false, \
|
||||
"1 = Enable SVM atomics in 32 bits (HSA backend-only). Any other value keeps then disabled.") \
|
||||
release(bool, GPU_IFH_MODE, false, \
|
||||
"1 = Enable GPU IFH (infinitely fast hardware) mode. Any other value keeps setting disabled.") \
|
||||
release(bool, HSAIL_IMAGE_HANDLE_ENABLE, false, \
|
||||
"Pass image/sampler SRD as pointer instead of blob") \
|
||||
release(bool, GPU_MIPMAP, false, \
|
||||
"Enables GPU mipmap extension") \
|
||||
debug(bool, GPU_FORCE_SINGLE_FP_DENORM, false, \
|
||||
"Forces reporting CL_FP_DENORM bit for single precision") \
|
||||
debug(bool, OCL_FORCE_CPU_SVM, false, \
|
||||
|
||||
Ссылка в новой задаче
Block a user