P4 to Git Change 1521567 by gandryey@gera-w8 on 2018/03/01 18:29:47
SWDEV-145716 - dGMA via OpenCL not working properly on AMD EPYC Ethanol platform with two WX9100/W9100s
- Add a stall and cache flushes before a barrier write in GSL and PAL
- Place temporary workarounds for CP prefetch of WRITE_DATA and the lack of SDMA marker in PAL
Affected files ...
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuvirtual.cpp#414 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palvirtual.cpp#76 edit
[ROCm/clr commit: 30eacbe243]
Dieser Commit ist enthalten in:
@@ -2380,6 +2380,8 @@ void VirtualGPU::submitSignal(amd::SignalCommand& vcmd) {
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uint64_t markerOffset = markerAddr - surfAddr;
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cs()->p2pMarkerOp(gpuMemory->gslResource(), vcmd.markerValue(), markerOffset, false);
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} else if (vcmd.type() == CL_COMMAND_WRITE_SIGNAL_AMD) {
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static constexpr bool FlushL2 = true;
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flushCUCaches(FlushL2);
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cs()->p2pMarkerOp(gpuMemory->gslResource(), vcmd.markerValue(), vcmd.markerOffset(), true);
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}
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eventEnd(MainEngine, gpuEvent);
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@@ -2537,6 +2537,17 @@ void VirtualGPU::submitSignal(amd::SignalCommand& vcmd) {
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iCmd()->CmdWaitBusAddressableMemoryMarker(*(pGpuMemory->iMem()), value, 0xFFFFFFFF,
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Pal::CompareFunc::GreaterEqual);
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} else if (vcmd.type() == CL_COMMAND_WRITE_SIGNAL_AMD) {
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// Make sure GPU finished operation and data reached memory before the marker write
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static constexpr bool FlushL2 = true;
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addBarrier(FlushL2);
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// \todo: Implement the right changes in PAL
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// Workarounds: for CP overfetch issues and the lack of SDMA sync
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{
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// Flush CB associated with the DGMA buffer
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isDone(pGpuMemory->getGpuEvent(*this));
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// Make sure SDMA is done on the DGMA buffer
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pGpuMemory->wait(*this, true);
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}
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iCmd()->CmdUpdateBusAddressableMemoryMarker(*(pGpuMemory->iMem()), value);
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}
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eventEnd(MainEngine, gpuEvent);
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