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P4 to Git Change 1519129 by skudchad@skudchad_test2_win_opencl on 2018/02/23 22:04:04

Selaa lähdekoodia 
SWDEV-145570 -  Add new info stats for VDI layer which are reported by HIP

	ReviewBoardURL = http://ocltc.amd.com/reviews/r/14290/diff/

Affected files ...

... //depot/stg/opencl/drivers/opencl/api/opencl/amdocl/cl_device.cpp#70 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/cpu/cpudevice.cpp#283 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/device.hpp#296 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpudevice.cpp#585 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuvirtual.cpp#413 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/paldevice.cpp#74 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palvirtual.cpp#75 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/rocdevice.cpp#83 edit


[ROCm/clr commit: b909e781de]
This commit is contained in:
foreman
2018-02-23 22:16:44 -05:00
vanhempi c4462940db
commit b130343aca
7 muutettua tiedostoa jossa 60 lisäystä ja 20 poistoa
Download Patch File Download Diff File Expand all files Collapse all files
projects/clr/rocclr/runtime/device/cpu/cpudevice.cpp
+6 -4
Näytä tiedosto
@@ -293,7 +293,7 @@ bool Device::init() {
::strcpy(info.name_, line.substr(line.find_first_of(':') + 2).c_str());
name = true;
} else if (!freq && (line.find("cpu MHz\t\t: ") != std::string::npos)) {
info.maxClockFrequency_ = ::atoi(line.substr(line.find_first_of(':') + 2).c_str());
info.maxEngineClockFrequency_ = ::atoi(line.substr(line.find_first_of(':') + 2).c_str());
freq = true;
}
}
@@ -338,7 +338,8 @@ bool Device::init() {
}
info.maxClockFrequency_ = 0;
info.maxEngineClockFrequency_ = 0;
info.maxMemoryClockFrequency_ = 0;
HKEY hKey;
// Open the key
@@ -346,7 +347,7 @@ bool Device::init() {
KEY_QUERY_VALUE, &hKey) == ERROR_SUCCESS) {
// Read the value
DWORD dwLen = 4;
RegQueryValueEx(hKey, "~MHz", NULL, NULL, (LPBYTE)&info.maxClockFrequency_, &dwLen);
RegQueryValueEx(hKey, "~MHz", NULL, NULL, (LPBYTE)&info.maxEngineClockFrequency_, &dwLen);
// Cleanup and return
RegCloseKey(hKey);
@@ -355,7 +356,8 @@ bool Device::init() {
#else
::strcpy(info.name_, "Unknown Processor");
::strcpy(info.vendor_, "Unknown Vendor");
info.maxClockFrequency_ = 0;
info.maxEngineClockFrequency_ = 0;
info.maxMemoryClockFrequency_ = 0;
#endif
#define OPENCL_VERSION_STR XSTR(OPENCL_MAJOR) "." XSTR(OPENCL_MINOR)
projects/clr/rocclr/runtime/device/device.hpp
+16 -2
Näytä tiedosto
@@ -312,8 +312,20 @@ struct Info : public amd::EmbeddedObject {
cl_uint nativeVectorWidthDouble_;
cl_uint nativeVectorWidthHalf_;
//! Maximum configured clock frequency of the device in MHz.
cl_uint maxClockFrequency_;
//! Maximum configured engine clock frequency of the device in MHz.
cl_uint maxEngineClockFrequency_;
//! Maximum configured memory clock frequency of the device in MHz.
cl_uint maxMemoryClockFrequency_;
//! Memory bus width in bits.
cl_uint vramBusBitWidth_;
//! Size of L2 Cache in bytes.
cl_uint l2CacheSize_;
//! Timestamp frequency in Hz.
cl_uint timeStampFrequency_;
//! Describes the address spaces supported by the device.
cl_uint addressBits_;
@@ -518,6 +530,8 @@ struct Info : public amd::EmbeddedObject {
cl_uint simdInstructionWidth_;
//! The number of workitems per wavefront
cl_uint wavefrontWidth_;
//! Available number of SGPRs
cl_uint availableSGPRs_;
//! Number of global memory channels
cl_uint globalMemChannels_;
//! Number of banks in each global memory channel
projects/clr/rocclr/runtime/device/gpu/gpudevice.cpp
+6 -2
Näytä tiedosto
@@ -333,7 +333,11 @@ void NullDevice::fillDeviceInfo(const CALdeviceattribs& calAttr, const gslMemInf
(settings().checkExtension(ClKhrFp64)) ? 1 : 0;
info_.nativeVectorWidthHalf_ = info_.preferredVectorWidthHalf_ = 0; // no half support
info_.maxClockFrequency_ = (calAttr.engineClock != 0) ? calAttr.engineClock : 555;
info_.maxEngineClockFrequency_ = (calAttr.engineClock != 0) ? calAttr.engineClock : 555;
info_.maxMemoryClockFrequency_ = (calAttr.memoryClock != 0) ? calAttr.memoryClock : 555;
info_.timeStampFrequency_ = 1000000;
info_.vramBusBitWidth_ = calAttr.memBusWidth;
info_.l2CacheSize_ = 0;
info_.maxParameterSize_ = 1024;
info_.minDataTypeAlignSize_ = sizeof(cl_long16);
info_.singleFPConfig_ =
@@ -571,7 +575,7 @@ void NullDevice::fillDeviceInfo(const CALdeviceattribs& calAttr, const gslMemInf
info_.simdWidth_ = hwInfo()->simdWidth_;
info_.simdInstructionWidth_ = hwInfo()->simdInstructionWidth_;
info_.wavefrontWidth_ = calAttr.wavefrontSize;
info_.globalMemChannels_ = calAttr.memBusWidth / 32;
info_.globalMemChannelBanks_ = calAttr.numMemBanks;
info_.globalMemChannelBankWidth_ = hwInfo()->memChannelBankWidth_;
info_.localMemSizePerCU_ = hwInfo()->localMemSizePerCU_;
projects/clr/rocclr/runtime/device/gpu/gpuvirtual.cpp
+3 -3
Näytä tiedosto
@@ -124,7 +124,7 @@ void VirtualGPU::MemoryDependency::clear(bool all) {
VirtualGPU::DmaFlushMgmt::DmaFlushMgmt(const Device& dev) : cbWorkload_(0), dispatchSplitSize_(0) {
aluCnt_ = dev.info().simdPerCU_ * dev.info().simdWidth_ * dev.info().maxComputeUnits_;
maxDispatchWorkload_ = static_cast<uint64_t>(dev.info().maxClockFrequency_) *
maxDispatchWorkload_ = static_cast<uint64_t>(dev.info().maxEngineClockFrequency_) *
// find time in us
dev.settings().maxWorkloadTime_ * aluCnt_;
resetCbWorkload(dev);
@@ -132,7 +132,7 @@ VirtualGPU::DmaFlushMgmt::DmaFlushMgmt(const Device& dev) : cbWorkload_(0), disp
void VirtualGPU::DmaFlushMgmt::resetCbWorkload(const Device& dev) {
cbWorkload_ = 0;
maxCbWorkload_ = static_cast<uint64_t>(dev.info().maxClockFrequency_) *
maxCbWorkload_ = static_cast<uint64_t>(dev.info().maxEngineClockFrequency_) *
// find time in us
dev.settings().minWorkloadTime_ * aluCnt_;
}
@@ -1794,7 +1794,7 @@ bool VirtualGPU::submitKernelInternalHSA(const amd::NDRangeContainer& sizes,
gpuDefQueue->schedParams_->data())[gpuDefQueue->schedParamIdx_];
param->signal = 1;
// Scale clock to 1024 to avoid 64 bit div in the scheduler
param->eng_clk = (1000 * 1024) / dev().info().maxClockFrequency_;
param->eng_clk = (1000 * 1024) / dev().info().maxEngineClockFrequency_;
param->hw_queue = patchStart + sizeof(uint32_t) /* Rewind packet*/;
param->hsa_queue = gpuDefQueue->hsaQueueMem()->vmAddress();
param->releaseHostCP = 0;
projects/clr/rocclr/runtime/device/pal/paldevice.cpp
+9 -2
Näytä tiedosto
@@ -276,9 +276,14 @@ void NullDevice::fillDeviceInfo(const Pal::DeviceProperties& palProp,
(settings().checkExtension(ClKhrFp64)) ? 1 : 0;
info_.nativeVectorWidthHalf_ = info_.preferredVectorWidthHalf_ = 0; // no half support
info_.maxClockFrequency_ = (palProp.gfxipProperties.performance.maxGpuClock != 0)
info_.maxEngineClockFrequency_ = (palProp.gfxipProperties.performance.maxGpuClock != 0)
? palProp.gfxipProperties.performance.maxGpuClock
: 555;
info_.maxMemoryClockFrequency_ = (palProp.gpuMemoryProperties.performance.maxMemClock != 0)
? palProp.gpuMemoryProperties.performance.maxMemClock
: 555;
info_.vramBusBitWidth_ = palProp.gpuMemoryProperties.performance.vramBusBitWidth;
info_.l2CacheSize_ = palProp.gfxipProperties.shaderCore.tccSizeInBytes;
info_.maxParameterSize_ = 1024;
info_.minDataTypeAlignSize_ = sizeof(cl_long16);
info_.singleFPConfig_ =
@@ -515,13 +520,15 @@ void NullDevice::fillDeviceInfo(const Pal::DeviceProperties& palProp,
info_.simdWidth_ = hwInfo()->simdWidth_;
info_.simdInstructionWidth_ = hwInfo()->simdInstructionWidth_;
info_.wavefrontWidth_ = palProp.gfxipProperties.shaderCore.wavefrontSize;
info_.globalMemChannels_ = palProp.gpuMemoryProperties.performance.vramBusBitWidth / 32;
info_.availableSGPRs_ = palProp.gfxipProperties.shaderCore.numAvailableSgprs;
info_.globalMemChannelBanks_ = 4;
info_.globalMemChannelBankWidth_ = hwInfo()->memChannelBankWidth_;
info_.localMemSizePerCU_ = hwInfo()->localMemSizePerCU_;
info_.localMemBanks_ = hwInfo()->localMemBanks_;
info_.gfxipVersion_ = hwInfo()->gfxipVersion_;
info_.timeStampFrequency_ = 1000000;
info_.numAsyncQueues_ = numComputeRings;
info_.numRTQueues_ = numExclusiveComputeRings;
projects/clr/rocclr/runtime/device/pal/palvirtual.cpp
+3 -3
Näytä tiedosto
@@ -479,7 +479,7 @@ void VirtualGPU::MemoryDependency::clear(bool all) {
VirtualGPU::DmaFlushMgmt::DmaFlushMgmt(const Device& dev) : cbWorkload_(0), dispatchSplitSize_(0) {
aluCnt_ = dev.info().simdPerCU_ * dev.info().simdWidth_ * dev.info().maxComputeUnits_;
maxDispatchWorkload_ = static_cast<uint64_t>(dev.info().maxClockFrequency_) *
maxDispatchWorkload_ = static_cast<uint64_t>(dev.info().maxEngineClockFrequency_) *
// find time in us
dev.settings().maxWorkloadTime_ * aluCnt_;
resetCbWorkload(dev);
@@ -487,7 +487,7 @@ VirtualGPU::DmaFlushMgmt::DmaFlushMgmt(const Device& dev) : cbWorkload_(0), disp
void VirtualGPU::DmaFlushMgmt::resetCbWorkload(const Device& dev) {
cbWorkload_ = 0;
maxCbWorkload_ = static_cast<uint64_t>(dev.info().maxClockFrequency_) *
maxCbWorkload_ = static_cast<uint64_t>(dev.info().maxEngineClockFrequency_) *
// find time in us
dev.settings().minWorkloadTime_ * aluCnt_;
}
@@ -2010,7 +2010,7 @@ void VirtualGPU::PostDeviceEnqueue(
gpuDefQueue->schedParams_->data())[gpuDefQueue->schedParamIdx_];
param->signal = 1;
// Scale clock to 1024 to avoid 64 bit div in the scheduler
param->eng_clk = (1000 * 1024) / dev().info().maxClockFrequency_;
param->eng_clk = (1000 * 1024) / dev().info().maxEngineClockFrequency_;
param->hw_queue = patchStart + sizeof(uint32_t) /* Rewind packet*/;
param->hsa_queue = gpuDefQueue->hsaQueueMem()->vmAddress();
param->releaseHostCP = 0;
projects/clr/rocclr/runtime/device/rocm/rocdevice.cpp
+17 -4
Näytä tiedosto
@@ -813,13 +813,19 @@ bool Device::populateOCLDeviceConstants() {
if (HSA_STATUS_SUCCESS !=
hsa_agent_get_info(_bkendDevice, (hsa_agent_info_t)HSA_AMD_AGENT_INFO_MAX_CLOCK_FREQUENCY,
&info_.maxClockFrequency_)) {
&info_.maxEngineClockFrequency_)) {
return false;
}
//TODO: add the assert statement for Raven
if (deviceInfo_.gfxipVersion_ != 902) {
assert(info_.maxClockFrequency_ > 0);
assert(info_.maxEngineClockFrequency_ > 0);
}
if (HSA_STATUS_SUCCESS !=
hsa_agent_get_info(_bkendDevice, (hsa_agent_info_t)HSA_AMD_AGENT_INFO_MEMORY_MAX_FREQUENCY,
&info_.maxMemoryClockFrequency_)) {
return false;
}
if (HSA_STATUS_SUCCESS !=
@@ -1123,10 +1129,17 @@ bool Device::populateOCLDeviceConstants() {
return false;
}
if (HSA_STATUS_SUCCESS !=
hsa_agent_get_info(_bkendDevice, (hsa_agent_info_t)HSA_AMD_AGENT_INFO_MEMORY_WIDTH, &info_.globalMemChannels_)) {
hsa_agent_get_info(_bkendDevice, (hsa_agent_info_t)HSA_AMD_AGENT_INFO_MEMORY_WIDTH, &info_.vramBusBitWidth_)) {
return false;
}
info_.globalMemChannels_ /= 32;
uint32_t cache_sizes[4];
/* FIXIT [skudchad] - Seems like hardcoded in HSA backend so 0*/
if (HSA_STATUS_SUCCESS !=
hsa_agent_get_info(_bkendDevice, (hsa_agent_info_t)HSA_AGENT_INFO_CACHE_SIZE, cache_sizes)) {
return false;
}
info_.l2CacheSize_ = cache_sizes[1];
info_.timeStampFrequency_ = 1000000;
info_.globalMemChannelBanks_ = 4;
info_.globalMemChannelBankWidth_ = deviceInfo_.memChannelBankWidth_;
info_.localMemSizePerCU_ = deviceInfo_.localMemSizePerCU_;