Improve LL performance (#546)
* Improve LL performance
* Add split barriers for LL
[ROCm/rccl commit: c9919e0e35]
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@@ -41,9 +41,13 @@ class Primitives<T, RedOp, Fan, Direct, ProtoLL, P2p>:
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inline __device__ uint32_t recvFlag(int i) { return NCCL_LL_FLAG(recvStep[i]+1); }
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inline __device__ uint32_t sendFlag(int i) { return NCCL_LL_FLAG(sendStep[i]+1); }
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uint64_t* barriers;
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uint64_t* barrier_next;
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inline __device__ void barrier() {
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#if defined(__HIP_PLATFORM_HCC__) || defined(__HCC__) || defined(__HIPCC__)
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__syncthreads();
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if (nthreads != WARP_SIZE)
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barrier_by_group();
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#else
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asm volatile ("bar.sync %1, %0;" :: "r"(nthreads), "r"(15-group));
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#endif
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@@ -86,7 +90,7 @@ class Primitives<T, RedOp, Fan, Direct, ProtoLL, P2p>:
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}
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inline __device__ void postRecv() {
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barrier();
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if (recvConnHeadPtr) STORE(recvConnHeadPtr, recvConnHead += 1);
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if (recvConnHeadPtr) atomicExch_system((unsigned long long *)recvConnHeadPtr, recvConnHead += 1);
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}
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inline __device__ void incSend(int i, int offset) {
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@@ -385,6 +389,8 @@ class Primitives<T, RedOp, Fan, Direct, ProtoLL, P2p>:
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redOp(redOpArg),
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tid(tid), nthreads(nthreads), wid(tid%WARP_SIZE), group(group&(uint16_t)0xFFFF),
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stepLines(ncclShmem->comm.buffSizes[NCCL_PROTO_LL]/NCCL_STEPS/sizeof(ncclLLFifoLine)) {
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barriers = &ncclShmem->groups[this->group].barrier;
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barrier_next = ncclShmem->groups[this->group].barrier_next;
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auto *channel = &ncclShmem->channel;
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// If we are going to support oneshot collNet + LL, then we would need to add connector index here
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