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[SWDEV-528647/SWDEV-528450] Reduce API load times and libdrm/libdrm_amdgpu dynamic loading (#333)

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Changes:
- Removed libdrm/libdrm_amdgpu dependencies
- Added/updated new internal libdrm/libdrm_amdgpu/xf86drm APIs
  to allow our APIs to reference before dynamic loading
  the libdrm/libdrm_amdgpu libraries:
  1. amdgpu_drm.h to what's seen in mainline
  2. Added xf86drm.h to whats seen in mainline
- Modified internal DRM capabilities:
  1. Require each API to independently connect to libdrm/libdrm_amdgpu
     + validate API handles reponses accordingly
  2. Initialization of AMD SMI no longer has as strong of a tie to
     libdrm
- Updated internal implementations of several APIs which have
connections to libdrm/libdrm_amdgpu or APIs which have conflicts
with open libdrm/libdrm_amdgpu connections:
  1. amdsmi_init()
  2. amdsmi_get_gpu_vram_usage()
  3. amdsmi_get_gpu_asic_info()
  4. amdsmi_get_gpu_vram_info()
  5. amdsmi_get_gpu_vbios_info()
  6. amdsmi_get_gpu_driver_info()
  7. amdsmi_get_gpu_virtualization_mode()
  8. amdsmi_set_gpu_memory_partition()
  9. amdsmi_set_gpu_memory_partition_mode()
- Cleaned up effected tests/APIs

Change-Id: I96e2cf1b06b0cfee1b01a5e991ccc6116c4245a8
This commit is contained in:
Poag, Charis
2025-05-02 21:58:53 -05:00
zatwierdzone przez GitHub
rodzic 757aa016f4
commit b5a43b7744
25 zmienionych plików z 2264 dodań i 629 usunięć
Ściągnij plik aktualizacji Ściągnij plik porównania Expand all files Collapse all files
CMakeLists.txt
+30 -21
Wyświetl plik
@@ -1,6 +1,12 @@
message("&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&")
message(" CMake AMD SMI (Library) [root] ")
message("&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&")
#
# Minimum version of cmake required
#
## Verbose output.
set(CMAKE_VERBOSE_MAKEFILE on)
cmake_minimum_required(VERSION 3.20)
set(AMD_SMI "amd_smi")
@@ -169,27 +175,26 @@ if(ENABLE_ESMI_LIB)
endif()
# sets DRM_LIBRARIES and DRM_INCLUDE_DIRS
pkg_check_modules(DRM REQUIRED libdrm)
# sets AMDGPU_DRM_LIBRARIES and AMDGPU_DRM_INCLUDE_DIRS
pkg_check_modules(AMDGPU_DRM REQUIRED libdrm_amdgpu)
include_directories(${CMAKE_CURRENT_SOURCE_DIR}/include ${CMAKE_CURRENT_SOURCE_DIR}/third_party/shared_mutex
${CMAKE_CURRENT_SOURCE_DIR}/include/amd_smi ${ESMI_INC_DIR} ${DRM_INCLUDE_DIRS})
${CMAKE_CURRENT_SOURCE_DIR}/include/amd_smi ${ESMI_INC_DIR})
set(CMN_SRC_LIST
"${ROCM_SRC_DIR}/rocm_smi.cc"
"${ROCM_SRC_DIR}/rocm_smi_counters.cc"
"${ROCM_SRC_DIR}/rocm_smi_device.cc"
"${ROCM_SRC_DIR}/rocm_smi_gpu_metrics.cc"
"${ROCM_SRC_DIR}/rocm_smi_binary_parser.cc"
"${ROCM_SRC_DIR}/rocm_smi_io_link.cc"
"${ROCM_SRC_DIR}/rocm_smi_kfd.cc"
"${ROCM_SRC_DIR}/rocm_smi_main.cc"
"${ROCM_SRC_DIR}/rocm_smi_monitor.cc"
"${ROCM_SRC_DIR}/rocm_smi_power_mon.cc"
"${ROCM_SRC_DIR}/rocm_smi_utils.cc"
"${ROCM_SRC_DIR}/rocm_smi_counters.cc"
"${ROCM_SRC_DIR}/rocm_smi_kfd.cc"
"${ROCM_SRC_DIR}/rocm_smi_io_link.cc"
"${ROCM_SRC_DIR}/rocm_smi_gpu_metrics.cc"
"${ROCM_SRC_DIR}/rocm_smi.cc"
"${ROCM_SRC_DIR}/rocm_smi_logger.cc"
"${SHR_MUTEX_DIR}/shared_mutex.cc")
"${SHR_MUTEX_DIR}/shared_mutex.cc"
"${ROCM_SRC_DIR}/rocm_smi_binary_parser.cc")
if(ENABLE_ESMI_LIB)
list(APPEND CMN_SRC_LIST ${ESMI_SRC_DIR}/e_smi.c)
@@ -199,21 +204,21 @@ if(ENABLE_ESMI_LIB)
endif()
set(CMN_INC_LIST
"${ROCM_INC_DIR}/rocm_smi.h"
"${ROCM_INC_DIR}/rocm_smi_common.h"
"${ROCM_INC_DIR}/rocm_smi_counters.h"
"${ROCM_INC_DIR}/rocm_smi_device.h"
"${ROCM_INC_DIR}/rocm_smi_gpu_metrics.h"
"${ROCM_INC_DIR}/rocm_smi_binary_parser.h"
"${ROCM_INC_DIR}/rocm_smi_exception.h"
"${ROCM_INC_DIR}/rocm_smi_io_link.h"
"${ROCM_INC_DIR}/rocm_smi_kfd.h"
"${ROCM_INC_DIR}/rocm_smi_main.h"
"${ROCM_INC_DIR}/rocm_smi_monitor.h"
"${ROCM_INC_DIR}/rocm_smi_power_mon.h"
"${ROCM_INC_DIR}/rocm_smi_utils.h"
"${ROCM_INC_DIR}/rocm_smi_common.h"
"${ROCM_INC_DIR}/rocm_smi_exception.h"
"${ROCM_INC_DIR}/rocm_smi_counters.h"
"${ROCM_INC_DIR}/rocm_smi_kfd.h"
"${ROCM_INC_DIR}/rocm_smi_io_link.h"
"${ROCM_INC_DIR}/rocm_smi_gpu_metrics.h"
"${ROCM_INC_DIR}/rocm_smi.h"
"${ROCM_INC_DIR}/rocm_smi_logger.h"
"${SHR_MUTEX_DIR}/shared_mutex.h")
"${SHR_MUTEX_DIR}/shared_mutex.h"
"${ROCM_INC_DIR}/rocm_smi_binary_parser.h")
add_subdirectory("rocm_smi")
add_subdirectory("src")
@@ -301,7 +306,7 @@ install(
add_subdirectory(goamdsmi_shim)
#Debian package specific variables
set(CPACK_DEBIAN_PACKAGE_RECOMMENDS "python3-argcomplete, libdrm-dev")
set(CPACK_DEBIAN_PACKAGE_RECOMMENDS "python3-argcomplete, libdrm-dev, libdrm-amdgpu-dev")
set(CPACK_DEBIAN_ASAN_PACKAGE_RECOMMENDS ${CPACK_DEBIAN_PACKAGE_RECOMMENDS})
set(CPACK_DEBIAN_DEV_PACKAGE_RECOMMENDS ${CPACK_DEBIAN_PACKAGE_RECOMMENDS})
set(CPACK_DEBIAN_PACKAGE_DEPENDS "sudo, python3 (>= 3.6.8), python3-pip, python3-setuptools, python3-wheel")
@@ -326,7 +331,7 @@ if(CPACK_RPM_PACKAGE_RELEASE)
set(CPACK_RPM_PACKAGE_RELEASE_DIST ON)
endif()
# NOTE: RPM SUGGESTS DO NOT WORK! https://bugzilla.redhat.com/show_bug.cgi?id=1811358
set(CPACK_RPM_PACKAGE_SUGGESTS "python3-argcomplete")
set(CPACK_RPM_PACKAGE_SUGGESTS "python3-argcomplete, libdrm-dev, libdrm-amdgpu-dev")
set(CPACK_RPM_DEV_PACKAGE_SUGGESTS ${CPACK_RPM_PACKAGE_SUGGESTS})
set(CPACK_RPM_ASAN_PACKAGE_SUGGESTS ${CPACK_RPM_PACKAGE_SUGGESTS})
# python version gated by rhel8 :(
@@ -385,3 +390,7 @@ set(CPACK_RPM_FILE_NAME "RPM-DEFAULT")
include(CPack)
generic_package_post()
message("&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&")
message(" CMake AMD SMI (Library) [root] END ")
message("&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&")
README.md
+1 -1
Wyświetl plik
@@ -169,7 +169,7 @@ This section describes the prerequisites and steps to build AMD SMI from source.
To build the AMD SMI library, the following components are required. Note that the software versions specified were used
during development; earlier versions are not guaranteed to work.
* CMake (v3.14.0 or later) -- `python3 -m pip install cmake`
* CMake (v3.15.0 or later) -- `python3 -m pip install cmake`
* g++ (v5.4.0 or later)
* libdrm-dev (for Ubuntu and Debian)
* libdrm-devel (for RPM-based distributions)
amdsmi_cli/CMakeLists.txt
+1 -1
Wyświetl plik
@@ -2,7 +2,7 @@ message("&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&")
message(" CMake AMDSMI CLI Install ")
message("&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&")
set(CMAKE_VERBOSE_MAKEFILE on)
# Set CLI Build Directory
set(PY_PACKAGE_DIR "amdsmi_cli")
set(PY_CLI_INSTALL_DIR
docs/install/build.md
+1 -1
Wyświetl plik
@@ -16,7 +16,7 @@ To build the AMD SMI library, the following components are required. Note that
the software versions specified were used during development; earlier
versions are not guaranteed to work.
* CMake (v3.14.0 or later) -- `python3 -m pip install cmake`
* CMake (v3.15.0 or later) -- `python3 -m pip install cmake`
* g++ (v5.4.0 or later)
* libdrm-dev (for Ubuntu and Debian)
* libdrm-devel (for RPM-based distributions)
example/CMakeLists.txt
+1
Wyświetl plik
@@ -1,3 +1,4 @@
set(CMAKE_VERBOSE_MAKEFILE on)
cmake_minimum_required(VERSION 3.15)
option(ENABLE_ESMI_LIB "Build ESMI Library" ON)
example/amd_smi_drm_example.cc
+47 -2
Wyświetl plik
@@ -255,6 +255,26 @@ mapStringToSMIMemoryPartitionTypes {
{"N/A", AMDSMI_MEMORY_PARTITION_UNKNOWN}
};
static const std::map<amdsmi_virtualization_mode_t, std::string>
virtualization_mode_map = {
{AMDSMI_VIRTUALIZATION_MODE_UNKNOWN, "UNKNOWN"},
{AMDSMI_VIRTUALIZATION_MODE_BAREMETAL, "BAREMETAL"},
{ AMDSMI_VIRTUALIZATION_MODE_HOST, "HOST"},
{ AMDSMI_VIRTUALIZATION_MODE_GUEST, "GUEST"},
{AMDSMI_VIRTUALIZATION_MODE_PASSTHROUGH, "PASSTHROUGH"}
};
static const std::map<processor_type_t, std::string>
processor_type_map = {
{AMDSMI_PROCESSOR_TYPE_UNKNOWN, "UNKNOWN"},
{AMDSMI_PROCESSOR_TYPE_AMD_GPU, "AMD_GPU"},
{AMDSMI_PROCESSOR_TYPE_AMD_CPU, "AMD_CPU"},
{AMDSMI_PROCESSOR_TYPE_NON_AMD_GPU, "NON_AMD_GPU"},
{AMDSMI_PROCESSOR_TYPE_NON_AMD_CPU, "NON_AMD_CPU"},
{AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE, "AMD_CPU_CORE"},
{AMDSMI_PROCESSOR_TYPE_AMD_APU, "AMD_APU"}
};
int main() {
amdsmi_status_t ret, ret_set;
const char *err_str;
@@ -304,7 +324,10 @@ int main() {
// For each device of the socket, get name and temperature.
for (uint32_t device_index = 0; device_index < device_count; device_index++) {
std::cout << "Device Index: " << device_index << std::endl;
#ifdef ENABLE_ESMI_LIB
// Commenting out the code to get CPU socket count and GPU count
// Doesn't work on system with no supported CPU sockets
#if 0
uint32_t cpu_sockets = 0;
uint32_t gpus = 0;
ret = amdsmi_get_processor_count_from_handles(&processor_handles[device_index], &device_count, &cpu_sockets, nullptr, &gpus);
@@ -318,6 +341,13 @@ int main() {
processor_type_t processor_type = {};
ret = amdsmi_get_processor_type(processor_handles[device_index], &processor_type);
CHK_AMDSMI_RET(ret)
auto it = processor_type_map.find(processor_type);
if (it != processor_type_map.end()) {
std::cout << "\t**Processor Type: " << it->second << std::endl;
} else {
std::cout << "\t**Processor Type: MAP TYPE UNKNOWN?" << std::endl;
}
if (processor_type != AMDSMI_PROCESSOR_TYPE_AMD_GPU) {
std::cout << "Expect AMDSMI_PROCESSOR_TYPE_AMD_GPU device type!\n";
return AMDSMI_STATUS_NOT_SUPPORTED;
@@ -359,6 +389,19 @@ int main() {
printf("\tPower Management Enabled: %s\n\n",
(is_power_management_enabled ? "TRUE" : "FALSE"));
amdsmi_virtualization_mode_t vmode;
ret = amdsmi_get_gpu_virtualization_mode(processor_handles[device_index], &vmode);
if (ret != AMDSMI_STATUS_NOT_SUPPORTED) {
CHK_AMDSMI_RET(ret)
}
auto it2 = virtualization_mode_map.find(vmode);
if (it2 != virtualization_mode_map.end()) {
std::cout << "\t**Virtualization Mode: " << it2->second << std::endl;
} else {
std::cout << "\t**Virtualization Mode: MAP TYPE UNKNOWN?" << std::endl;
}
std::cout << " **Version 1: Accelerator/Compute Partition API Examples**\n";
char original_compute_partition[AMDSMI_MAX_STRING_LENGTH];
ret = amdsmi_get_gpu_compute_partition(processor_handles[device_index], original_compute_partition,
@@ -1376,7 +1419,9 @@ int main() {
for (uint32_t k = 0; k < topology_nearest_info.count; k++) {
amdsmi_bdf_t bdf = {};
ret = amdsmi_get_gpu_device_bdf(topology_nearest_info.processor_list[k], &bdf);
CHK_AMDSMI_RET(ret)
if (ret != AMDSMI_STATUS_INVAL) {
CHK_AMDSMI_RET(ret);
}
printf("\t\tGPU BDF %04" PRIx64 ":%02" PRIx32 ":%02" PRIx32 ".%" PRIu32 "\n",
static_cast<uint64_t>(bdf.domain_number),
static_cast<uint32_t>(bdf.bus_number),
include/amd_smi/impl/amd_smi_drm.h
+8 -21
Wyświetl plik
@@ -24,12 +24,16 @@
#define AMD_SMI_INCLUDE_IMPL_AMD_SMI_DRM_H_
#include <unistd.h>
#include <xf86drm.h>
#include <vector>
#include <memory>
#include <mutex> // NOLINT
#include <string>
#include "amd_smi/amdsmi.h"
#include "amd_smi/impl/amd_smi_lib_loader.h"
#include "amd_smi/impl/amdgpu_drm.h"
#include "amd_smi/impl/xf86drm.h"
namespace amd {
namespace smi {
@@ -44,35 +48,18 @@ class AMDSmiDrm {
std::vector<amdsmi_bdf_t> get_bdfs();
std::vector<std::string>& get_drm_paths();
bool check_if_drm_is_supported();
uint32_t get_vendor_id();
amdsmi_status_t amdgpu_query_info(int fd, unsigned info_id,
unsigned size, void *value);
amdsmi_status_t amdgpu_query_fw(int fd, unsigned info_id, unsigned fw_type,
unsigned size, void *value);
amdsmi_status_t amdgpu_query_hw_ip(int fd, unsigned info_id,
unsigned hw_ip_type, unsigned size, void *value);
amdsmi_status_t amdgpu_query_vbios(int fd, void *info);
amdsmi_status_t amdgpu_query_driver_name(int fd, std::string& driver_name);
amdsmi_status_t amdgpu_query_driver_date(int fd, std::string& driver_date);
uint32_t get_vendor_id();
private:
// when file is not found, the empty string will be returned
std::string find_file_in_folder(const std::string& folder,
const std::string& regex);
using DrmCmdWriteFunc = int (*)(int, unsigned long, void *, unsigned long);
std::vector<int> drm_fds_; // drm file descriptor by gpu_index
std::vector<std::string> drm_paths_; // drm path (renderD128 for example)
std::vector<amdsmi_bdf_t> drm_bdfs_; // bdf
std::vector<std::string> drm_paths_; // drm path (renderD128 for example)
std::vector<amdsmi_bdf_t> drm_bdfs_; // bdf
uint32_t vendor_id;
AMDSmiLibraryLoader lib_loader_; // lazy load libdrm
DrmCmdWriteFunc drm_cmd_write_; // drmCommandWrite
using drmGetVersionFunc = drmVersionPtr (*)(int); // drmGetVersion
using drmFreeVersionFunc = void (*)(drmVersionPtr); // drmFreeVersion
drmGetVersionFunc drm_get_version_;
drmFreeVersionFunc drm_free_version_;
std::mutex drm_mutex_;
};
include/amd_smi/impl/amd_smi_gpu_device.h
-10
Wyświetl plik
@@ -71,16 +71,6 @@ class AMDSmiGPUDevice: public AMDSmiProcessor {
return amdgpu_get_compute_process_list(ComputeProcessListType_t::kAllProcesses);
}
amdsmi_status_t amdgpu_query_info(unsigned info_id,
unsigned size, void *value) const;
amdsmi_status_t amdgpu_query_hw_ip(unsigned info_id, unsigned hw_ip_type,
unsigned size, void *value) const;
amdsmi_status_t amdgpu_query_fw(unsigned info_id, unsigned fw_type,
unsigned size, void *value) const;
amdsmi_status_t amdgpu_query_vbios(void *info) const;
amdsmi_status_t amdgpu_query_driver_name(std::string& name) const;
amdsmi_status_t amdgpu_query_driver_date(std::string& date) const;
// New methods for -e feature
std::string bdf_to_string() const; // -e feature
include/amd_smi/impl/amd_smi_system.h
+1 -4
Wyświetl plik
@@ -58,11 +58,8 @@ class AMDSmiSystem {
amdsmi_status_t get_cpu_model(uint32_t *cpu_model);
amdsmi_status_t clean_up_drm() { return drm_.cleanup();}
amdsmi_status_t init_drm() { return drm_.init();}
amdsmi_status_t get_cpu_model_name(uint32_t socket_id, std::string *model_name);
private:
AMDSmiSystem() : init_flag_(AMDSMI_INIT_AMD_GPUS) {}
include/amd_smi/impl/amd_smi_utils.h
+13
Wyświetl plik
@@ -57,6 +57,19 @@ std::string smi_amdgpu_get_status_string(amdsmi_status_t ret, bool fullStatus);
amdsmi_status_t smi_clear_char_and_reinitialize(char buffer[], uint32_t len,
std::string newString);
amdsmi_status_t amdsmi_get_gpu_cper_entries_by_path(const char *amdgpu_ring_cper_file, uint32_t severity_mask, char *cper_data, uint64_t *buf_size, amdsmi_cper_hdr_t **cper_hdrs, uint64_t *entry_count, uint64_t *cursor);
/**
* @brief Wait for user input, a debugging function to pause the program
*
* @details This function will wait for user input before continuing.
* It is useful for debugging purposes to allow the user to inspect the state of the program
* before it continues. The function will print a message to the console and then wait for
* the user to press Enter. Once Enter is pressed, the function will return and the program
* will continue executing.
*
* @note This function is intended for debugging purposes only and should not be used in production code.
* It will block the program execution and cause it to wait indefinitely for user input.
*/
void amdsmi_wait_for_user_input(void);
/**
* @brief Get the device index given the processor handle.
include/amd_smi/impl/amdgpu_drm.h
+237 -136
Wyświetl plik
@@ -17,7 +17,7 @@
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
@@ -29,10 +29,15 @@
* Keith Whitwell <keith@tungstengraphics.com>
*/
#ifndef __AMDGPU_DRM_H__
#define __AMDGPU_DRM_H__
#ifndef __LIBDRM_AMDGPU__
#define __LIBDRM_AMDGPU__
#include <libdrm/amdgpu.h>
#endif
#ifndef __LIBDRM__
#define __LIBDRM__
#include <libdrm/drm.h>
#endif
#if defined(__cplusplus)
extern "C" {
@@ -54,12 +59,6 @@ extern "C" {
#define DRM_AMDGPU_VM 0x13
#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
#define DRM_AMDGPU_SCHED 0x15
/* not upstream */
#define DRM_AMDGPU_FREESYNC 0x5d
#define DRM_AMDGPU_GEM_DGMA 0x5c
/* hybrid specific ioctls */
#define DRM_AMDGPU_SEM 0x5b
#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -77,9 +76,6 @@ extern "C" {
#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
#define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync)
#define DRM_IOCTL_AMDGPU_GEM_DGMA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_DGMA, struct drm_amdgpu_gem_dgma)
/**
* DOC: memory domains
@@ -89,7 +85,7 @@ extern "C" {
*
* %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the
* GPU's virtual address space via gart. Gart memory linearizes non-contiguous
* pages of system memory, allows GPU access system memory in a linezrized
* pages of system memory, allows GPU access system memory in a linearized
* fashion.
*
* %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory
@@ -103,28 +99,24 @@ extern "C" {
*
* %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines
* for appending data.
*
* %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for
* signalling user mode queues.
*/
/* hybrid specific ioctls */
#define DRM_IOCTL_AMDGPU_SEM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_SEM, union drm_amdgpu_sem)
#define AMDGPU_GEM_DOMAIN_CPU 0x1
#define AMDGPU_GEM_DOMAIN_GTT 0x2
#define AMDGPU_GEM_DOMAIN_VRAM 0x4
#define AMDGPU_GEM_DOMAIN_GDS 0x8
#define AMDGPU_GEM_DOMAIN_GWS 0x10
#define AMDGPU_GEM_DOMAIN_OA 0x20
#define AMDGPU_GEM_DOMAIN_DGMA 0x40
#define AMDGPU_GEM_DOMAIN_DGMA_IMPORT 0x80
#define AMDGPU_GEM_DOMAIN_DGMA_PEER 0x100 /* verylike DGMA_IMPORT but it doesn't consume domain0 GART space */
#define AMDGPU_GEM_DOMAIN_DOORBELL 0x40
#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
AMDGPU_GEM_DOMAIN_GTT | \
AMDGPU_GEM_DOMAIN_VRAM | \
AMDGPU_GEM_DOMAIN_GDS | \
AMDGPU_GEM_DOMAIN_GWS | \
AMDGPU_GEM_DOMAIN_OA |\
AMDGPU_GEM_DOMAIN_DGMA |\
AMDGPU_GEM_DOMAIN_DGMA_IMPORT |\
AMDGPU_GEM_DOMAIN_DGMA_PEER)
AMDGPU_GEM_DOMAIN_OA | \
AMDGPU_GEM_DOMAIN_DOORBELL)
/* Flag that CPU access will be required for the case of VRAM domain */
#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
@@ -134,8 +126,6 @@ extern "C" {
#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
/* Flag that the memory should be in VRAM and cleared */
#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
/* Flag that create shadow bo(GTT) while allocating vram bo */
#define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
/* Flag that allocating the BO should use linear VRAM */
#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
/* Flag that BO is always valid in this VM */
@@ -156,14 +146,38 @@ extern "C" {
* accessing it with various hw blocks
*/
#define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10)
/* hybrid specific */
/* Flag that the memory should be in SPARSE resource */
#define AMDGPU_GEM_CREATE_SPARSE (1ULL << 29)
/* Flag that the memory allocation should be from top of domain */
#define AMDGPU_GEM_CREATE_TOP_DOWN (1ULL << 30)
/* Flag that the memory allocation should be pinned */
#define AMDGPU_GEM_CREATE_NO_EVICT (1ULL << 31)
/* Flag that BO will be used only in preemptible context, which does
* not require GTT memory accounting
*/
#define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11)
/* Flag that BO can be discarded under memory pressure without keeping the
* content.
*/
#define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12)
/* Flag that BO is shared coherently between multiple devices or CPU threads.
* May depend on GPU instructions to flush caches to system scope explicitly.
*
* This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
* may override the MTYPE selected in AMDGPU_VA_OP_MAP.
*/
#define AMDGPU_GEM_CREATE_COHERENT (1 << 13)
/* Flag that BO should not be cached by GPU. Coherent without having to flush
* GPU caches explicitly
*
* This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
* may override the MTYPE selected in AMDGPU_VA_OP_MAP.
*/
#define AMDGPU_GEM_CREATE_UNCACHED (1 << 14)
/* Flag that BO should be coherent across devices when using device-level
* atomics. May depend on GPU instructions to flush caches to device scope
* explicitly, promoting them to system scope automatically.
*
* This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
* may override the MTYPE selected in AMDGPU_VA_OP_MAP.
*/
#define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15)
/* Set PTE.D and recompress during GTT->VRAM moves according to TILING flags. */
#define AMDGPU_GEM_CREATE_GFX12_DCC (1 << 16)
struct drm_amdgpu_gem_create_in {
/** the requested memory size */
@@ -230,6 +244,8 @@ union drm_amdgpu_bo_list {
#define AMDGPU_CTX_OP_FREE_CTX 2
#define AMDGPU_CTX_OP_QUERY_STATE 3
#define AMDGPU_CTX_OP_QUERY_STATE2 4
#define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5
#define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6
/* GPU reset status */
#define AMDGPU_CTX_NO_RESET 0
@@ -240,15 +256,17 @@ union drm_amdgpu_bo_list {
/* unknown cause */
#define AMDGPU_CTX_UNKNOWN_RESET 3
/* indicate gpu reset occured after ctx created */
/* indicate gpu reset occurred after ctx created */
#define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)
/* indicate vram lost occured after ctx created */
/* indicate vram lost occurred after ctx created */
#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
/* indicate some job from this context once cause gpu hang */
#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
/* indicate some errors are detected by RAS */
#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3)
#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4)
/* indicate that the reset hasn't completed yet */
#define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5)
/* Context priority level */
#define AMDGPU_CTX_PRIORITY_UNSET -2048
@@ -262,10 +280,18 @@ union drm_amdgpu_bo_list {
#define AMDGPU_CTX_PRIORITY_HIGH 512
#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
/* select a stable profiling pstate for perfmon tools */
#define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf
#define AMDGPU_CTX_STABLE_PSTATE_NONE 0
#define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1
#define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2
#define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3
#define AMDGPU_CTX_STABLE_PSTATE_PEAK 4
struct drm_amdgpu_ctx_in {
/** AMDGPU_CTX_OP_* */
__u32 op;
/** For future use, no flags defined so far */
/** Flags */
__u32 flags;
__u32 ctx_id;
/** AMDGPU_CTX_PRIORITY_* */
@@ -286,6 +312,11 @@ union drm_amdgpu_ctx_out {
/** Reset status since the last call of the ioctl. */
__u32 reset_status;
} state;
struct {
__u32 flags;
__u32 _pad;
} pstate;
};
union drm_amdgpu_ctx {
@@ -293,35 +324,6 @@ union drm_amdgpu_ctx {
union drm_amdgpu_ctx_out out;
};
/* sem related */
#define AMDGPU_SEM_OP_CREATE_SEM 1
#define AMDGPU_SEM_OP_WAIT_SEM 2
#define AMDGPU_SEM_OP_SIGNAL_SEM 3
#define AMDGPU_SEM_OP_DESTROY_SEM 4
#define AMDGPU_SEM_OP_IMPORT_SEM 5
#define AMDGPU_SEM_OP_EXPORT_SEM 6
struct drm_amdgpu_sem_in {
/** AMDGPU_SEM_OP_* */
uint32_t op;
uint32_t handle;
uint32_t ctx_id;
uint32_t ip_type;
uint32_t ip_instance;
uint32_t ring;
uint64_t seq;
};
union drm_amdgpu_sem_out {
int32_t fd;
uint32_t handle;
};
union drm_amdgpu_sem {
struct drm_amdgpu_sem_in in;
union drm_amdgpu_sem_out out;
};
/* vm ioctl */
#define AMDGPU_VM_OP_RESERVE_VMID 1
#define AMDGPU_VM_OP_UNRESERVE_VMID 2
@@ -368,7 +370,6 @@ union drm_amdgpu_sched {
#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
#define AMDGPU_GEM_USERPTR_PEERMEM (1 << 4)
struct drm_amdgpu_gem_userptr {
__u64 addr;
@@ -379,15 +380,6 @@ struct drm_amdgpu_gem_userptr {
__u32 handle;
};
#define AMDGPU_GEM_DGMA_IMPORT 0
#define AMDGPU_GEM_DGMA_QUERY_PHYS_ADDR 1
struct drm_amdgpu_gem_dgma {
__u64 addr;
__u64 size;
__u32 op;
__u32 handle;
};
/* SI-CI-VI: */
/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
@@ -407,7 +399,7 @@ struct drm_amdgpu_gem_dgma {
#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
/* GFX9 and later: */
/* GFX9 - GFX11: */
#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5
@@ -416,6 +408,28 @@ struct drm_amdgpu_gem_dgma {
#define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF
#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43
#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1
#define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44
#define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1
#define AMDGPU_TILING_SCANOUT_SHIFT 63
#define AMDGPU_TILING_SCANOUT_MASK 0x1
/* GFX12 and later: */
#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0
#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7
/* These are DCC recompression settings for memory management: */
#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3
#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */
#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5
#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */
#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8
#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */
/* When clearing the buffer or moving it from VRAM to GTT, don't compress and set DCC metadata
* to uncompressed. Set when parts of an allocation bypass DCC and read raw data. */
#define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_SHIFT 14
#define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_MASK 0x1
/* bit gap */
#define AMDGPU_TILING_GFX12_SCANOUT_SHIFT 63
#define AMDGPU_TILING_GFX12_SCANOUT_MASK 0x1
/* Set/Get helpers for tiling flags. */
#define AMDGPU_TILING_SET(field, value) \
@@ -563,16 +577,18 @@ struct drm_amdgpu_gem_op {
#define AMDGPU_VM_MTYPE_MASK (0xf << 5)
/* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */
#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
/* Use NC MTYPE instead of default MTYPE */
/* Use Non Coherent MTYPE instead of default MTYPE */
#define AMDGPU_VM_MTYPE_NC (1 << 5)
/* Use WC MTYPE instead of default MTYPE */
/* Use Write Combine MTYPE instead of default MTYPE */
#define AMDGPU_VM_MTYPE_WC (2 << 5)
/* Use CC MTYPE instead of default MTYPE */
/* Use Cache Coherent MTYPE instead of default MTYPE */
#define AMDGPU_VM_MTYPE_CC (3 << 5)
/* Use UC MTYPE instead of default MTYPE */
/* Use UnCached MTYPE instead of default MTYPE */
#define AMDGPU_VM_MTYPE_UC (4 << 5)
/* Use RW MTYPE instead of default MTYPE */
/* Use Read Write MTYPE instead of default MTYPE */
#define AMDGPU_VM_MTYPE_RW (5 << 5)
/* don't allocate MALL */
#define AMDGPU_VM_PAGE_NOALLOC (1 << 9)
struct drm_amdgpu_gem_va {
/** GEM object handle */
@@ -597,9 +613,14 @@ struct drm_amdgpu_gem_va {
#define AMDGPU_HW_IP_VCE 4
#define AMDGPU_HW_IP_UVD_ENC 5
#define AMDGPU_HW_IP_VCN_DEC 6
/*
* From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support
* both encoding and decoding jobs.
*/
#define AMDGPU_HW_IP_VCN_ENC 7
#define AMDGPU_HW_IP_VCN_JPEG 8
#define AMDGPU_HW_IP_NUM 9
#define AMDGPU_HW_IP_VPE 9
#define AMDGPU_HW_IP_NUM 10
#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
@@ -612,6 +633,7 @@ struct drm_amdgpu_gem_va {
#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08
#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09
#define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a
struct drm_amdgpu_cs_chunk {
__u32 chunk_id;
@@ -663,6 +685,10 @@ union drm_amdgpu_cs {
*/
#define AMDGPU_IB_FLAGS_SECURE (1 << 5)
/* Tell KMD to flush and invalidate caches
*/
#define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6)
struct drm_amdgpu_cs_chunk_ib {
__u32 _pad;
/** AMDGPU_IB_FLAG_* */
@@ -724,7 +750,16 @@ struct drm_amdgpu_cs_chunk_data {
};
};
/**
#define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1
struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
__u64 shadow_va;
__u64 csa_va;
__u64 gds_va;
__u64 flags;
};
/*
* Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
*
*/
@@ -792,7 +827,22 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_FW_TA 0x13
/* Subquery id: Query DMCUB firmware version */
#define AMDGPU_INFO_FW_DMCUB 0x14
#define AMDGPU_INFO_FW_CAP 0x15
/* Subquery id: Query TOC firmware version */
#define AMDGPU_INFO_FW_TOC 0x15
/* Subquery id: Query CAP firmware version */
#define AMDGPU_INFO_FW_CAP 0x16
/* Subquery id: Query GFX RLCP firmware version */
#define AMDGPU_INFO_FW_GFX_RLCP 0x17
/* Subquery id: Query GFX RLCV firmware version */
#define AMDGPU_INFO_FW_GFX_RLCV 0x18
/* Subquery id: Query MES_KIQ firmware version */
#define AMDGPU_INFO_FW_MES_KIQ 0x19
/* Subquery id: Query MES firmware version */
#define AMDGPU_INFO_FW_MES 0x1a
/* Subquery id: Query IMU firmware version */
#define AMDGPU_INFO_FW_IMU 0x1b
/* Subquery id: Query VPE firmware version */
#define AMDGPU_INFO_FW_VPE 0x1c
/* number of bytes moved for TTM migration */
#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
@@ -846,12 +896,17 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8
/* Subquery id: Query GPU stable pstate memory clock */
#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9
/* Subquery id: Query GPU peak pstate shader clock */
#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa
/* Subquery id: Query GPU peak pstate memory clock */
#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb
/* Subquery id: Query input GPU power */
#define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc
/* Number of VRAM page faults on CPU access. */
#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
/* query ras mask of enabled features*/
#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
/* RAS MASK: UMC (VRAM) */
#define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)
/* RAS MASK: SDMA */
@@ -880,18 +935,16 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)
/* RAS MASK: FUSE */
#define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)
/* Hybrid Stack Specific Defs*/
/* gpu capability */
#define AMDGPU_INFO_CAPABILITY 0x50
/* virtual range */
#define AMDGPU_INFO_VIRTUAL_RANGE 0x51
/* query pin memory capability */
#define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0)
/* query direct gma capability */
#define AMDGPU_CAPABILITY_DIRECT_GMA_FLAG (1 << 1)
/* query ssg capability */
#define AMDGPU_CAPABILITY_SSG_FLAG (1 << 2)
/* query video encode/decode caps */
#define AMDGPU_INFO_VIDEO_CAPS 0x21
/* Subquery id: Decode */
#define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
/* Subquery id: Encode */
#define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
/* Query the max number of IBs per gang per submission */
#define AMDGPU_INFO_MAX_IBS 0x22
/* query last page fault info */
#define AMDGPU_INFO_GPUVM_FAULT 0x23
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
@@ -949,11 +1002,6 @@ struct drm_amdgpu_info {
__u32 flags;
} read_mmr_reg;
struct {
uint32_t aperture;
uint32_t _pad;
} virtual_range;
struct drm_amdgpu_query_fw query_fw;
struct {
@@ -964,6 +1012,10 @@ struct drm_amdgpu_info {
struct {
__u32 type;
} sensor_info;
struct {
__u32 type;
} video_cap;
};
};
@@ -1043,8 +1095,9 @@ struct drm_amdgpu_info_vbios {
#define AMDGPU_VRAM_TYPE_DDR3 7
#define AMDGPU_VRAM_TYPE_DDR4 8
#define AMDGPU_VRAM_TYPE_GDDR6 9
#define AMDGPU_VRAM_TYPE_HBM_WIDTH 4096
#define AMDGPU_VRAM_TYPE_DDR5 10
#define AMDGPU_VRAM_TYPE_LPDDR4 11
#define AMDGPU_VRAM_TYPE_LPDDR5 12
struct drm_amdgpu_info_device {
/** PCI Device ID */
@@ -1070,8 +1123,9 @@ struct drm_amdgpu_info_device {
__u32 enabled_rb_pipes_mask;
__u32 num_rb_pipes;
__u32 num_hw_gfx_contexts;
__u32 _pad;
__u64 ids_flags; // Relevant info here REMOVE LATER
/* PCIe version (the smaller of the GPU and the CPU/motherboard) */
__u32 pcie_gen;
__u64 ids_flags;
/** Starting virtual address for UMDs. */
__u64 virtual_address_offset;
/** The maximum virtual address */
@@ -1117,7 +1171,8 @@ struct drm_amdgpu_info_device {
__u32 gs_prim_buffer_depth;
/* max gs wavefront per vgt*/
__u32 max_gs_waves_per_vgt;
__u32 _pad1;
/* PCIe number of lanes (the smaller of the GPU and the CPU/motherboard) */
__u32 pcie_num_lanes;
/* always on cu bitmap */
__u32 cu_ao_bitmap[4][4];
/** Starting high virtual address for UMDs. */
@@ -1128,6 +1183,26 @@ struct drm_amdgpu_info_device {
__u32 pa_sc_tile_steering_override;
/* disabled TCCs */
__u64 tcc_disabled_mask;
__u64 min_engine_clock;
__u64 min_memory_clock;
/* The following fields are only set on gfx11+, older chips set 0. */
__u32 tcp_cache_size; /* AKA GL0, VMEM cache */
__u32 num_sqc_per_wgp;
__u32 sqc_data_cache_size; /* AKA SMEM cache */
__u32 sqc_inst_cache_size;
__u32 gl1c_cache_size;
__u32 gl2c_cache_size;
__u64 mall_size; /* AKA infinity cache */
/* high 32 bits of the rb pipes mask */
__u32 enabled_rb_pipes_mask_hi;
/* shadow area size for gfx11 */
__u32 shadow_size;
/* shadow area base virtual alignment for gfx11 */
__u32 shadow_alignment;
/* context save area size for gfx11 */
__u32 csa_size;
/* context save area base virtual alignment for gfx11 */
__u32 csa_alignment;
};
struct drm_amdgpu_info_hw_ip {
@@ -1142,7 +1217,8 @@ struct drm_amdgpu_info_hw_ip {
__u32 ib_size_alignment;
/** Bitmask of available rings. Bit 0 means ring 0, etc. */
__u32 available_rings;
__u32 _pad;
/** version info: bits 23:16 major, 15:8 minor, 7:0 revision */
__u32 ip_discovery_version;
};
struct drm_amdgpu_info_num_handles {
@@ -1170,6 +1246,44 @@ struct drm_amdgpu_info_vce_clock_table {
__u32 pad;
};
/* query video encode/decode caps */
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8
struct drm_amdgpu_info_video_codec_info {
__u32 valid;
__u32 max_width;
__u32 max_height;
__u32 max_pixels_per_frame;
__u32 max_level;
__u32 pad;
};
struct drm_amdgpu_info_video_caps {
struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT];
};
#define AMDGPU_VMHUB_TYPE_MASK 0xff
#define AMDGPU_VMHUB_TYPE_SHIFT 0
#define AMDGPU_VMHUB_TYPE_GFX 0
#define AMDGPU_VMHUB_TYPE_MM0 1
#define AMDGPU_VMHUB_TYPE_MM1 2
#define AMDGPU_VMHUB_IDX_MASK 0xff00
#define AMDGPU_VMHUB_IDX_SHIFT 8
struct drm_amdgpu_info_gpuvm_fault {
__u64 addr;
__u32 status;
__u32 vmhub;
};
/*
* Supported GPU families
*/
@@ -1182,37 +1296,24 @@ struct drm_amdgpu_info_vce_clock_table {
#define AMDGPU_FAMILY_AI 141 /* Vega10 */
#define AMDGPU_FAMILY_RV 142 /* Raven */
#define AMDGPU_FAMILY_NV 143 /* Navi10 */
#define AMDGPU_FAMILY_VGH 144 /* Van Gogh */
#define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */
#define AMDGPU_FAMILY_YC 146 /* Yellow Carp */
#define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */
#define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */
#define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */
#define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */
#define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */
/**
* Definition of System Unified Address (SUA) apertures
*/
#define AMDGPU_SUA_APERTURE_PRIVATE 1
#define AMDGPU_SUA_APERTURE_SHARED 2
struct drm_amdgpu_virtual_range {
uint64_t start;
uint64_t end;
};
struct drm_amdgpu_capability {
__u32 flag;
__u32 direct_gma_size;
};
/*
* Definition of free sync enter and exit signals
* We may have more options in the future
*/
#define AMDGPU_FREESYNC_FULLSCREEN_ENTER 1
#define AMDGPU_FREESYNC_FULLSCREEN_EXIT 2
struct drm_amdgpu_freesync {
__u32 op; /* AMDGPU_FREESYNC_FULLSCREEN_ENTER or */
/* AMDGPU_FREESYNC_FULLSCREEN_ENTER */
__u32 spare[7];
/* FIXME wrong namespace! */
struct drm_color_ctm_3x4 {
/*
* Conversion matrix with 3x4 dimensions in S31.32 sign-magnitude
* (not two's complement!) format.
*/
__u64 matrix[12];
};
#if defined(__cplusplus)
}
#endif
#endif
include/amd_smi/impl/xf86drm.h
+986
Wyświetl plik
@@ -0,0 +1,986 @@
/**
* \file xf86drm.h
* OS-independent header for DRM user-level library interface.
*
* \author Rickard E. (Rik) Faith <faith@valinux.com>
*/
/*
* Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas.
* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _XF86DRM_H_
#define _XF86DRM_H_
#include <stdarg.h>
#include <sys/types.h>
#include <stdint.h>
#ifndef __LIBDRM__
#define __LIBDRM__
#include <libdrm/drm.h>
#endif
#if defined(__cplusplus)
extern "C" {
#endif
#ifndef DRM_MAX_MINOR
#define DRM_MAX_MINOR 64 /* deprecated */
#endif
#if defined(__linux__)
#define DRM_IOCTL_NR(n) _IOC_NR(n)
#define DRM_IOC_VOID _IOC_NONE
#define DRM_IOC_READ _IOC_READ
#define DRM_IOC_WRITE _IOC_WRITE
#define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE
#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
#else /* One of the *BSDs */
#include <sys/ioccom.h>
#define DRM_IOCTL_NR(n) ((n) & 0xff)
#define DRM_IOC_VOID IOC_VOID
#define DRM_IOC_READ IOC_OUT
#define DRM_IOC_WRITE IOC_IN
#define DRM_IOC_READWRITE IOC_INOUT
#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
#endif
/* Defaults, if nothing set in xf86config */
#define DRM_DEV_UID 0
#define DRM_DEV_GID 0
/* Default /dev/dri directory permissions 0755 */
#define DRM_DEV_DIRMODE \
(S_IRUSR|S_IWUSR|S_IXUSR|S_IRGRP|S_IXGRP|S_IROTH|S_IXOTH)
#define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
#ifdef __OpenBSD__
#define DRM_DIR_NAME "/dev"
#define DRM_PRIMARY_MINOR_NAME "drm"
#define DRM_CONTROL_MINOR_NAME "drmC" /* deprecated */
#define DRM_RENDER_MINOR_NAME "drmR"
#else
#define DRM_DIR_NAME "/dev/dri"
#define DRM_PRIMARY_MINOR_NAME "card"
#define DRM_CONTROL_MINOR_NAME "controlD" /* deprecated */
#define DRM_RENDER_MINOR_NAME "renderD"
#define DRM_PROC_NAME "/proc/dri/" /* For backward Linux compatibility */
#endif
#define DRM_DEV_NAME "%s/" DRM_PRIMARY_MINOR_NAME "%d"
#define DRM_CONTROL_DEV_NAME "%s/" DRM_CONTROL_MINOR_NAME "%d" /* deprecated */
#define DRM_RENDER_DEV_NAME "%s/" DRM_RENDER_MINOR_NAME "%d"
#define DRM_NODE_NAME_MAX \
(sizeof(DRM_DIR_NAME) + 1 /* slash */ \
+ MAX3(sizeof(DRM_PRIMARY_MINOR_NAME), \
sizeof(DRM_CONTROL_MINOR_NAME), \
sizeof(DRM_RENDER_MINOR_NAME)) \
+ sizeof("1048575") /* highest possible node number 2^MINORBITS - 1 */ \
+ 1) /* NULL-terminator */
#define DRM_ERR_NO_DEVICE (-1001)
#define DRM_ERR_NO_ACCESS (-1002)
#define DRM_ERR_NOT_ROOT (-1003)
#define DRM_ERR_INVALID (-1004)
#define DRM_ERR_NO_FD (-1005)
#define DRM_AGP_NO_HANDLE 0
typedef unsigned int drmSize, *drmSizePtr; /**< For mapped regions */
typedef void *drmAddress, **drmAddressPtr; /**< For mapped regions */
#if (__GNUC__ >= 3)
#define DRM_PRINTFLIKE(f, a) __attribute__ ((format(__printf__, f, a)))
#else
#define DRM_PRINTFLIKE(f, a)
#endif
typedef struct _drmServerInfo {
int (*debug_print)(const char *format, va_list ap) DRM_PRINTFLIKE(1,0);
int (*load_module)(const char *name);
void (*get_perms)(gid_t *, mode_t *);
} drmServerInfo, *drmServerInfoPtr;
typedef struct drmHashEntry {
int fd;
void (*f)(int, void *, void *);
void *tagTable;
} drmHashEntry;
extern int drmIoctl(int fd, unsigned long request, void *arg);
extern void *drmGetHashTable(void);
extern drmHashEntry *drmGetEntry(int fd);
/**
* Driver version information.
*
* \sa drmGetVersion() and drmSetVersion().
*/
typedef struct _drmVersion {
int version_major; /**< Major version */
int version_minor; /**< Minor version */
int version_patchlevel; /**< Patch level */
int name_len; /**< Length of name buffer */
char *name; /**< Name of driver */
int date_len; /**< Length of date buffer */
char *date; /**< User-space buffer to hold date */
int desc_len; /**< Length of desc buffer */
char *desc; /**< User-space buffer to hold desc */
} drmVersion, *drmVersionPtr;
typedef struct _drmStats {
unsigned long count; /**< Number of data */
struct {
unsigned long value; /**< Value from kernel */
const char *long_format; /**< Suggested format for long_name */
const char *long_name; /**< Long name for value */
const char *rate_format; /**< Suggested format for rate_name */
const char *rate_name; /**< Short name for value per second */
int isvalue; /**< True if value (vs. counter) */
const char *mult_names; /**< Multiplier names (e.g., "KGM") */
int mult; /**< Multiplier value (e.g., 1024) */
int verbose; /**< Suggest only in verbose output */
} data[15];
} drmStatsT;
/* All of these enums *MUST* match with the
kernel implementation -- so do *NOT*
change them! (The drmlib implementation
will just copy the flags instead of
translating them.) */
typedef enum {
DRM_FRAME_BUFFER = 0, /**< WC, no caching, no core dump */
DRM_REGISTERS = 1, /**< no caching, no core dump */
DRM_SHM = 2, /**< shared, cached */
DRM_AGP = 3, /**< AGP/GART */
DRM_SCATTER_GATHER = 4, /**< PCI scatter/gather */
DRM_CONSISTENT = 5 /**< PCI consistent */
} drmMapType;
typedef enum {
DRM_RESTRICTED = 0x0001, /**< Cannot be mapped to client-virtual */
DRM_READ_ONLY = 0x0002, /**< Read-only in client-virtual */
DRM_LOCKED = 0x0004, /**< Physical pages locked */
DRM_KERNEL = 0x0008, /**< Kernel requires access */
DRM_WRITE_COMBINING = 0x0010, /**< Use write-combining, if available */
DRM_CONTAINS_LOCK = 0x0020, /**< SHM page that contains lock */
DRM_REMOVABLE = 0x0040 /**< Removable mapping */
} drmMapFlags;
/**
* \warning These values *MUST* match drm.h
*/
typedef enum {
/** \name Flags for DMA buffer dispatch */
/*@{*/
DRM_DMA_BLOCK = 0x01, /**<
* Block until buffer dispatched.
*
* \note the buffer may not yet have been
* processed by the hardware -- getting a
* hardware lock with the hardware quiescent
* will ensure that the buffer has been
* processed.
*/
DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
/*@}*/
/** \name Flags for DMA buffer request */
/*@{*/
DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
/*@}*/
} drmDMAFlags;
typedef enum {
DRM_PAGE_ALIGN = 0x01,
DRM_AGP_BUFFER = 0x02,
DRM_SG_BUFFER = 0x04,
DRM_FB_BUFFER = 0x08,
DRM_PCI_BUFFER_RO = 0x10
} drmBufDescFlags;
typedef enum {
DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
/* These *HALT* flags aren't supported yet
-- they will be used to support the
full-screen DGA-like mode. */
DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
} drmLockFlags;
typedef enum {
DRM_CONTEXT_PRESERVED = 0x01, /**< This context is preserved and
never swapped. */
DRM_CONTEXT_2DONLY = 0x02 /**< This context is for 2D rendering only. */
} drm_context_tFlags, *drm_context_tFlagsPtr;
typedef struct _drmBufDesc {
int count; /**< Number of buffers of this size */
int size; /**< Size in bytes */
int low_mark; /**< Low water mark */
int high_mark; /**< High water mark */
} drmBufDesc, *drmBufDescPtr;
typedef struct _drmBufInfo {
int count; /**< Number of buffers described in list */
drmBufDescPtr list; /**< List of buffer descriptions */
} drmBufInfo, *drmBufInfoPtr;
typedef struct _drmBuf {
int idx; /**< Index into the master buffer list */
int total; /**< Buffer size */
int used; /**< Amount of buffer in use (for DMA) */
drmAddress address; /**< Address */
} drmBuf, *drmBufPtr;
/**
* Buffer mapping information.
*
* Used by drmMapBufs() and drmUnmapBufs() to store information about the
* mapped buffers.
*/
typedef struct _drmBufMap {
int count; /**< Number of buffers mapped */
drmBufPtr list; /**< Buffers */
} drmBufMap, *drmBufMapPtr;
typedef struct _drmLock {
volatile unsigned int lock;
char padding[60];
/* This is big enough for most current (and future?) architectures:
DEC Alpha: 32 bytes
Intel Merced: ?
Intel P5/PPro/PII/PIII: 32 bytes
Intel StrongARM: 32 bytes
Intel i386/i486: 16 bytes
MIPS: 32 bytes (?)
Motorola 68k: 16 bytes
Motorola PowerPC: 32 bytes
Sun SPARC: 32 bytes
*/
} drmLock, *drmLockPtr;
/**
* Indices here refer to the offset into
* list in drmBufInfo
*/
typedef struct _drmDMAReq {
drm_context_t context; /**< Context handle */
int send_count; /**< Number of buffers to send */
int *send_list; /**< List of handles to buffers */
int *send_sizes; /**< Lengths of data to send, in bytes */
drmDMAFlags flags; /**< Flags */
int request_count; /**< Number of buffers requested */
int request_size; /**< Desired size of buffers requested */
int *request_list; /**< Buffer information */
int *request_sizes; /**< Minimum acceptable sizes */
int granted_count; /**< Number of buffers granted at this size */
} drmDMAReq, *drmDMAReqPtr;
typedef struct _drmRegion {
drm_handle_t handle;
unsigned int offset;
drmSize size;
drmAddress map;
} drmRegion, *drmRegionPtr;
typedef struct _drmTextureRegion {
unsigned char next;
unsigned char prev;
unsigned char in_use;
unsigned char padding; /**< Explicitly pad this out */
unsigned int age;
} drmTextureRegion, *drmTextureRegionPtr;
typedef enum {
DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
/* bits 1-6 are reserved for high crtcs */
DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,
DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */
DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
DRM_VBLANK_SIGNAL = 0x40000000 /* Send signal instead of blocking */
} drmVBlankSeqType;
#define DRM_VBLANK_HIGH_CRTC_SHIFT 1
typedef struct _drmVBlankReq {
drmVBlankSeqType type;
unsigned int sequence;
unsigned long signal;
} drmVBlankReq, *drmVBlankReqPtr;
typedef struct _drmVBlankReply {
drmVBlankSeqType type;
unsigned int sequence;
long tval_sec;
long tval_usec;
} drmVBlankReply, *drmVBlankReplyPtr;
typedef union _drmVBlank {
drmVBlankReq request;
drmVBlankReply reply;
} drmVBlank, *drmVBlankPtr;
typedef struct _drmSetVersion {
int drm_di_major;
int drm_di_minor;
int drm_dd_major;
int drm_dd_minor;
} drmSetVersion, *drmSetVersionPtr;
#define __drm_dummy_lock(lock) (*(__volatile__ unsigned int *)lock)
#define DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
#define DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
#if defined(__GNUC__) && (__GNUC__ >= 2)
# if defined(__i386) || defined(__AMD64__) || defined(__x86_64__) || defined(__amd64__)
/* Reflect changes here to drmP.h */
#define DRM_CAS(lock,old,new,__ret) \
do { \
int __dummy; /* Can't mark eax as clobbered */ \
__asm__ __volatile__( \
"lock ; cmpxchg %4,%1\n\t" \
"setnz %0" \
: "=d" (__ret), \
"=m" (__drm_dummy_lock(lock)), \
"=a" (__dummy) \
: "2" (old), \
"r" (new)); \
} while (0)
#elif defined(__alpha__)
#define DRM_CAS(lock, old, new, ret) \
do { \
int tmp, old32; \
__asm__ __volatile__( \
" addl $31, %5, %3\n" \
"1: ldl_l %0, %2\n" \
" cmpeq %0, %3, %1\n" \
" beq %1, 2f\n" \
" mov %4, %0\n" \
" stl_c %0, %2\n" \
" beq %0, 3f\n" \
" mb\n" \
"2: cmpeq %1, 0, %1\n" \
".subsection 2\n" \
"3: br 1b\n" \
".previous" \
: "=&r"(tmp), "=&r"(ret), \
"=m"(__drm_dummy_lock(lock)), \
"=&r"(old32) \
: "r"(new), "r"(old) \
: "memory"); \
} while (0)
#elif defined(__sparc__)
#define DRM_CAS(lock,old,new,__ret) \
do { register unsigned int __old __asm("o0"); \
register unsigned int __new __asm("o1"); \
register volatile unsigned int *__lock __asm("o2"); \
__old = old; \
__new = new; \
__lock = (volatile unsigned int *)lock; \
__asm__ __volatile__( \
/*"cas [%2], %3, %0"*/ \
".word 0xd3e29008\n\t" \
/*"membar #StoreStore | #StoreLoad"*/ \
".word 0x8143e00a" \
: "=&r" (__new) \
: "0" (__new), \
"r" (__lock), \
"r" (__old) \
: "memory"); \
__ret = (__new != __old); \
} while(0)
#elif defined(__ia64__)
#ifdef __INTEL_COMPILER
/* this currently generates bad code (missing stop bits)... */
#include <ia64intrin.h>
#define DRM_CAS(lock,old,new,__ret) \
do { \
unsigned long __result, __old = (old) & 0xffffffff; \
__mf(); \
__result = _InterlockedCompareExchange_acq(&__drm_dummy_lock(lock), (new), __old);\
__ret = (__result) != (__old); \
/* __ret = (__sync_val_compare_and_swap(&__drm_dummy_lock(lock), \
(old), (new)) \
!= (old)); */\
} while (0)
#else
#define DRM_CAS(lock,old,new,__ret) \
do { \
unsigned int __result, __old = (old); \
__asm__ __volatile__( \
"mf\n" \
"mov ar.ccv=%2\n" \
";;\n" \
"cmpxchg4.acq %0=%1,%3,ar.ccv" \
: "=r" (__result), "=m" (__drm_dummy_lock(lock)) \
: "r" ((unsigned long)__old), "r" (new) \
: "memory"); \
__ret = (__result) != (__old); \
} while (0)
#endif
#elif defined(__powerpc__)
#define DRM_CAS(lock,old,new,__ret) \
do { \
__asm__ __volatile__( \
"sync;" \
"0: lwarx %0,0,%1;" \
" xor. %0,%3,%0;" \
" bne 1f;" \
" stwcx. %2,0,%1;" \
" bne- 0b;" \
"1: " \
"sync;" \
: "=&r"(__ret) \
: "r"(lock), "r"(new), "r"(old) \
: "cr0", "memory"); \
} while (0)
# elif defined (__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \
|| defined (__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) \
|| defined (__ARM_ARCH_6K__) || defined(__ARM_ARCH_6T2__) \
|| defined (__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \
|| defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \
|| defined(__ARM_ARCH_7EM__)
/* excluding ARMv4/ARMv5 and lower (lacking ldrex/strex support) */
#undef DRM_DEV_MODE
#define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH)
#define DRM_CAS(lock,old,new,__ret) \
do { \
__asm__ __volatile__ ( \
"1: ldrex %0, [%1]\n" \
" teq %0, %2\n" \
" ite eq\n" \
" strexeq %0, %3, [%1]\n" \
" movne %0, #1\n" \
: "=&r" (__ret) \
: "r" (lock), "r" (old), "r" (new) \
: "cc","memory"); \
} while (0)
#endif /* architecture */
#endif /* __GNUC__ >= 2 */
#ifndef DRM_CAS
#define DRM_CAS(lock,old,new,ret) do { ret=1; } while (0) /* FAST LOCK FAILS */
#endif
#if defined(__alpha__)
#define DRM_CAS_RESULT(_result) long _result
#elif defined(__powerpc__)
#define DRM_CAS_RESULT(_result) int _result
#else
#define DRM_CAS_RESULT(_result) char _result
#endif
#define DRM_LIGHT_LOCK(fd,lock,context) \
do { \
DRM_CAS_RESULT(__ret); \
DRM_CAS(lock,context,DRM_LOCK_HELD|context,__ret); \
if (__ret) drmGetLock(fd,context,0); \
} while(0)
/* This one counts fast locks -- for
benchmarking only. */
#define DRM_LIGHT_LOCK_COUNT(fd,lock,context,count) \
do { \
DRM_CAS_RESULT(__ret); \
DRM_CAS(lock,context,DRM_LOCK_HELD|context,__ret); \
if (__ret) drmGetLock(fd,context,0); \
else ++count; \
} while(0)
#define DRM_LOCK(fd,lock,context,flags) \
do { \
if (flags) drmGetLock(fd,context,flags); \
else DRM_LIGHT_LOCK(fd,lock,context); \
} while(0)
#define DRM_UNLOCK(fd,lock,context) \
do { \
DRM_CAS_RESULT(__ret); \
DRM_CAS(lock,DRM_LOCK_HELD|context,context,__ret); \
if (__ret) drmUnlock(fd,context); \
} while(0)
/* Simple spin locks */
#define DRM_SPINLOCK(spin,val) \
do { \
DRM_CAS_RESULT(__ret); \
do { \
DRM_CAS(spin,0,val,__ret); \
if (__ret) while ((spin)->lock); \
} while (__ret); \
} while(0)
#define DRM_SPINLOCK_TAKE(spin,val) \
do { \
DRM_CAS_RESULT(__ret); \
int cur; \
do { \
cur = (*spin).lock; \
DRM_CAS(spin,cur,val,__ret); \
} while (__ret); \
} while(0)
#define DRM_SPINLOCK_COUNT(spin,val,count,__ret) \
do { \
int __i; \
__ret = 1; \
for (__i = 0; __ret && __i < count; __i++) { \
DRM_CAS(spin,0,val,__ret); \
if (__ret) for (;__i < count && (spin)->lock; __i++); \
} \
} while(0)
#define DRM_SPINUNLOCK(spin,val) \
do { \
DRM_CAS_RESULT(__ret); \
if ((*spin).lock == val) { /* else server stole lock */ \
do { \
DRM_CAS(spin,val,0,__ret); \
} while (__ret); \
} \
} while(0)
/* General user-level programmer's API: unprivileged */
extern int drmAvailable(void);
extern int drmOpen(const char *name, const char *busid);
#define DRM_NODE_PRIMARY 0
#define DRM_NODE_CONTROL 1 /* deprecated: never returned */
#define DRM_NODE_RENDER 2
#define DRM_NODE_MAX 3
extern int drmOpenWithType(const char *name, const char *busid,
int type);
extern int drmOpenControl(int minor); /* deprecated: always fails */
extern int drmOpenRender(int minor);
extern int drmClose(int fd);
extern drmVersionPtr drmGetVersion(int fd);
extern drmVersionPtr drmGetLibVersion(int fd);
extern int drmGetCap(int fd, uint64_t capability, uint64_t *value);
extern void drmFreeVersion(drmVersionPtr);
extern int drmGetMagic(int fd, drm_magic_t * magic);
extern char *drmGetBusid(int fd);
extern int drmGetInterruptFromBusID(int fd, int busnum, int devnum,
int funcnum);
extern int drmGetMap(int fd, int idx, drm_handle_t *offset,
drmSize *size, drmMapType *type,
drmMapFlags *flags, drm_handle_t *handle,
int *mtrr);
extern int drmGetClient(int fd, int idx, int *auth, int *pid,
int *uid, unsigned long *magic,
unsigned long *iocs);
extern int drmGetStats(int fd, drmStatsT *stats);
extern int drmSetInterfaceVersion(int fd, drmSetVersion *version);
extern int drmCommandNone(int fd, unsigned long drmCommandIndex);
extern int drmCommandRead(int fd, unsigned long drmCommandIndex,
void *data, unsigned long size);
extern int drmCommandWrite(int fd, unsigned long drmCommandIndex,
void *data, unsigned long size);
extern int drmCommandWriteRead(int fd, unsigned long drmCommandIndex,
void *data, unsigned long size);
/* General user-level programmer's API: X server (root) only */
extern void drmFreeBusid(const char *busid);
extern int drmSetBusid(int fd, const char *busid);
extern int drmAuthMagic(int fd, drm_magic_t magic);
extern int drmAddMap(int fd,
drm_handle_t offset,
drmSize size,
drmMapType type,
drmMapFlags flags,
drm_handle_t * handle);
extern int drmRmMap(int fd, drm_handle_t handle);
extern int drmAddContextPrivateMapping(int fd, drm_context_t ctx_id,
drm_handle_t handle);
extern int drmAddBufs(int fd, int count, int size,
drmBufDescFlags flags,
int agp_offset);
extern int drmMarkBufs(int fd, double low, double high);
extern int drmCreateContext(int fd, drm_context_t * handle);
extern int drmSetContextFlags(int fd, drm_context_t context,
drm_context_tFlags flags);
extern int drmGetContextFlags(int fd, drm_context_t context,
drm_context_tFlagsPtr flags);
extern int drmAddContextTag(int fd, drm_context_t context, void *tag);
extern int drmDelContextTag(int fd, drm_context_t context);
extern void *drmGetContextTag(int fd, drm_context_t context);
extern drm_context_t * drmGetReservedContextList(int fd, int *count);
extern void drmFreeReservedContextList(drm_context_t *);
extern int drmSwitchToContext(int fd, drm_context_t context);
extern int drmDestroyContext(int fd, drm_context_t handle);
extern int drmCreateDrawable(int fd, drm_drawable_t * handle);
extern int drmDestroyDrawable(int fd, drm_drawable_t handle);
extern int drmUpdateDrawableInfo(int fd, drm_drawable_t handle,
drm_drawable_info_type_t type,
unsigned int num, void *data);
extern int drmCtlInstHandler(int fd, int irq);
extern int drmCtlUninstHandler(int fd);
extern int drmSetClientCap(int fd, uint64_t capability,
uint64_t value);
extern int drmCrtcGetSequence(int fd, uint32_t crtcId,
uint64_t *sequence, uint64_t *ns);
extern int drmCrtcQueueSequence(int fd, uint32_t crtcId,
uint32_t flags, uint64_t sequence,
uint64_t *sequence_queued,
uint64_t user_data);
/* General user-level programmer's API: authenticated client and/or X */
extern int drmMap(int fd,
drm_handle_t handle,
drmSize size,
drmAddressPtr address);
extern int drmUnmap(drmAddress address, drmSize size);
extern drmBufInfoPtr drmGetBufInfo(int fd);
extern drmBufMapPtr drmMapBufs(int fd);
extern int drmUnmapBufs(drmBufMapPtr bufs);
extern int drmDMA(int fd, drmDMAReqPtr request);
extern int drmFreeBufs(int fd, int count, int *list);
extern int drmGetLock(int fd,
drm_context_t context,
drmLockFlags flags);
extern int drmUnlock(int fd, drm_context_t context);
extern int drmFinish(int fd, int context, drmLockFlags flags);
extern int drmGetContextPrivateMapping(int fd, drm_context_t ctx_id,
drm_handle_t * handle);
/* AGP/GART support: X server (root) only */
extern int drmAgpAcquire(int fd);
extern int drmAgpRelease(int fd);
extern int drmAgpEnable(int fd, unsigned long mode);
extern int drmAgpAlloc(int fd, unsigned long size,
unsigned long type, unsigned long *address,
drm_handle_t *handle);
extern int drmAgpFree(int fd, drm_handle_t handle);
extern int drmAgpBind(int fd, drm_handle_t handle,
unsigned long offset);
extern int drmAgpUnbind(int fd, drm_handle_t handle);
/* AGP/GART info: authenticated client and/or X */
extern int drmAgpVersionMajor(int fd);
extern int drmAgpVersionMinor(int fd);
extern unsigned long drmAgpGetMode(int fd);
extern unsigned long drmAgpBase(int fd); /* Physical location */
extern unsigned long drmAgpSize(int fd); /* Bytes */
extern unsigned long drmAgpMemoryUsed(int fd);
extern unsigned long drmAgpMemoryAvail(int fd);
extern unsigned int drmAgpVendorId(int fd);
extern unsigned int drmAgpDeviceId(int fd);
/* PCI scatter/gather support: X server (root) only */
extern int drmScatterGatherAlloc(int fd, unsigned long size,
drm_handle_t *handle);
extern int drmScatterGatherFree(int fd, drm_handle_t handle);
extern int drmWaitVBlank(int fd, drmVBlankPtr vbl);
/* Support routines */
extern void drmSetServerInfo(drmServerInfoPtr info);
extern int drmError(int err, const char *label);
extern void *drmMalloc(int size);
extern void drmFree(void *pt);
/* Hash table routines */
extern void *drmHashCreate(void);
extern int drmHashDestroy(void *t);
extern int drmHashLookup(void *t, unsigned long key, void **value);
extern int drmHashInsert(void *t, unsigned long key, void *value);
extern int drmHashDelete(void *t, unsigned long key);
extern int drmHashFirst(void *t, unsigned long *key, void **value);
extern int drmHashNext(void *t, unsigned long *key, void **value);
/* PRNG routines */
extern void *drmRandomCreate(unsigned long seed);
extern int drmRandomDestroy(void *state);
extern unsigned long drmRandom(void *state);
extern double drmRandomDouble(void *state);
/* Skip list routines */
extern void *drmSLCreate(void);
extern int drmSLDestroy(void *l);
extern int drmSLLookup(void *l, unsigned long key, void **value);
extern int drmSLInsert(void *l, unsigned long key, void *value);
extern int drmSLDelete(void *l, unsigned long key);
extern int drmSLNext(void *l, unsigned long *key, void **value);
extern int drmSLFirst(void *l, unsigned long *key, void **value);
extern void drmSLDump(void *l);
extern int drmSLLookupNeighbors(void *l, unsigned long key,
unsigned long *prev_key, void **prev_value,
unsigned long *next_key, void **next_value);
extern int drmOpenOnce(void *unused, const char *BusID, int *newlyopened);
extern int drmOpenOnceWithType(const char *BusID, int *newlyopened, int type);
extern void drmCloseOnce(int fd);
extern void drmMsg(const char *format, ...) DRM_PRINTFLIKE(1, 2);
extern int drmSetMaster(int fd);
extern int drmDropMaster(int fd);
extern int drmIsMaster(int fd);
#define DRM_EVENT_CONTEXT_VERSION 4
typedef struct _drmEventContext {
/* This struct is versioned so we can add more pointers if we
* add more events. */
int version;
void (*vblank_handler)(int fd,
unsigned int sequence,
unsigned int tv_sec,
unsigned int tv_usec,
void *user_data);
void (*page_flip_handler)(int fd,
unsigned int sequence,
unsigned int tv_sec,
unsigned int tv_usec,
void *user_data);
void (*page_flip_handler2)(int fd,
unsigned int sequence,
unsigned int tv_sec,
unsigned int tv_usec,
unsigned int crtc_id,
void *user_data);
void (*sequence_handler)(int fd,
uint64_t sequence,
uint64_t ns,
uint64_t user_data);
} drmEventContext, *drmEventContextPtr;
extern int drmHandleEvent(int fd, drmEventContextPtr evctx);
extern char *drmGetDeviceNameFromFd(int fd);
/* Improved version of drmGetDeviceNameFromFd which attributes for any type of
* device/node - card or renderD.
*/
extern char *drmGetDeviceNameFromFd2(int fd);
extern int drmGetNodeTypeFromFd(int fd);
/* Convert between GEM handles and DMA-BUF file descriptors.
*
* Warning: since GEM handles are not reference-counted and are unique per
* DRM file description, the caller is expected to perform its own reference
* counting. drmPrimeFDToHandle is guaranteed to return the same handle for
* different FDs if they reference the same underlying buffer object. This
* could even be a buffer object originally created on the same DRM FD.
*
* When sharing a DRM FD with an API such as EGL or GBM, the caller must not
* use drmPrimeHandleToFD nor drmPrimeFDToHandle. A single user-space
* reference-counting implementation is necessary to avoid double-closing GEM
* handles.
*
* Two processes can't share the same DRM FD and both use it to create or
* import GEM handles, even when using a single user-space reference-counting
* implementation like GBM, because GBM doesn't share its state between
* processes.
*/
extern int drmPrimeHandleToFD(int fd, uint32_t handle, uint32_t flags, int *prime_fd);
extern int drmPrimeFDToHandle(int fd, int prime_fd, uint32_t *handle);
extern int drmCloseBufferHandle(int fd, uint32_t handle);
extern char *drmGetPrimaryDeviceNameFromFd(int fd);
extern char *drmGetRenderDeviceNameFromFd(int fd);
#define DRM_BUS_PCI 0
#define DRM_BUS_USB 1
#define DRM_BUS_PLATFORM 2
#define DRM_BUS_HOST1X 3
typedef struct _drmPciBusInfo {
uint16_t domain;
uint8_t bus;
uint8_t dev;
uint8_t func;
} drmPciBusInfo, *drmPciBusInfoPtr;
typedef struct _drmPciDeviceInfo {
uint16_t vendor_id;
uint16_t device_id;
uint16_t subvendor_id;
uint16_t subdevice_id;
uint8_t revision_id;
} drmPciDeviceInfo, *drmPciDeviceInfoPtr;
typedef struct _drmUsbBusInfo {
uint8_t bus;
uint8_t dev;
} drmUsbBusInfo, *drmUsbBusInfoPtr;
typedef struct _drmUsbDeviceInfo {
uint16_t vendor;
uint16_t product;
} drmUsbDeviceInfo, *drmUsbDeviceInfoPtr;
#define DRM_PLATFORM_DEVICE_NAME_LEN 512
typedef struct _drmPlatformBusInfo {
char fullname[DRM_PLATFORM_DEVICE_NAME_LEN];
} drmPlatformBusInfo, *drmPlatformBusInfoPtr;
typedef struct _drmPlatformDeviceInfo {
char **compatible; /* NULL terminated list of compatible strings */
} drmPlatformDeviceInfo, *drmPlatformDeviceInfoPtr;
#define DRM_HOST1X_DEVICE_NAME_LEN 512
typedef struct _drmHost1xBusInfo {
char fullname[DRM_HOST1X_DEVICE_NAME_LEN];
} drmHost1xBusInfo, *drmHost1xBusInfoPtr;
typedef struct _drmHost1xDeviceInfo {
char **compatible; /* NULL terminated list of compatible strings */
} drmHost1xDeviceInfo, *drmHost1xDeviceInfoPtr;
typedef struct _drmDevice {
char **nodes; /* DRM_NODE_MAX sized array */
int available_nodes; /* DRM_NODE_* bitmask */
int bustype;
union {
drmPciBusInfoPtr pci;
drmUsbBusInfoPtr usb;
drmPlatformBusInfoPtr platform;
drmHost1xBusInfoPtr host1x;
} businfo;
union {
drmPciDeviceInfoPtr pci;
drmUsbDeviceInfoPtr usb;
drmPlatformDeviceInfoPtr platform;
drmHost1xDeviceInfoPtr host1x;
} deviceinfo;
} drmDevice, *drmDevicePtr;
extern int drmGetDevice(int fd, drmDevicePtr *device);
extern void drmFreeDevice(drmDevicePtr *device);
extern int drmGetDevices(drmDevicePtr devices[], int max_devices);
extern void drmFreeDevices(drmDevicePtr devices[], int count);
#define DRM_DEVICE_GET_PCI_REVISION (1 << 0)
extern int drmGetDevice2(int fd, uint32_t flags, drmDevicePtr *device);
extern int drmGetDevices2(uint32_t flags, drmDevicePtr devices[], int max_devices);
extern int drmGetDeviceFromDevId(dev_t dev_id, uint32_t flags, drmDevicePtr *device);
/**
* Get the node type (DRM_NODE_PRIMARY or DRM_NODE_RENDER) from a device ID.
*
* Returns negative errno on error.
*/
extern int drmGetNodeTypeFromDevId(dev_t devid);
/**
* Check if two drmDevice pointers represent the same DRM device.
*
* Returns 1 if the devices are equal, 0 otherwise.
*/
extern int drmDevicesEqual(drmDevicePtr a, drmDevicePtr b);
extern int drmSyncobjCreate(int fd, uint32_t flags, uint32_t *handle);
extern int drmSyncobjDestroy(int fd, uint32_t handle);
extern int drmSyncobjHandleToFD(int fd, uint32_t handle, int *obj_fd);
extern int drmSyncobjFDToHandle(int fd, int obj_fd, uint32_t *handle);
extern int drmSyncobjImportSyncFile(int fd, uint32_t handle, int sync_file_fd);
extern int drmSyncobjExportSyncFile(int fd, uint32_t handle, int *sync_file_fd);
extern int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles,
int64_t timeout_nsec, unsigned flags,
uint32_t *first_signaled);
extern int drmSyncobjReset(int fd, const uint32_t *handles, uint32_t handle_count);
extern int drmSyncobjSignal(int fd, const uint32_t *handles, uint32_t handle_count);
extern int drmSyncobjTimelineSignal(int fd, const uint32_t *handles,
uint64_t *points, uint32_t handle_count);
extern int drmSyncobjTimelineWait(int fd, uint32_t *handles, uint64_t *points,
unsigned num_handles,
int64_t timeout_nsec, unsigned flags,
uint32_t *first_signaled);
extern int drmSyncobjQuery(int fd, uint32_t *handles, uint64_t *points,
uint32_t handle_count);
extern int drmSyncobjQuery2(int fd, uint32_t *handles, uint64_t *points,
uint32_t handle_count, uint32_t flags);
extern int drmSyncobjTransfer(int fd,
uint32_t dst_handle, uint64_t dst_point,
uint32_t src_handle, uint64_t src_point,
uint32_t flags);
extern int drmSyncobjEventfd(int fd, uint32_t handle, uint64_t point, int ev_fd,
uint32_t flags);
extern char *
drmGetFormatModifierVendor(uint64_t modifier);
extern char *
drmGetFormatModifierName(uint64_t modifier);
extern char *
drmGetFormatName(uint32_t format);
#ifndef fourcc_mod_get_vendor
#define fourcc_mod_get_vendor(modifier) \
(((modifier) >> 56) & 0xff)
#endif
#if defined(__cplusplus)
}
#endif
#endif
py-interface/CMakeLists.txt
+1
Wyświetl plik
@@ -1,5 +1,6 @@
# Generate py-interface and package targets
set(CMAKE_VERBOSE_MAKEFILE on)
# CLANG installed must be 16.0 or above
# CLANG is only needed for generating new amdsmi_wrapper.py
# this is normally done in a docker container with a controlled clang and python-clang versions
py-interface/amdsmi_interface.py
+1
Wyświetl plik
@@ -1888,6 +1888,7 @@ def amdsmi_get_gpu_asic_info(
# Remove commas from vendor name for clean output
asic_info["vendor_name"] = asic_info["vendor_name"].replace(',', '')
logging.debug("amdsmi_interface.py | amdsmi_get_gpu_asic_info | return_dictionary = \n" + str(json.dumps(asic_info, indent=4)))
return asic_info
rocm_smi/CMakeLists.txt
+87 -55
Wyświetl plik
@@ -6,6 +6,9 @@ message("&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&")
message(" CMake ROCm SMI (Library) ")
message("&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&")
## Verbose output.
set(CMAKE_VERBOSE_MAKEFILE on)
message("")
message("Build Configuration:")
# message("-----------BuildType: " ${CMAKE_BUILD_TYPE})
@@ -15,6 +18,8 @@ message("--------Proj Src Dir: " ${PROJECT_SOURCE_DIR})
# message("--------Proj Bld Dir: " ${PROJECT_BINARY_DIR})
# message("--------Proj Lib Dir: " ${PROJECT_BINARY_DIR}/lib)
# message("--------Proj Exe Dir: " ${PROJECT_BINARY_DIR}/bin)
# message("--------RSMI Lib Dir: " ${RSMI_LIB_DIR})
# message("--------RSMI Inc Dir: " ${RSMI_INC_DIR})
# message("")
set(ROCM_SMI "rocm_smi")
@@ -35,8 +40,8 @@ message("Package version: ${PKG_VERSION_STR}")
get_version_from_tag("1.0.0.0" ${SO_VERSION_GIT_TAG_PREFIX} GIT)
# VERSION_* variables should be set by get_version_from_tag
if(${ROCM_PATCH_VERSION})
set(VERSION_PATCH ${ROCM_PATCH_VERSION})
if ( ${ROCM_PATCH_VERSION} )
set ( VERSION_PATCH ${ROCM_PATCH_VERSION})
set(SO_VERSION_STRING "${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH}")
else()
set(SO_VERSION_STRING "${VERSION_MAJOR}.${VERSION_MINOR}")
@@ -48,73 +53,100 @@ set(${ROCM_SMI}_VERSION_BUILD "0")
set(${ROCM_SMI}_VERSION_HASH "${PKG_VERSION_HASH}")
message("SOVERSION: ${SO_VERSION_STRING}")
# Configure rsmiBindingsInit.py.in with SO major version:
# configure_file(
# "${COMMON_SRC_ROOT}/python_smi_tools/rsmiBindingsInit.py.in"
# "${COMMON_SRC_ROOT}/python_smi_tools/rsmiBindingsInit.py")
# Create a configure file to get version info from within library
configure_file("src/${ROCM_SMI_TARGET}Config.in"
"${CMAKE_CURRENT_SOURCE_DIR}/include/rocm_smi/${ROCM_SMI_TARGET}Config.h")
set(rocm_smi_VERSION_MAJOR "${VERSION_MAJOR}")
set(rocm_smi_VERSION_MINOR "${VERSION_MINOR}")
set(rocm_smi_VERSION_PATCH "0")
set(rocm_smi_VERSION_BUILD "0")
set(RSMI_SRC_DIR "src")
set(RSMI_INC_DIR "include")
set(RSMI_DOCS_DIR "docs")
add_library(${ROCM_SMI_TARGET} ${CMN_SRC_LIST} ${CMN_INC_LIST})
target_link_libraries(${ROCM_SMI_TARGET} pthread rt dl)
target_include_directories(${ROCM_SMI_TARGET} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}
${PROJECT_SOURCE_DIR}/common/shared_mutex)
# Add any rocm_smi_lib specific source files here
set(SMI_SRC_LIST ${CMN_SRC_LIST})
# Add any rocm_smi_lib specific headers here
set(SMI_INC_LIST "")
set(SMI_EXAMPLE_EXE "rocm_smi_ex")
# add_executable(${SMI_EXAMPLE_EXE} "example/rocm_smi_example.cc")
# target_link_libraries(${SMI_EXAMPLE_EXE} ${ROCM_SMI_TARGET})
add_library(${ROCM_SMI_TARGET} ${CMN_SRC_LIST} ${CMN_INC_LIST})
target_link_libraries(${ROCM_SMI_TARGET} PRIVATE pthread rt dl)
target_include_directories(${ROCM_SMI_TARGET} PRIVATE
${CMAKE_CURRENT_SOURCE_DIR} ${PROJECT_SOURCE_DIR}/common/shared_mutex)
# use the target_include_directories() command to specify the include directories for the target
target_include_directories(${ROCM_SMI_TARGET} PUBLIC "$<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/include>"
"$<INSTALL_INTERFACE:${ROCM_SMI}/include>")
target_include_directories(${ROCM_SMI_TARGET}
PUBLIC
"$<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/include>"
"$<INSTALL_INTERFACE:${ROCM_SMI}/include>"
)
if(FILE_REORG_BACKWARD_COMPATIBILITY)
target_include_directories(${ROCM_SMI_TARGET}
PUBLIC
"$<INSTALL_INTERFACE:${ROCM_SMI}/include>")
endif()
## Set the VERSION and SOVERSION values
set_property(TARGET ${ROCM_SMI_TARGET} PROPERTY SOVERSION "${VERSION_MAJOR}")
set_property(TARGET ${ROCM_SMI_TARGET} PROPERTY VERSION "${SO_VERSION_STRING}")
set_property(TARGET ${ROCM_SMI_TARGET} PROPERTY
SOVERSION "${VERSION_MAJOR}")
set_property(TARGET ${ROCM_SMI_TARGET} PROPERTY
VERSION "${SO_VERSION_STRING}")
## If the library is a release, strip the target library
if("${CMAKE_BUILD_TYPE}" STREQUAL Release)
if(${BUILD_SHARED_LIBS}) #stripping only for .so
add_custom_command(
TARGET ${ROCM_SMI_TARGET}
POST_BUILD
COMMAND ${CMAKE_STRIP} lib${ROCM_SMI_TARGET}.so.${SO_VERSION_STRING})
endif()
endif()
if ("${CMAKE_BUILD_TYPE}" STREQUAL Release)
if(${BUILD_SHARED_LIBS}) #stripping only for .so
add_custom_command(
TARGET ${ROCM_SMI_TARGET}
POST_BUILD COMMAND ${CMAKE_STRIP} lib${ROCM_SMI_TARGET}.so.${SO_VERSION_STRING})
endif()
endif ()
#file reorganization changes
#rocm_smi.py moved to libexec/rocm_smi. so creating rocm-smi symlink
#file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/bin)
#add_custom_target(
# link-rocm-smi ALL
# WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
# COMMAND ${CMAKE_COMMAND} -E create_symlink ../libexec/${ROCM_SMI}/rocm_smi.py
# ${CMAKE_CURRENT_BINARY_DIR}/bin/rocm-smi)
# file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/bin)
# add_custom_target(link-rocm-smi ALL
# WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
# COMMAND ${CMAKE_COMMAND} -E create_symlink
# ../${CMAKE_INSTALL_LIBEXECDIR}/${ROCM_SMI}/rocm_smi.py ${CMAKE_CURRENT_BINARY_DIR}/bin/rocm-smi)
## Add the install directives for the runtime library.
#install(
# TARGETS ${ROCM_SMI_TARGET}
# EXPORT rocm_smiTargets
# LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}
# ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT ${ROCM_SMI_COMPONENT})
#
#install(
# FILES ${CMAKE_CURRENT_SOURCE_DIR}/include/rocm_smi/rocm_smi.h
# DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/rocm_smi
# COMPONENT ${ROCM_SMI_COMPONENT})
#install(
# FILES ${CMAKE_CURRENT_SOURCE_DIR}/include/rocm_smi/${ROCM_SMI_TARGET}Config.h
# DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/rocm_smi
# COMPONENT ${ROCM_SMI_COMPONENT})
#install(
# FILES ${CMAKE_CURRENT_SOURCE_DIR}/include/rocm_smi/kfd_ioctl.h
# DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/rocm_smi
# COMPONENT ${ROCM_SMI_COMPONENT})
#install(FILES ${PROJECT_SOURCE_DIR}/rocm_smi/python_smi_tools/rsmiBindings.py
# DESTINATION libexec/${ROCM_SMI})
#install(FILES ${PROJECT_SOURCE_DIR}/rocm_smi/python_smi_tools/rocm_smi.py
# PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE GROUP_READ
# GROUP_WRITE GROUP_EXECUTE WORLD_READ WORLD_EXECUTE
# DESTINATION libexec/${ROCM_SMI})
#install(FILES ${CMAKE_CURRENT_BINARY_DIR}/bin/rocm-smi
# DESTINATION bin)
# install(TARGETS ${ROCM_SMI_TARGET}
# EXPORT rocm_smiTargets
# LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT dev
# ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT dev)
# install(TARGETS ${ROCM_SMI_TARGET}
# LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}
# COMPONENT asan)
# NOTE: Doxygen generation has been stripped
# install(FILES ${COMMON_SRC_ROOT}/include/rocm_smi/rocm_smi.h
# DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/rocm_smi
# COMPONENT dev)
# install(FILES ${COMMON_SRC_ROOT}/include/rocm_smi/${ROCM_SMI_TARGET}Config.h
# DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/rocm_smi
# COMPONENT dev)
# install(FILES ${COMMON_SRC_ROOT}/include/rocm_smi/kfd_ioctl.h
# DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/rocm_smi
# COMPONENT dev)
# install(PROGRAMS ${COMMON_SRC_ROOT}/python_smi_tools/rsmiBindingsInit.py
# DESTINATION ${CMAKE_INSTALL_LIBEXECDIR}/${ROCM_SMI}
# COMPONENT dev)
# install(PROGRAMS ${COMMON_SRC_ROOT}/python_smi_tools/rsmiBindings.py
# DESTINATION ${CMAKE_INSTALL_LIBEXECDIR}/${ROCM_SMI}
# COMPONENT dev)
# install(PROGRAMS ${COMMON_SRC_ROOT}/python_smi_tools/rocm_smi.py
# DESTINATION ${CMAKE_INSTALL_LIBEXECDIR}/${ROCM_SMI}
# COMPONENT dev)
# install(FILES ${CMAKE_CURRENT_BINARY_DIR}/bin/rocm-smi
# DESTINATION ${CMAKE_INSTALL_BINDIR}
# COMPONENT dev)
message("&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&")
message(" CMake ROCm SMI (Library) END ")
message("&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&")
rocm_smi/src/rocm_smi.cc
+35 -21
Wyświetl plik
@@ -915,7 +915,11 @@ rsmi_dev_id_get(uint32_t dv_ind, uint16_t *id) {
rsmi_status_t ret;
ss << __PRETTY_FUNCTION__ << "| ======= start =======";
LOG_TRACE(ss);
if (id == nullptr) {
return RSMI_STATUS_INVALID_ARGS;
}
CHK_SUPPORT_NAME_ONLY(id)
// Set the device ID to max value
*id = std::numeric_limits<uint16_t>::max();
// Get the device ID from KGD
@@ -936,7 +940,7 @@ rsmi_dev_id_get(uint32_t dv_ind, uint16_t *id) {
int ret_kfd = kfd_node->get_node_id(&node_id);
ret_kfd = amd::smi::read_node_properties(node_id, "device_id", &kfd_device_id);
if (ret_kfd == 0) {
*id = kfd_device_id;
*id = static_cast<uint16_t>(kfd_device_id);
ret = RSMI_STATUS_SUCCESS;
} else {
*id = std::numeric_limits<uint16_t>::max();
@@ -1012,35 +1016,42 @@ rsmi_dev_subsystem_id_get(uint32_t dv_ind, uint16_t *id) {
rsmi_status_t
rsmi_dev_vendor_id_get(uint32_t dv_ind, uint16_t *id) {
TRY
std::ostringstream ss;
ss << __PRETTY_FUNCTION__ << "| ======= start =======";
LOG_TRACE(ss);
CHK_SUPPORT_NAME_ONLY(id)
rsmi_status_t status = get_id(dv_ind, amd::smi::kDevVendorID, id);
if (status != RSMI_STATUS_SUCCESS)
{
int ret_kfd = 0;
uint32_t node_id;
rsmi_status_t ret = get_id(dv_ind, amd::smi::kDevVendorID, id);
bool need_fallback = false;
if (ret != RSMI_STATUS_SUCCESS) {
need_fallback = true;
}
if (ret != RSMI_STATUS_SUCCESS) {
GET_DEV_AND_KFDNODE_FROM_INDX
uint32_t node_id;
uint64_t kfd_vendor_id;
int ret_kfd = kfd_node->get_node_id(&node_id);
ret_kfd = kfd_node->get_node_id(&node_id);
ret_kfd = amd::smi::read_node_properties(node_id, "vendor_id", &kfd_vendor_id);
if (ret_kfd == 0) {
*id = kfd_vendor_id;
status = RSMI_STATUS_SUCCESS;
*id = static_cast<uint16_t>(kfd_vendor_id);
ret = RSMI_STATUS_SUCCESS;
} else {
*id = std::numeric_limits<uint16_t>::max();
status = RSMI_STATUS_NOT_SUPPORTED;
ret = RSMI_STATUS_NOT_SUPPORTED;
}
ss << __PRETTY_FUNCTION__
<< " | Issue: Could not read device from sysfs, falling back to KFD" << "\n"
<< " ; Device #: " << std::to_string(dv_ind) << "\n"
<< " ; ret_kfd: " << std::to_string(ret_kfd) << "\n"
<< " ; node: " << std::to_string(node_id) << "\n"
<< " ; Data: vendor_id (from KFD)= " << std::to_string(*id) << "\n"
<< " ; ret = " << getRSMIStatusString(status, false);
LOG_DEBUG(ss);
}
return status;
ss << __PRETTY_FUNCTION__
<< (need_fallback ? " | Needed to fallback to use KFD to read vendor_id" :
" | Read through SYSFS to read vendor_id") << "\n"
<< " ; Device #: " << std::to_string(dv_ind) << "\n"
<< " ; ret_kfd: " << std::to_string(ret_kfd) << "\n"
<< " ; node: " << std::to_string(node_id) << "\n"
<< " ; Data: vendor_id: " << std::to_string(*id) << "\n"
<< " ; ret = " << getRSMIStatusString(ret, false);
LOG_INFO(ss);
return ret;
CATCH
}
rsmi_status_t
@@ -2922,12 +2933,12 @@ rsmi_dev_vendor_name_get(uint32_t dv_ind, char *name, size_t len) {
std::ostringstream ss;
ss << __PRETTY_FUNCTION__ << "| ======= start =======";
LOG_TRACE(ss);
if (name == nullptr || len == 0) {
return RSMI_STATUS_INVALID_ARGS;
}
CHK_SUPPORT_NAME_ONLY(name)
assert(len > 0);
if (len == 0) {
return RSMI_STATUS_INVALID_ARGS;
}
DEVICE_MUTEX
ret = get_dev_name_from_id(dv_ind, name, len, NAME_STR_VENDOR);
@@ -3526,6 +3537,9 @@ rsmi_dev_gpu_reset(uint32_t dv_ind) {
// Read amdgpu_gpu_recover to reset it
ret = get_dev_value_int(amd::smi::kDevGpuReset, dv_ind, &status_code);
ss << __PRETTY_FUNCTION__ << " | ======= end ======= | returning "
<< getRSMIStatusString(ret, false);
LOG_INFO(ss);
return ret;
CATCH
rust-interface/CMakeLists.txt
+1
Wyświetl plik
@@ -1,4 +1,5 @@
# Generate rust-wrapper and package targets
set(CMAKE_VERBOSE_MAKEFILE on)
# This string is the installation directory containing all rust files
set(RUST_WRAPPER_INSTALL_DIR "${SHARE_INSTALL_PREFIX}/rust-wrapper" CACHE STRING "Rust wrapper installation directory")
src/CMakeLists.txt
+2 -2
Wyświetl plik
@@ -1,7 +1,7 @@
#
# Minimum version of cmake required
#
set(CMAKE_VERBOSE_MAKEFILE on)
message("&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&")
message(" CMake AMD SMI C/C++ Library ")
message("&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&")
@@ -81,7 +81,7 @@ configure_file("${AMD_SMI_TARGET}Config.in" "${PROJECT_SOURCE_DIR}/include/amd_s
add_executable(amd_smi_ex "../example/amd_smi_drm_example.cc")
target_link_libraries(amd_smi_ex ${AMD_SMI_TARGET})
add_library(${AMD_SMI_TARGET} ${SRC_LIST} ${INC_LIST})
target_link_libraries(${AMD_SMI_TARGET} pthread rt dl ${DRM_LIBRARIES} ${AMDGPU_DRM_LIBRARIES})
target_link_libraries(${AMD_SMI_TARGET} pthread rt dl)
target_include_directories(${AMD_SMI_TARGET} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR} ${PROJECT_SOURCE_DIR}/rocm_smi/include
${PROJECT_SOURCE_DIR}/common/shared_mutex)
src/amd_smi/amd_smi.cc
+641 -144
Wyświetl plik
@@ -21,14 +21,14 @@
*/
#include <assert.h>
#include <cstdlib>
#include <errno.h>
#include <sys/utsname.h>
#include <stdio.h>
#include <string.h>
#include <fcntl.h>
#include <xf86drm.h>
#include <cstdlib>
#include <string>
#include <algorithm>
#include <sstream>
@@ -50,14 +50,13 @@
#include "amd_smi/impl/amd_smi_socket.h"
#include "amd_smi/impl/amd_smi_gpu_device.h"
#include "amd_smi/impl/amd_smi_uuid.h"
#include "rocm_smi/rocm_smi.h"
#include "rocm_smi/rocm_smi_common.h"
#include "amd_smi/impl/amdgpu_drm.h"
#include "amd_smi/impl/xf86drm.h"
#include "amd_smi/impl/amd_smi_utils.h"
#include "amd_smi/impl/amd_smi_processor.h"
#include "rocm_smi/rocm_smi.h"
#include "rocm_smi/rocm_smi_common.h"
#include "rocm_smi/rocm_smi_logger.h"
#include "rocm_smi/rocm_smi_utils.h"
#include "rocm_smi/rocm_smi.h"
#include "rocm_smi/rocm_smi_kfd.h"
// a global instance of std::mutex to protect data passed during threads
@@ -146,6 +145,9 @@ amdsmi_status_t rsmi_wrapper(F && f,
std::ostringstream ss;
amd::smi::AMDSmiGPUDevice* gpu_device = nullptr;
amdsmi_status_t r = get_gpu_device_from_handle(processor_handle, &gpu_device);
ss << __PRETTY_FUNCTION__ << " | get_gpu_device_from_handle status = "
<< smi_amdgpu_get_status_string(r, false);
LOG_INFO(ss);
if (r != AMDSMI_STATUS_SUCCESS) return r;
@@ -888,28 +890,111 @@ amdsmi_status_t amdsmi_get_gpu_vram_usage(amdsmi_processor_handle processor_hand
struct drm_amdgpu_info_vram_gtt gtt;
uint64_t vram_used = 0;
std::ostringstream ss;
amd::smi::AMDSmiSystem::getInstance().init_drm();
r = gpu_device->amdgpu_query_info(AMDGPU_INFO_VRAM_GTT,
sizeof(struct drm_amdgpu_memory_info), &gtt);
if (r != AMDSMI_STATUS_SUCCESS) {
amd::smi::AMDSmiSystem::getInstance().clean_up_drm();
return r;
SMIGPUDEVICE_MUTEX(gpu_device->get_mutex());
std::string render_name = gpu_device->get_gpu_path();
int drm_fd = -1;
std::string path = "/dev/dri/" + render_name;
if (render_name != "") {
drm_fd = open(path.c_str(), O_RDWR | O_CLOEXEC);
} else {
close(drm_fd);
return AMDSMI_STATUS_NOT_SUPPORTED;
}
ss << __PRETTY_FUNCTION__
<< " | open(" << path << ") returned: " << strerror(errno) << "\n"
<< " | drm_fd: " << std::dec << drm_fd << "\n"
<< " | render_name: " << render_name << "\n";
LOG_INFO(ss);
amd::smi::AMDSmiLibraryLoader libdrm;
amdsmi_status_t status = libdrm.load("libdrm.so.2");
if (status != AMDSMI_STATUS_SUCCESS) {
close(drm_fd);
libdrm.unload();
ss << __PRETTY_FUNCTION__
<< " | Failed to load libdrm.so.2: " << strerror(errno)
<< "; Returning: " << smi_amdgpu_get_status_string(status, false);
LOG_ERROR(ss);
return status;
}
ss << __PRETTY_FUNCTION__
<< " | about to load drmCommandWrite symbol";
LOG_INFO(ss);
// extern int drmCommandWrite(int fd, unsigned long drmCommandIndex,
// void *data, unsigned long size);
typedef int (*drmCommandWrite_t)(int fd, unsigned long drmCommandIndex,
void *data, unsigned long size);
drmCommandWrite_t drmCommandWrite = nullptr;
// load symbol from libdrm
status = libdrm.load_symbol(reinterpret_cast<drmCommandWrite_t *>(&drmCommandWrite),
"drmCommandWrite");
if (status != AMDSMI_STATUS_SUCCESS) {
close(drm_fd);
libdrm.unload();
ss << __PRETTY_FUNCTION__
<< " | Failed to load drmCommandWrite symbol"
<< " | Returning: " << smi_amdgpu_get_status_string(status, false);
LOG_ERROR(ss);
return status;
}
ss << __PRETTY_FUNCTION__
<< " | drmCommandWrite symbol loaded successfully";
LOG_INFO(ss);
// Get the device info
memset(&gtt, 0, sizeof(struct drm_amdgpu_info_vram_gtt));
struct drm_amdgpu_info request = {};
memset(&request, 0, sizeof(request));
request.return_pointer = reinterpret_cast<unsigned long long>(&gtt);
request.return_size = sizeof(struct drm_amdgpu_memory_info);
request.query = AMDGPU_INFO_VRAM_GTT;
auto drm_write = drmCommandWrite(drm_fd, DRM_AMDGPU_INFO, &request,
sizeof(struct drm_amdgpu_info));
if (drm_write != 0) {
close(drm_fd);
libdrm.unload();
ss << __PRETTY_FUNCTION__
<< " | Issue - drm_write failed, drm_write (AMDGPU_INFO_VRAM_GTT): "
<< std::dec << drm_write << "\n"
<< "; Returning: " << smi_amdgpu_get_status_string(AMDSMI_STATUS_DRM_ERROR, false);
LOG_ERROR(ss);
return AMDSMI_STATUS_DRM_ERROR;
}
vram_info->vram_total = static_cast<uint32_t>(
gtt.vram_size / (1024 * 1024));
r = gpu_device->amdgpu_query_info(AMDGPU_INFO_VRAM_USAGE,
sizeof(vram_used), &vram_used);
amd::smi::AMDSmiSystem::getInstance().clean_up_drm();
if (r != AMDSMI_STATUS_SUCCESS) {
return r;
memset(&request, 0, sizeof(request));
request.return_pointer = reinterpret_cast<unsigned long long>(&vram_used);
request.return_size = sizeof(vram_used);
request.query = AMDGPU_INFO_VRAM_USAGE;
drm_write = drmCommandWrite(drm_fd, DRM_AMDGPU_INFO, &request,
sizeof(struct drm_amdgpu_info));
if (drm_write != 0) {
close(drm_fd);
libdrm.unload();
ss << __PRETTY_FUNCTION__
<< " | Issue - drm_write failed, drm_write (AMDGPU_INFO_VRAM_USAGE): "
<< std::dec << drm_write << "\n"
<< "; Returning: " << smi_amdgpu_get_status_string(AMDSMI_STATUS_DRM_ERROR, false);
LOG_ERROR(ss);
return AMDSMI_STATUS_DRM_ERROR;
}
vram_info->vram_used = static_cast<uint32_t>(vram_used / (1024 * 1024));
close(drm_fd);
libdrm.unload();
ss << __PRETTY_FUNCTION__
<< " | vram_info->vram_total (MB): " << std::dec << vram_info->vram_total << "\n"
<< " | vram_info->vram_used (MB): " << std::dec << vram_info->vram_used << "\n"
<< " | Returning: " << smi_amdgpu_get_status_string(AMDSMI_STATUS_SUCCESS, false);
LOG_INFO(ss);
return AMDSMI_STATUS_SUCCESS;
}
@@ -1343,6 +1428,7 @@ amdsmi_get_gpu_asic_info(amdsmi_processor_handle processor_handle, amdsmi_asic_i
struct drm_amdgpu_info_device dev_info = {};
uint16_t vendor_id = 0;
uint16_t subvendor_id = 0;
uint16_t device_id = 0;
std::ostringstream ss;
amd::smi::AMDSmiGPUDevice* gpu_device = nullptr;
@@ -1350,48 +1436,85 @@ amdsmi_get_gpu_asic_info(amdsmi_processor_handle processor_handle, amdsmi_asic_i
if (r != AMDSMI_STATUS_SUCCESS) {
return r;
}
SMIGPUDEVICE_MUTEX(gpu_device->get_mutex())
amdsmi_status_t status = smi_amdgpu_get_market_name_from_dev_id(gpu_device, info->market_name);
if (status != AMDSMI_STATUS_SUCCESS) {
rsmi_wrapper(rsmi_dev_brand_get, processor_handle, 0,
info->market_name, AMDSMI_256_LENGTH);
}
amdsmi_status_t status;
amd::smi::AMDSmiSystem::getInstance().init_drm();
// removing drm check for now due to drm issues
if (gpu_device->check_if_drm_is_supported()) {
status = gpu_device->amdgpu_query_info(AMDGPU_INFO_DEV_INFO,
sizeof(struct drm_amdgpu_info_device), &dev_info);
std::string render_name = gpu_device->get_gpu_path();
int drm_fd = -1;
std::string path = "/dev/dri/" + render_name;
if (render_name != "") {
drm_fd = open(path.c_str(), O_RDWR | O_CLOEXEC);
} else {
close(drm_fd);
return AMDSMI_STATUS_NOT_SUPPORTED;
}
ss << __PRETTY_FUNCTION__
<< " | open(" << path << ") returned: " << strerror(errno) << "\n"
<< " | drm_fd: " << std::dec << drm_fd << "\n"
<< " | render_name: " << render_name << "\n";
LOG_INFO(ss);
amd::smi::AMDSmiLibraryLoader libdrm;
status = libdrm.load("libdrm.so.2");
if (status != AMDSMI_STATUS_SUCCESS) {
close(drm_fd);
libdrm.unload();
ss << __PRETTY_FUNCTION__
<< " | amdgpu_query_info(): "
<< smi_amdgpu_get_status_string(status, true);
LOG_INFO(ss);
if (status != AMDSMI_STATUS_SUCCESS) {
amd::smi::AMDSmiSystem::getInstance().clean_up_drm();
return status;
}
SMIGPUDEVICE_MUTEX(gpu_device->get_mutex())
status = smi_amdgpu_get_market_name_from_dev_id(gpu_device, info->market_name);
if (status != AMDSMI_STATUS_SUCCESS) {
rsmi_wrapper(rsmi_dev_brand_get, processor_handle, 0,
info->market_name, AMDSMI_256_LENGTH);
}
// info->device_id = dev_info.device_id;
// info->rev_id = dev_info.pci_rev;
// info->vendor_id = gpu_device->get_vendor_id();
<< " | Failed to load libdrm.so.2: " << strerror(errno)
<< "; Returning: " << smi_amdgpu_get_status_string(status, false);
LOG_ERROR(ss);
return status;
}
else {
status = rsmi_wrapper(rsmi_dev_brand_get, processor_handle, 0,
info->market_name, AMDSMI_256_LENGTH);
// extern int drmCommandWrite(int fd, unsigned long drmCommandIndex,
// void *data, unsigned long size);
typedef int (*drmCommandWrite_t)(int fd, unsigned long drmCommandIndex,
void *data, unsigned long size);
drmCommandWrite_t drmCommandWrite = nullptr;
// load symbol from libdrm
status = libdrm.load_symbol(reinterpret_cast<drmCommandWrite_t *>(&drmCommandWrite),
"drmCommandWrite");
if (status != AMDSMI_STATUS_SUCCESS) {
close(drm_fd);
libdrm.unload();
ss << __PRETTY_FUNCTION__
<< " | Failed to load drmCommandWrite symbol"
<< " | Returning: " << smi_amdgpu_get_status_string(status, false);
LOG_ERROR(ss);
return status;
}
uint16_t device_id = std::numeric_limits<uint16_t>::max();
status = rsmi_wrapper(rsmi_dev_id_get, processor_handle, 0, &device_id);
if (status == AMDSMI_STATUS_SUCCESS) info->device_id = static_cast<uint64_t>(device_id);
uint16_t rev_id = std::numeric_limits<uint16_t>::max();
status = rsmi_wrapper(rsmi_dev_revision_get, processor_handle, 0, &rev_id);
if (status == AMDSMI_STATUS_SUCCESS) info->rev_id = static_cast<uint32_t>(rev_id);
// Get the device info
memset(&dev_info, 0, sizeof(struct drm_amdgpu_info_device));
struct drm_amdgpu_info request = {};
memset(&request, 0, sizeof(request));
request.return_pointer = reinterpret_cast<unsigned long long>(&dev_info);
request.return_size = sizeof(struct drm_amdgpu_info_device);
request.query = AMDGPU_INFO_DEV_INFO;
auto drm_write = drmCommandWrite(drm_fd, DRM_AMDGPU_INFO, &request,
sizeof(struct drm_amdgpu_info));
if (drm_write != 0) {
libdrm.unload();
close(drm_fd);
ss << __PRETTY_FUNCTION__
<< " | Issue - drm_write failed, drm_write: " << std::dec << drm_write << "\n"
<< "; Returning: " << smi_amdgpu_get_status_string(AMDSMI_STATUS_DRM_ERROR, false);
LOG_ERROR(ss);
return AMDSMI_STATUS_DRM_ERROR;
}
// TODO(cpoag): check if this is correct, might be able to go through KGD/KFD
info->rev_id = static_cast<uint32_t>(dev_info.pci_rev);
libdrm.unload();
close(drm_fd);
status = rsmi_wrapper(rsmi_dev_vendor_id_get, processor_handle, 0,
&vendor_id);
if (status == AMDSMI_STATUS_SUCCESS) info->vendor_id = vendor_id;
// For other sysfs related information, get from rocm-smi
/**
* For other sysfs related information, get from rocm-smi
*/
// Ensure asic_serial defaults to an unsupported value
std::string max_uint64_str = "ffffffffffffffff";
@@ -1421,13 +1544,6 @@ amdsmi_get_gpu_asic_info(amdsmi_processor_handle processor_handle, amdsmi_asic_i
status = rsmi_wrapper(rsmi_dev_pcie_vendor_name_get, processor_handle, 0,
info->vendor_name, AMDSMI_MAX_STRING_LENGTH);
// If vendor name is empty and the vendor id is 0x1002, set vendor name to AMD vendor string
if ((info->vendor_name != NULL && info->vendor_name[0] == '\0') && info->vendor_id == 0x1002) {
std::string amd_name = "Advanced Micro Devices Inc. [AMD/ATI]";
memset(info->vendor_name, 0, amd_name.size()+1);
strncpy(info->vendor_name, amd_name.c_str(), amd_name.size()+1);
}
// default to 0xffff as not supported
info->oam_id = std::numeric_limits<uint16_t>::max();
uint16_t tmp_oam_id = 0;
@@ -1452,8 +1568,60 @@ amdsmi_get_gpu_asic_info(amdsmi_processor_handle processor_handle, amdsmi_asic_i
if (status == amdsmi_status_t::AMDSMI_STATUS_SUCCESS) {
info->target_graphics_version = tmp_target_gfx_version;
}
amd::smi::AMDSmiSystem::getInstance().clean_up_drm();
status = rsmi_wrapper(rsmi_dev_id_get, processor_handle, 0,
&device_id);
ss << __PRETTY_FUNCTION__ << " | rsmi_dev_id_get() returned: "
<< smi_amdgpu_get_status_string(status, true) << "\n"
<< " ; device_id (dec): " << std::dec << device_id << "\n"
<< " ; device_id (hex): 0x"
<< std::hex << std::setw(4) << std::setfill('0') << device_id << std::dec;
LOG_INFO(ss);
if (status == AMDSMI_STATUS_SUCCESS) {
info->device_id = static_cast<uint64_t>(device_id);
} else {
info->device_id = std::numeric_limits<uint64_t>::max();
}
info->rev_id = dev_info.pci_rev;
status = rsmi_wrapper(rsmi_dev_vendor_id_get, processor_handle, 0,
&vendor_id);
if (status == AMDSMI_STATUS_SUCCESS) {
info->vendor_id = vendor_id;
} else {
info->vendor_id = std::numeric_limits<uint32_t>::max();
}
// If vendor name is empty and the vendor id is 0x1002, set vendor name to AMD vendor string
if ((info->vendor_name != NULL && info->vendor_name[0] == '\0') && info->vendor_id == 0x1002) {
std::string amd_name = "Advanced Micro Devices Inc. [AMD/ATI]";
smi_clear_char_and_reinitialize(info->vendor_name, AMDSMI_MAX_STRING_LENGTH, amd_name);
}
ss << __PRETTY_FUNCTION__
<< " | info->market_name: " << info->market_name << "\n"
<< " | info->vendor_id (dec): " << std::dec << info->vendor_id << "\n"
<< " | info->vendor_id (hex): 0x"
<< std::hex << std::setw(4) << std::setfill('0') << info->vendor_id << "\n"
<< " | info->vendor_name: " << info->vendor_name << "\n"
<< " | info->subvendor_id (dec): " << std::dec << info->subvendor_id << "\n"
<< " | info->subvendor_id (hex): 0x"
<< std::hex << std::setw(4) << std::setfill('0') << info->subvendor_id << "\n"
<< " | info->device_id (dec): " << std::dec << info->device_id << "\n"
<< " | info->device_id (hex): 0x"
<< std::hex << std::setw(4) << std::setfill('0') << info->device_id << "\n"
<< " | info->rev_id (dec): " << std::dec << info->rev_id << "\n"
<< " | info->rev_id (hex): 0x"
<< std::hex << std::setw(4) << std::setfill('0') << info->rev_id << "\n"
<< " | info->asic_serial: 0x" << info->asic_serial << "\n"
<< " | info->oam_id (dec): " << std::dec << info->oam_id << "\n"
<< " | info->oam_id (hex): 0x"
<< std::hex << std::setw(4) << std::setfill('0') << info->oam_id << "\n"
<< " | info->num_of_compute_units (dec): " << std::dec
<< info->num_of_compute_units << "\n"
<< " | info->target_graphics_version: gfx"
<< std::hex << info->target_graphics_version << "\n"
<< " | Returning: " << smi_amdgpu_get_status_string(AMDSMI_STATUS_SUCCESS, true);
LOG_INFO(ss);
return AMDSMI_STATUS_SUCCESS;
}
@@ -1581,6 +1749,7 @@ amdsmi_status_t amdsmi_get_gpu_vram_info(
return r;
}
std::ostringstream ss;
// init the info structure with default value
info->vram_type = AMDSMI_VRAM_TYPE_UNKNOWN;
info->vram_size = 0;
@@ -1588,18 +1757,83 @@ amdsmi_status_t amdsmi_get_gpu_vram_info(
info->vram_bit_width = std::numeric_limits<decltype(info->vram_bit_width)>::max();
info->vram_max_bandwidth = std::numeric_limits<decltype(info->vram_max_bandwidth)>::max();
amd::smi::AMDSmiSystem::getInstance().init_drm();
// Only can read vram type from libdrm
if (gpu_device->check_if_drm_is_supported()) {
struct drm_amdgpu_info_device dev_info = {};
r = gpu_device->amdgpu_query_info(
AMDGPU_INFO_DEV_INFO,
sizeof(struct drm_amdgpu_info_device), &dev_info);
if (r == AMDSMI_STATUS_SUCCESS) {
info->vram_type = amd::smi::vram_type_value(dev_info.vram_type);
info->vram_bit_width = dev_info.vram_bit_width;
}
SMIGPUDEVICE_MUTEX(gpu_device->get_mutex());
std::string render_name = gpu_device->get_gpu_path();
int drm_fd = -1;
std::string path = "/dev/dri/" + render_name;
if (render_name != "") {
drm_fd = open(path.c_str(), O_RDWR | O_CLOEXEC);
} else {
close(drm_fd);
return AMDSMI_STATUS_NOT_SUPPORTED;
}
ss << __PRETTY_FUNCTION__
<< " | open(" << path << ") returned: " << strerror(errno) << "\n"
<< " | drm_fd: " << std::dec << drm_fd << "\n"
<< " | render_name: " << render_name << "\n";
LOG_INFO(ss);
amd::smi::AMDSmiLibraryLoader libdrm;
amdsmi_status_t status = libdrm.load("libdrm.so.2");
if (status != AMDSMI_STATUS_SUCCESS) {
close(drm_fd);
libdrm.unload();
ss << __PRETTY_FUNCTION__
<< " | Failed to load libdrm.so.2: " << strerror(errno)
<< "; Returning: " << smi_amdgpu_get_status_string(status, false);
LOG_ERROR(ss);
return status;
}
ss << __PRETTY_FUNCTION__
<< " | about to load drmCommandWrite symbol";
LOG_INFO(ss);
// extern int drmCommandWrite(int fd, unsigned long drmCommandIndex,
// void *data, unsigned long size);
typedef int (*drmCommandWrite_t)(int fd, unsigned long drmCommandIndex,
void *data, unsigned long size);
drmCommandWrite_t drmCommandWrite = nullptr;
// load symbol from libdrm
status = libdrm.load_symbol(reinterpret_cast<drmCommandWrite_t *>(&drmCommandWrite),
"drmCommandWrite");
if (status != AMDSMI_STATUS_SUCCESS) {
close(drm_fd);
libdrm.unload();
ss << __PRETTY_FUNCTION__
<< " | Failed to load drmCommandWrite symbol"
<< " | Returning: " << smi_amdgpu_get_status_string(status, false);
LOG_ERROR(ss);
return status;
}
ss << __PRETTY_FUNCTION__
<< " | drmCommandWrite symbol loaded successfully";
LOG_INFO(ss);
struct drm_amdgpu_info_device dev_info = {};
memset(&dev_info, 0, sizeof(struct drm_amdgpu_info_device));
struct drm_amdgpu_info request = {};
memset(&request, 0, sizeof(request));
request.return_pointer = reinterpret_cast<unsigned long long>(&dev_info);
request.return_size = sizeof(struct drm_amdgpu_info_device);
request.query = AMDGPU_INFO_DEV_INFO;
auto drm_write = drmCommandWrite(drm_fd, DRM_AMDGPU_INFO, &request,
sizeof(struct drm_amdgpu_info));
if (drm_write != 0) {
close(drm_fd);
libdrm.unload();
ss << __PRETTY_FUNCTION__
<< " | Issue - drm_write failed, drm_write: " << std::dec << drm_write << "\n"
<< "; Returning: " << smi_amdgpu_get_status_string(AMDSMI_STATUS_DRM_ERROR, false);
LOG_ERROR(ss);
return AMDSMI_STATUS_DRM_ERROR;
}
info->vram_type = amd::smi::vram_type_value(dev_info.vram_type);
info->vram_bit_width = dev_info.vram_bit_width;
close(drm_fd);
libdrm.unload();
// set info->vram_max_bandwidth to gpu_metrics vram_max_bandwidth if it is not set
amdsmi_gpu_metrics_t metric_info = {};
@@ -1644,8 +1878,18 @@ amdsmi_status_t amdsmi_get_gpu_vram_info(
if (r == AMDSMI_STATUS_SUCCESS) {
info->vram_size = total / (1024 * 1024);
}
amd::smi::AMDSmiSystem::getInstance().clean_up_drm();
ss << __PRETTY_FUNCTION__
<< " | info->vram_type: " << std::dec << info->vram_type << "\n"
<< "; info->vram_size (MB): " << std::dec << info->vram_size << "\n"
<< "; info->vram_vendor: " << std::dec << info->vram_vendor << "\n"
<< "; info->vram_bit_width: " << std::dec
<< (info->vram_bit_width == std::numeric_limits<uint64_t>::max() ?
"N/A" : std::to_string(info->vram_bit_width)) << "\n"
<< "; info->vram_max_bandwidth (GB/s): " << std::dec
<< info->vram_max_bandwidth << "\n"
<< "; Returning: " << smi_amdgpu_get_status_string(AMDSMI_STATUS_SUCCESS, false);
LOG_INFO(ss);
return AMDSMI_STATUS_SUCCESS;
}
@@ -1940,7 +2184,6 @@ amdsmi_set_gpu_memory_partition(amdsmi_processor_handle processor_handle,
return AMDSMI_STATUS_INVAL;
}
amd::smi::AMDSmiSystem::getInstance().clean_up_drm();
amdsmi_status_t ret = rsmi_wrapper(rsmi_dev_memory_partition_set, processor_handle, 0,
rsmi_type);
@@ -3250,7 +3493,12 @@ amdsmi_status_t amdsmi_set_gpu_clk_limit(amdsmi_processor_handle processor_handl
}
amdsmi_status_t amdsmi_reset_gpu(amdsmi_processor_handle processor_handle) {
return rsmi_wrapper(rsmi_dev_gpu_reset, processor_handle, 0);
std::ostringstream ss;
amdsmi_status_t ret = rsmi_wrapper(rsmi_dev_gpu_reset, processor_handle, 0);
ss << __PRETTY_FUNCTION__
<< " | Returning: " << smi_amdgpu_get_status_string(ret, false);
LOG_INFO(ss);
return ret;
}
amdsmi_status_t amdsmi_get_gpu_busy_percent(amdsmi_processor_handle processor_handle,
@@ -3308,24 +3556,84 @@ amdsmi_get_gpu_vbios_info(amdsmi_processor_handle processor_handle, amdsmi_vbios
struct drm_amdgpu_info_vbios vbios = {};
amdsmi_status_t status;
std::ostringstream ss;
amd::smi::AMDSmiGPUDevice* gpu_device = nullptr;
status = get_gpu_device_from_handle(processor_handle, &gpu_device);
if (status != AMDSMI_STATUS_SUCCESS)
if (status != AMDSMI_STATUS_SUCCESS) {
return status;
}
amd::smi::AMDSmiSystem::getInstance().init_drm();
// requires libdrm being active & available, if not defaults to rocm_smi
if (gpu_device->check_if_drm_is_supported()) {
status = gpu_device->amdgpu_query_vbios(&vbios);
if (status == AMDSMI_STATUS_SUCCESS) {
strncpy(info->name, reinterpret_cast<char *>(vbios.name), AMDSMI_MAX_STRING_LENGTH);
strncpy(info->build_date, reinterpret_cast<char *>(vbios.date), AMDSMI_MAX_DATE_LENGTH);
strncpy(info->part_number, reinterpret_cast<char *>(vbios.vbios_pn),
AMDSMI_MAX_STRING_LENGTH);
strncpy(info->version, reinterpret_cast<char *>(vbios.vbios_ver_str),
AMDSMI_MAX_STRING_LENGTH);
}
SMIGPUDEVICE_MUTEX(gpu_device->get_mutex());
std::string render_name = gpu_device->get_gpu_path();
int drm_fd = -1;
std::string path = "/dev/dri/" + render_name;
if (render_name != "") {
drm_fd = open(path.c_str(), O_RDWR | O_CLOEXEC);
} else {
close(drm_fd);
return AMDSMI_STATUS_NOT_SUPPORTED;
}
ss << __PRETTY_FUNCTION__
<< " | open(" << path << ") returned: " << strerror(errno) << "\n"
<< " | drm_fd: " << std::dec << drm_fd << "\n"
<< " | render_name: " << render_name << "\n";
LOG_INFO(ss);
amd::smi::AMDSmiLibraryLoader libdrm;
status = libdrm.load("libdrm.so.2");
if (status != AMDSMI_STATUS_SUCCESS) {
close(drm_fd);
libdrm.unload();
ss << __PRETTY_FUNCTION__
<< " | Failed to load libdrm.so.2: " << strerror(errno)
<< "; Returning: " << smi_amdgpu_get_status_string(status, false);
LOG_ERROR(ss);
return status;
}
ss << __PRETTY_FUNCTION__
<< " | about to load drmCommandWrite symbol";
LOG_INFO(ss);
// extern int drmCommandWrite(int fd, unsigned long drmCommandIndex,
// void *data, unsigned long size);
typedef int (*drmCommandWrite_t)(int fd, unsigned long drmCommandIndex,
void *data, unsigned long size);
drmCommandWrite_t drmCommandWrite = nullptr;
// load symbol from libdrm
status = libdrm.load_symbol(reinterpret_cast<drmCommandWrite_t *>(&drmCommandWrite),
"drmCommandWrite");
if (status != AMDSMI_STATUS_SUCCESS) {
libdrm.unload();
close(drm_fd);
ss << __PRETTY_FUNCTION__
<< " | Failed to load drmCommandWrite symbol"
<< " | Returning: " << smi_amdgpu_get_status_string(status, false);
LOG_ERROR(ss);
return status;
}
ss << __PRETTY_FUNCTION__
<< " | drmCommandWrite symbol loaded successfully";
LOG_INFO(ss);
memset(&vbios, 0, sizeof(struct drm_amdgpu_info_vbios));
struct drm_amdgpu_info request = {};
memset(&request, 0, sizeof(request));
request.return_pointer = reinterpret_cast<uint64_t>(&vbios);
request.return_size = sizeof(drm_amdgpu_info_vbios);
request.query = AMDGPU_INFO_VBIOS;
request.vbios_info.type = AMDGPU_INFO_VBIOS_INFO;
auto drm_write = drmCommandWrite(drm_fd, DRM_AMDGPU_INFO, &request,
sizeof(struct drm_amdgpu_info));
if (drm_write == 0) {
strncpy(info->name, reinterpret_cast<char *>(vbios.name), AMDSMI_MAX_STRING_LENGTH);
strncpy(info->build_date, reinterpret_cast<char *>(vbios.date), AMDSMI_MAX_DATE_LENGTH);
strncpy(info->part_number, reinterpret_cast<char *>(vbios.vbios_pn),
AMDSMI_MAX_STRING_LENGTH);
strncpy(info->version, reinterpret_cast<char *>(vbios.vbios_ver_str),
AMDSMI_MAX_STRING_LENGTH);
} else {
// get vbios version string from rocm_smi
char vbios_version[AMDSMI_MAX_STRING_LENGTH];
@@ -3339,8 +3647,16 @@ amdsmi_get_gpu_vbios_info(amdsmi_processor_handle processor_handle, amdsmi_vbios
vbios_version, AMDSMI_MAX_STRING_LENGTH);
}
}
amd::smi::AMDSmiSystem::getInstance().clean_up_drm();
close(drm_fd);
libdrm.unload();
ss << __PRETTY_FUNCTION__
<< " | drmCommandWrite returned: " << strerror(errno) << "\n"
<< " | vbios name: " << info->name << "\n"
<< " | vbios build date: " << info->build_date << "\n"
<< " | vbios part number: " << info->part_number << "\n"
<< " | vbios version: " << info->version << "\n"
<< " | Returning: " << smi_amdgpu_get_status_string(status, false);
LOG_INFO(ss);
return status;
}
@@ -3731,6 +4047,7 @@ amdsmi_status_t amdsmi_get_gpu_driver_info(amdsmi_processor_handle processor_han
if (info == nullptr) {
return AMDSMI_STATUS_INVAL;
}
std::ostringstream ss;
amdsmi_status_t status = AMDSMI_STATUS_SUCCESS;
amd::smi::AMDSmiGPUDevice* gpu_device = nullptr;
amdsmi_status_t r = get_gpu_device_from_handle(processor_handle, &gpu_device);
@@ -3740,17 +4057,75 @@ amdsmi_status_t amdsmi_get_gpu_driver_info(amdsmi_processor_handle processor_han
int length = AMDSMI_MAX_STRING_LENGTH;
// Get the driver version
amd::smi::AMDSmiSystem::getInstance().init_drm();
status = smi_amdgpu_get_driver_version(gpu_device,
&length, info->driver_version);
SMIGPUDEVICE_MUTEX(gpu_device->get_mutex())
std::string render_name = gpu_device->get_gpu_path();
int drm_fd = -1;
std::string path = "/dev/dri/" + render_name;
if (render_name != "") {
drm_fd = open(path.c_str(), O_RDWR | O_CLOEXEC);
} else {
close(drm_fd);
return AMDSMI_STATUS_NOT_SUPPORTED;
}
amd::smi::AMDSmiLibraryLoader libdrm;
status = libdrm.load("libdrm.so.2");
if (status != AMDSMI_STATUS_SUCCESS) {
close(drm_fd);
libdrm.unload();
ss << __PRETTY_FUNCTION__
<< " | Failed to load libdrm.so.2"
<< "; Returning: " << smi_amdgpu_get_status_string(status, false);
LOG_ERROR(ss);
return status;
}
// Define a function pointer for drmGetVersion
typedef struct _drmVersion* (*drmGetVersion_t)(int fd); // drmGetVersion
drmGetVersion_t drm_get_version = nullptr;
typedef void (*drmFreeVersion_t)(drmVersionPtr version); // drmFreeVersion
drmFreeVersion_t drm_free_version = nullptr;
status = libdrm.load_symbol(
reinterpret_cast<drmGetVersion_t *>(&drm_get_version), "drmGetVersion");
if (status != AMDSMI_STATUS_SUCCESS) {
close(drm_fd);
libdrm.unload();
ss << __PRETTY_FUNCTION__
<< " | Failed to load drmGetVersion symbol"
<< "; Returning: " << smi_amdgpu_get_status_string(status, false);
LOG_ERROR(ss);
return status;
}
status = libdrm.load_symbol(
reinterpret_cast<drmGetVersion_t *>(&drm_free_version), "drmFreeVersion");
if (status != AMDSMI_STATUS_SUCCESS) {
close(drm_fd);
libdrm.unload();
ss << __PRETTY_FUNCTION__
<< " | Failed to load drmFreeVersion symbol"
<< "; Returning: " << smi_amdgpu_get_status_string(status, false);
LOG_ERROR(ss);
return status;
}
// Get the driver date
std::string driver_date;
status = gpu_device->amdgpu_query_driver_date(driver_date);
if (status != AMDSMI_STATUS_SUCCESS) {
amd::smi::AMDSmiSystem::getInstance().clean_up_drm();
return r;
auto version = drm_get_version(drm_fd);
if (version == nullptr) {
close(drm_fd);
libdrm.unload();
ss << __PRETTY_FUNCTION__
<< " | Failed to get driver version"
<< "; Returning: " << smi_amdgpu_get_status_string(AMDSMI_STATUS_DRM_ERROR, false);
LOG_ERROR(ss);
return AMDSMI_STATUS_DRM_ERROR;
}
driver_date = version->date;
// Reformat the driver date from 20150101 to 2015/01/01 00:00
if (driver_date.length() == 8) {
driver_date = driver_date.substr(0, 4) + "/" + driver_date.substr(4, 2)
@@ -3759,13 +4134,17 @@ amdsmi_status_t amdsmi_get_gpu_driver_info(amdsmi_processor_handle processor_han
strncpy(info->driver_date, driver_date.c_str(), AMDSMI_MAX_STRING_LENGTH-1);
// Get the driver name
std::string driver_name;
status = gpu_device->amdgpu_query_driver_name(driver_name);
amd::smi::AMDSmiSystem::getInstance().clean_up_drm();
if (status != AMDSMI_STATUS_SUCCESS)
return r;
std::string driver_name = version->name;
strncpy(info->driver_name, driver_name.c_str(), AMDSMI_MAX_STRING_LENGTH-1);
drm_free_version(version);
close(drm_fd);
libdrm.unload();
ss << __PRETTY_FUNCTION__
<< " | Driver version: " << info->driver_version << "\n"
<< " | Driver date: " << info->driver_date << "\n"
<< " | Driver name: " << info->driver_name << "\n"
<< " | Returning: " << smi_amdgpu_get_status_string(status, false);
LOG_INFO(ss);
return status;
}
@@ -4159,11 +4538,22 @@ amdsmi_get_link_topology_nearest(amdsmi_processor_handle processor_handle,
return status;
}
static const std::map<amdsmi_virtualization_mode_t, std::string>
virtualization_mode_map = {
{AMDSMI_VIRTUALIZATION_MODE_UNKNOWN, "UNKNOWN"},
{AMDSMI_VIRTUALIZATION_MODE_BAREMETAL, "BAREMETAL"},
{ AMDSMI_VIRTUALIZATION_MODE_HOST, "HOST"},
{ AMDSMI_VIRTUALIZATION_MODE_GUEST, "GUEST"},
{AMDSMI_VIRTUALIZATION_MODE_PASSTHROUGH, "PASSTHROUGH"}
};
amdsmi_status_t
amdsmi_get_gpu_virtualization_mode(amdsmi_processor_handle processor_handle,
amdsmi_virtualization_mode_t *mode) {
AMDSMI_CHECK_INIT();
std::ostringstream ss;
ss << __PRETTY_FUNCTION__ << " | start";
LOG_INFO(ss);
if (mode == nullptr) {
return AMDSMI_STATUS_INVAL;
}
@@ -4178,45 +4568,136 @@ amdsmi_get_gpu_virtualization_mode(amdsmi_processor_handle processor_handle,
}
amdsmi_status_t status;
amd::smi::AMDSmiSystem::getInstance().init_drm();
// requires libdrm being active
if (gpu_device->check_if_drm_is_supported()) {
status = gpu_device->amdgpu_query_info(AMDGPU_INFO_DEV_INFO,
sizeof(struct drm_amdgpu_info_device), &dev_info);
if (status != AMDSMI_STATUS_SUCCESS) {
amd::smi::AMDSmiSystem::getInstance().clean_up_drm();
return status;
}
SMIGPUDEVICE_MUTEX(gpu_device->get_mutex())
SMIGPUDEVICE_MUTEX(gpu_device->get_mutex())
std::string render_name = gpu_device->get_gpu_path();
int drm_fd = -1;
std::string path = "/dev/dri/" + render_name;
if (render_name != "") {
drm_fd = open(path.c_str(), O_RDWR | O_CLOEXEC);
} else {
close(drm_fd);
return AMDSMI_STATUS_NOT_SUPPORTED;
}
// get drm version. If it's older than 3.62.0, then say not supported and exit.
drmVersionPtr drm_version;
std::string render_name = gpu_device->get_gpu_path();
int drm_fd = -1;
std::string path = "/dev/dri/" + render_name;
if (render_name != "") {
drm_fd = open(path.c_str(), O_RDWR | O_CLOEXEC);
} else {
close(drm_fd);
return AMDSMI_STATUS_NOT_SUPPORTED;
}
amd::smi::AMDSmiLibraryLoader libdrm;
status = libdrm.load("libdrm.so.2");
if (status != AMDSMI_STATUS_SUCCESS) {
close(drm_fd);
libdrm.unload();
ss << __PRETTY_FUNCTION__
<< " | Failed to load libdrm.so.2"
<< "; Returning: " << smi_amdgpu_get_status_string(status, false);
LOG_ERROR(ss);
return status;
}
drm_version = drmGetVersion(drm_fd);
typedef drmVersionPtr (*drmGetVersion_t)(int fd);
typedef void (*drmFreeVersion_t)(drmVersionPtr version);
// minimum version that supports getting of virtualization mode
int major_version = 3;
int minor_version = 62;
int patch_version = 0;
drmGetVersion_t drm_get_version = nullptr;
drmFreeVersion_t drm_free_version = nullptr;
// Load the drmGetVersion symbol
status = libdrm.load_symbol(reinterpret_cast<drmGetVersion_t *>(&drm_get_version),
"drmGetVersion");
if (status != AMDSMI_STATUS_SUCCESS) {
drm_get_version = nullptr;
libdrm.unload();
close(drm_fd);
ss << __PRETTY_FUNCTION__
<< " | Failed to load drmGetVersion symbol"
<< "; Returning: " << smi_amdgpu_get_status_string(status, false);
LOG_ERROR(ss);
return status;
}
if ((drm_version->version_major <= major_version)
&& (drm_version->version_minor <= minor_version)
&& (drm_version->version_patchlevel < patch_version)) {
amd::smi::AMDSmiSystem::getInstance().clean_up_drm();
close(drm_fd);
return AMDSMI_STATUS_NOT_SUPPORTED;
}
// Load the drmFreeVersion symbol
status = libdrm.load_symbol(reinterpret_cast<drmFreeVersion_t *>(&drm_free_version),
"drmFreeVersion");
if (status != AMDSMI_STATUS_SUCCESS) {
drm_free_version = nullptr;
libdrm.unload();
close(drm_fd);
ss << __PRETTY_FUNCTION__
<< " | Failed to load drmFreeVersion symbol"
<< "; Returning: " << smi_amdgpu_get_status_string(status, false);
LOG_ERROR(ss);
return status;
}
// get drm version. If it's older than 3.62.0, then say not supported and exit.
auto drm_version = drm_get_version(drm_fd);
// minimum version that supports getting of virtualization mode
int major_version = 3;
int minor_version = 62;
int patch_version = 0;
bool isDRMVersionSupported = false;
((drm_version->version_major >= major_version)
&& (drm_version->version_minor >= minor_version)
&& (drm_version->version_patchlevel >= patch_version) ?
isDRMVersionSupported = true : isDRMVersionSupported = false);
ss << __PRETTY_FUNCTION__ << " | drm_version: "
<< std::dec << drm_version->version_major << "." << drm_version->version_minor
<< "." << drm_version->version_patchlevel << "\n"
<< " | isDRMVersionSupported: " << (isDRMVersionSupported ? "TRUE" : "FALSE") << "\n"
<< " | Expecting version >= " << major_version << "." << minor_version
<< "." << patch_version << "\n"
<< "; Returning: " << (isDRMVersionSupported ?
smi_amdgpu_get_status_string(AMDSMI_STATUS_SUCCESS, false):
smi_amdgpu_get_status_string(AMDSMI_STATUS_NOT_SUPPORTED, false));
LOG_INFO(ss);
// Check if the version is supported
// If not, then return not supported
if (isDRMVersionSupported == false) {
drm_free_version(drm_version);
close(drm_fd);
libdrm.unload();
return AMDSMI_STATUS_NOT_SUPPORTED;
}
// Get the device info
typedef int (*drmCommandWrite_t)(int fd, unsigned long drmCommandIndex,
void *data, unsigned long size);
drmCommandWrite_t drmCommandWrite = nullptr;
// load symbol from libdrm
status = libdrm.load_symbol(reinterpret_cast<drmCommandWrite_t *>(&drmCommandWrite),
"drmCommandWrite");
if (status != AMDSMI_STATUS_SUCCESS) {
drm_free_version(drm_version);
close(drm_fd);
libdrm.unload();
ss << __PRETTY_FUNCTION__
<< " | Failed to load drmCommandWrite symbol: " << strerror(errno)
<< " | returning AMDSMI_STATUS_DRM_ERROR";
LOG_ERROR(ss);
return status;
}
// Get the device info
memset(&dev_info, 0, sizeof(struct drm_amdgpu_info_device));
struct drm_amdgpu_info request = {};
memset(&request, 0, sizeof(request));
request.return_pointer = reinterpret_cast<unsigned long long>(&dev_info);
request.return_size = sizeof(struct drm_amdgpu_info_device);
request.query = AMDGPU_INFO_DEV_INFO;
auto drm_write = drmCommandWrite(drm_fd, DRM_AMDGPU_INFO, &request,
sizeof(struct drm_amdgpu_info));
ss << __PRETTY_FUNCTION__
<< " | drm_fd: " << std::dec << drm_fd << "\n"
<< " | path: " << path << "\n"
<< " | drmCommandWrite: " << drm_write << "\n"
<< " | drmCommandWrite returned: " << strerror(errno) << "\n"
<< " | dev_info.ids_flags: " << dev_info.ids_flags << "\n"
<< " | dev_info.ids_flags size: " << sizeof(dev_info.ids_flags) << "\n"
<< " | dev_info.pci_rev: 0x"
<< std::setw(4) << std::setfill('0') << std::hex << dev_info.pci_rev << "\n"
<< " | dev_info.device_id: 0x"
<< std::setw(4) << std::setfill('0') << std::hex << dev_info.device_id;
LOG_INFO(ss);
if (drm_write == 0) {
uint32_t ids_flag = ((dev_info.ids_flags & AMDGPU_IDS_FLAGS_MODE_MASK)
>> AMDGPU_IDS_FLAGS_MODE_SHIFT);
switch (ids_flag) {
@@ -4225,15 +4706,31 @@ amdsmi_get_gpu_virtualization_mode(amdsmi_processor_handle processor_handle,
case 2: *mode = AMDSMI_VIRTUALIZATION_MODE_PASSTHROUGH; break;
default: *mode = AMDSMI_VIRTUALIZATION_MODE_UNKNOWN; break;
}
free(drm_version);
close(drm_fd);
amd::smi::AMDSmiSystem::getInstance().clean_up_drm();
std::string mode_str = "UNKNOWN";
if (virtualization_mode_map.find(*mode) != virtualization_mode_map.end()) {
mode_str.clear();
mode_str = virtualization_mode_map.at(*mode);
}
ss << __PRETTY_FUNCTION__
<< " | ids_flag: " << std::dec << ids_flag << "\n"
<< " | dev_info.ids_flags: 0x"
<< std::hex << std::setw(8) << std::setfill('0') << dev_info.ids_flags << "\n"
<< " | *mode: " << mode_str << "\n"
<< " | Returning: " << smi_amdgpu_get_status_string(status, false)
<< std::endl;
LOG_INFO(ss);
} else {
amd::smi::AMDSmiSystem::getInstance().clean_up_drm();
return AMDSMI_STATUS_DRM_ERROR;
ss << __PRETTY_FUNCTION__
<< " | Failed to get device info: " << strerror(errno)
<< " | returning AMDSMI_STATUS_DRM_ERROR";
LOG_ERROR(ss);
*mode = AMDSMI_VIRTUALIZATION_MODE_UNKNOWN;
status = AMDSMI_STATUS_DRM_ERROR;
}
return AMDSMI_STATUS_SUCCESS;
drm_free_version(drm_version);
close(drm_fd);
libdrm.unload();
return status;
}
src/amd_smi/amd_smi_drm.cc
+76 -133
Wyświetl plik
@@ -28,7 +28,6 @@
#include <memory>
#include <regex>
#include "amd_smi/impl/amd_smi_drm.h"
#include "amd_smi/impl/amdgpu_drm.h"
#include "amd_smi/impl/amd_smi_common.h"
#include "rocm_smi/rocm_smi.h"
#include "rocm_smi/rocm_smi_main.h"
@@ -59,12 +58,7 @@ std::string AMDSmiDrm::find_file_in_folder(const std::string& folder,
}
amdsmi_status_t AMDSmiDrm::init() {
// A few RAII handler
using drm_version_ptr = std::unique_ptr<drmVersion,
decltype(&drmFreeVersion)>;
// using drm_device_ptr = std::unique_ptr(drmDevicePtr,
// decltype(&drmFreeDevice));
std::ostringstream ss;
int fd = -1;
@@ -73,35 +67,47 @@ amdsmi_status_t AMDSmiDrm::init() {
return status;
}
typedef int (*drmCommandWrite_t)(int fd, unsigned long drmCommandIndex,
void *data, unsigned long size);
drmCommandWrite_t drmCommandWrite = nullptr;
// load symbol from libdrm
drm_cmd_write_ = nullptr;
status = lib_loader_.load_symbol(&drm_cmd_write_, "drmCommandWrite");
status = lib_loader_.load_symbol(reinterpret_cast<drmCommandWrite_t *>(&drmCommandWrite),
"drmCommandWrite");
if (status != AMDSMI_STATUS_SUCCESS) {
return status;
}
using drmGetDeviceType = int(*)(int, drmDevicePtr*); // drmGetDevice
using drmFreeDeviceType = void(*)(drmDevicePtr*); // drmFreeDevice
typedef int (*drmGetDevice_t)(int fd, drmDevicePtr *device); // drmGetDevice
typedef void (*drmFreeDevice_t)(drmDevicePtr *device); // drmFreeDevice
drmGetDeviceType drm_get_device = nullptr;
drmFreeDeviceType drm_free_device = nullptr;
drm_get_version_ = nullptr;
drm_free_version_ = nullptr;
drmGetDevice_t drm_get_device = nullptr;
drmFreeDevice_t drm_free_device = nullptr;
status = lib_loader_.load_symbol(&drm_get_version_, "drmGetVersion");
// Define a function pointer for drmGetVersion
typedef struct _drmVersion* (*drmGetVersion_t)(int fd); // drmGetVersion
drmGetVersion_t drm_get_version = nullptr;
typedef void (*drmFreeVersion_t)(drmVersionPtr version); // drmFreeVersion
drmFreeVersion_t drm_free_version = nullptr;
status = lib_loader_.load_symbol(
reinterpret_cast<drmGetVersion_t *>(&drm_get_version), "drmGetVersion");
if (status != AMDSMI_STATUS_SUCCESS) {
return status;
}
status = lib_loader_.load_symbol(&drm_free_version_, "drmFreeVersion");
status = lib_loader_.load_symbol(
reinterpret_cast<drmGetVersion_t *>(&drm_free_version), "drmFreeVersion");
if (status != AMDSMI_STATUS_SUCCESS) {
return status;
}
status = lib_loader_.load_symbol(&drm_get_device, "drmGetDevice");
status = lib_loader_.load_symbol(
reinterpret_cast<drmGetDevice_t *>(&drm_get_device), "drmGetDevice");
if (status != AMDSMI_STATUS_SUCCESS) {
return status;
}
status = lib_loader_.load_symbol(&drm_free_device, "drmFreeDevice");
status = lib_loader_.load_symbol(
reinterpret_cast<drmFreeDevice_t *>(&drm_free_device), "drmFreeDevice");
if (status != AMDSMI_STATUS_SUCCESS) {
return status;
}
@@ -133,8 +139,7 @@ amdsmi_status_t AMDSmiDrm::init() {
amdsmi_bdf_t bdf;
if (fd >= 0) {
auto version = drm_version_ptr(
drm_get_version_(fd), drm_free_version_);
auto version = drm_get_version(fd);
if (strcmp("amdgpu", version->name)) { // only amdgpu
close(fd);
fd = -1;
@@ -144,6 +149,29 @@ amdsmi_status_t AMDSmiDrm::init() {
close(fd);
fd = -1;
}
ss << __PRETTY_FUNCTION__ << " | "
<< " render file name: " << name << "\n"
<< "; fd: " << std::dec << fd << "\n"
<< "; drm version->name: " << version->name << "\n"
<< "; drm version->date: " << version->date << "\n"
<< "; drm version_major.version_minor.version_patchlevel: "
<< std::dec << version->version_major << "."
<< version->version_minor << "."
<< version->version_patchlevel << "\n"
<< "; device->deviceinfo.pci->vendor_id: 0x"
<< std::hex << std::setfill('0') << std::setw(4)
<< static_cast<uint32_t>(device->deviceinfo.pci->vendor_id) << "\n"
<< "; device->deviceinfo.pci->device_id: 0x"
<< std::hex << std::setfill('0') << std::setw(4)
<< static_cast<uint32_t>(device->deviceinfo.pci->device_id) << "\n"
<< "; device->deviceinfo.pci->revision_id: 0x"
<< std::hex << std::setfill('0') << std::setw(4)
<< static_cast<uint32_t>(device->deviceinfo.pci->revision_id) << "\n"
<< "; device->deviceinfo.pci->subdevice_id: 0x"
<< std::hex << std::setfill('0') << std::setw(4)
<< static_cast<uint32_t>(device->deviceinfo.pci->subdevice_id) << "\n";
LOG_INFO(ss);
drm_free_version(version);
}
drm_fds_.push_back(fd);
@@ -158,28 +186,37 @@ amdsmi_status_t AMDSmiDrm::init() {
std::ostringstream ss;
uint64_t bdf_rocm = 0;
rsmi_dev_pci_id_get(i, &bdf_rocm);
ss << __PRETTY_FUNCTION__ << " | "
<< "bdf_rocm | Received bdf: "
<< "\nWhole BDF: " << amd::smi::print_unsigned_hex_and_int(bdf_rocm)
<< "\nDomain = "
<< amd::smi::print_unsigned_hex_and_int((bdf_rocm & static_cast<uint64_t>(0xFFFFFFFF00000000)) >> 32)
<< "; \nBus# = " << amd::smi::print_unsigned_hex_and_int((bdf_rocm & 0xFF00) >> 8)
<< "; \nDevice# = "<< amd::smi::print_unsigned_hex_and_int((bdf_rocm & 0xF8) >> 3)
<< "; \nFunction# = " << amd::smi::print_unsigned_hex_and_int((bdf_rocm & 0x7));
LOG_INFO(ss);
bdf.function_number = ((bdf_rocm & 0x7));
bdf.device_number = ((bdf_rocm & 0xF8) >> 3);
bdf.bus_number = ((bdf_rocm & 0xFF00) >> 8);
bdf.domain_number = static_cast<uint32_t>(((bdf_rocm & 0xFFFFFFFF00000000) >> 32));
ss << __PRETTY_FUNCTION__ << " | " << "Received bdf: Domain = " << bdf.domain_number
<< "; Bus# = " << bdf.bus_number << "; Device# = "<< bdf.device_number
<< "; Function# = " << bdf.function_number;
LOG_INFO(ss);
vendor_id = device->deviceinfo.pci->vendor_id;
std::ostringstream bdf_sstream;
bdf_sstream << std::hex << std::setfill('0') << std::setw(4)
<< ((bdf_rocm >> 32) & 0xFFFFFFFF) << ":" // DOMAIN
<< std::hex << std::setfill('0') << std::setw(2)
<< ((bdf_rocm >> 8) & 0xFF) << ":" // BUS
<< std::hex << std::setfill('0') << std::setw(2)
<< ((bdf_rocm >> 3) & 0x1F) << "." // DEVICE
<< std::hex << std::setfill('0') << +(bdf_rocm & 0x7); // FUNCTION
bdf_sstream << "\n[Option 1] Partition ID ((pci_id >> 28) & 0xf): " << std::dec
<< static_cast<int>((bdf_rocm >> 28) & 0xf);
bdf_sstream << "\n[Option 2] Partition ID (pci_id & 0x7): " << std::dec
<< static_cast<int>(bdf_rocm & 0x7);
ss << __PRETTY_FUNCTION__ << " | "
<< "bdf_rocm | Received bdf: "
<< "\nWhole BDF: " << amd::smi::print_unsigned_hex_and_int(bdf_rocm)
<< "\nBDF = "
<< bdf_sstream.str() << "\n"
<< "; Vendor ID: 0x" << std::hex << std::setfill('0') << std::setw(4) << vendor_id;
LOG_INFO(ss);
bdf.domain_number = static_cast<uint64_t>(((bdf_rocm >> 32) & 0xFFFFFFFF));
bdf.bus_number = static_cast<uint64_t>(((bdf_rocm >> 8) & 0xFF));
bdf.device_number = static_cast<uint64_t>(((bdf_rocm >> 3) & 0x1F));
bdf.function_number = static_cast<uint64_t>((bdf_rocm & 0x7));
bdf.as_uint = bdf_rocm;
drm_bdfs_.push_back(bdf);
drm_free_device(&device);
close(fd);
}
// cannot find any valid fds.
@@ -203,100 +240,6 @@ amdsmi_status_t AMDSmiDrm::cleanup() {
return AMDSMI_STATUS_SUCCESS;
}
amdsmi_status_t AMDSmiDrm::amdgpu_query_driver_name(int fd, std::string& driver_name) {
// RAII handler
using drm_version_ptr = std::unique_ptr<drmVersion,
decltype(&drmFreeVersion)>;
std::lock_guard<std::mutex> guard(drm_mutex_);
auto version = drm_version_ptr(
drm_get_version_(fd), drm_free_version_);
if (version == nullptr) return AMDSMI_STATUS_DRM_ERROR;
driver_name = version->name;
return AMDSMI_STATUS_SUCCESS;
}
amdsmi_status_t AMDSmiDrm::amdgpu_query_driver_date(int fd, std::string& driver_date) {
// RAII handler
using drm_version_ptr = std::unique_ptr<drmVersion,
decltype(&drmFreeVersion)>;
std::lock_guard<std::mutex> guard(drm_mutex_);
auto version = drm_version_ptr(
drm_get_version_(fd), drm_free_version_);
if (version == nullptr) return AMDSMI_STATUS_DRM_ERROR;
driver_date = version->date;
return AMDSMI_STATUS_SUCCESS;
}
amdsmi_status_t AMDSmiDrm::amdgpu_query_info(int fd, unsigned info_id,
unsigned size, void *value) {
if (drm_cmd_write_ == nullptr) return AMDSMI_STATUS_NOT_SUPPORTED;
std::lock_guard<std::mutex> guard(drm_mutex_);
struct drm_amdgpu_info request;
memset(&request, 0, sizeof(request));
request.return_pointer = (uintptr_t)value;
request.return_size = size;
request.query = info_id;
int status = drm_cmd_write_(fd, DRM_AMDGPU_INFO,
&request, sizeof(struct drm_amdgpu_info));
if (status == 0) return AMDSMI_STATUS_SUCCESS;
return AMDSMI_STATUS_DRM_ERROR;
}
amdsmi_status_t AMDSmiDrm::amdgpu_query_fw(int fd, unsigned info_id,
unsigned fw_type, unsigned size, void *value) {
if (drm_cmd_write_ == nullptr) return AMDSMI_STATUS_NOT_SUPPORTED;
std::lock_guard<std::mutex> guard(drm_mutex_);
struct drm_amdgpu_info request;
memset(&request, 0, sizeof(request));
request.return_pointer = (uintptr_t)value;
request.return_size = size;
request.query = info_id;
request.query_fw.fw_type = fw_type;
int status = drm_cmd_write_(fd, DRM_AMDGPU_INFO, &request,
sizeof(struct drm_amdgpu_info));
if (status == 0) return AMDSMI_STATUS_SUCCESS;
return AMDSMI_STATUS_DRM_ERROR;
}
amdsmi_status_t AMDSmiDrm::amdgpu_query_hw_ip(int fd, unsigned info_id,
unsigned hw_ip_type, unsigned size, void *value) {
if (drm_cmd_write_ == nullptr) return AMDSMI_STATUS_NOT_SUPPORTED;
std::lock_guard<std::mutex> guard(drm_mutex_);
struct drm_amdgpu_info request;
memset(&request, 0, sizeof(request));
request.return_pointer = (uintptr_t)value;
request.return_size = size;
request.query = info_id;
request.query_hw_ip.type = hw_ip_type;
int status = drm_cmd_write_(fd, DRM_AMDGPU_INFO, &request,
sizeof(struct drm_amdgpu_info));
if (status == 0) return AMDSMI_STATUS_SUCCESS;
return AMDSMI_STATUS_DRM_ERROR;
}
amdsmi_status_t AMDSmiDrm::amdgpu_query_vbios(int fd, void *info) {
if (drm_cmd_write_ == nullptr) return AMDSMI_STATUS_NOT_SUPPORTED;
std::lock_guard<std::mutex> guard(drm_mutex_);
struct drm_amdgpu_info request;
memset(&request, 0, sizeof request);
request.return_pointer = (uint64_t) info;
request.return_size = sizeof(drm_amdgpu_info_vbios);
request.query = AMDGPU_INFO_VBIOS;
request.vbios_info.type = AMDGPU_INFO_VBIOS_INFO;
int status = drm_cmd_write_(fd, DRM_AMDGPU_INFO, &request,
sizeof(struct drm_amdgpu_info));
if (status == 0) return AMDSMI_STATUS_SUCCESS;
return AMDSMI_STATUS_DRM_ERROR;
}
amdsmi_status_t AMDSmiDrm::get_drm_fd_by_index(uint32_t gpu_index, uint32_t *fd_info) const {
if (gpu_index + 1 > drm_fds_.size()) return AMDSMI_STATUS_NOT_SUPPORTED;
if (drm_fds_[gpu_index] < 0 ) return AMDSMI_STATUS_NOT_SUPPORTED;
@@ -335,7 +278,7 @@ std::vector<std::string>& AMDSmiDrm::get_drm_paths() {
}
bool AMDSmiDrm::check_if_drm_is_supported() {
return (drm_cmd_write_ != NULL && drm_bdfs_.size() >0) ? true : false;
return (drm_bdfs_.size() >0) ? true : false;
}
std::vector<amdsmi_bdf_t> AMDSmiDrm::get_bdfs() {
src/amd_smi/amd_smi_gpu_device.cc
+1 -58
Wyświetl plik
@@ -109,7 +109,7 @@ std::string& AMDSmiGPUDevice::get_gpu_path() {
}
amdsmi_bdf_t AMDSmiGPUDevice::get_bdf() {
return bdf_;
return this->bdf_;
}
uint32_t AMDSmiGPUDevice::get_vendor_id() {
@@ -159,63 +159,6 @@ pthread_mutex_t* AMDSmiGPUDevice::get_mutex() {
return amd::smi::GetMutex(gpu_id_);
}
amdsmi_status_t AMDSmiGPUDevice::amdgpu_query_info(unsigned info_id,
unsigned size, void *value) const {
amdsmi_status_t ret;
uint32_t fd = 0;
ret = drm_.get_drm_fd_by_index(gpu_id_, &fd);
if (ret != AMDSMI_STATUS_SUCCESS) return AMDSMI_STATUS_NOT_SUPPORTED;
return drm_.amdgpu_query_info(fd, info_id, size, value);
}
amdsmi_status_t AMDSmiGPUDevice::amdgpu_query_driver_name(std::string& name) const {
amdsmi_status_t ret;
uint32_t fd = 0;
ret = drm_.get_drm_fd_by_index(gpu_id_, &fd);
if (ret != AMDSMI_STATUS_SUCCESS) return AMDSMI_STATUS_NOT_SUPPORTED;
return drm_.amdgpu_query_driver_name(fd, name);
}
amdsmi_status_t AMDSmiGPUDevice::amdgpu_query_driver_date(std::string& date) const {
amdsmi_status_t ret;
uint32_t fd = 0;
ret = drm_.get_drm_fd_by_index(gpu_id_, &fd);
if (ret != AMDSMI_STATUS_SUCCESS) return AMDSMI_STATUS_NOT_SUPPORTED;
return drm_.amdgpu_query_driver_date(fd, date);
}
amdsmi_status_t AMDSmiGPUDevice::amdgpu_query_hw_ip(unsigned info_id,
unsigned hw_ip_type, unsigned size, void *value) const {
amdsmi_status_t ret;
uint32_t fd = 0;
ret = drm_.get_drm_fd_by_index(gpu_id_, &fd);
if (ret != AMDSMI_STATUS_SUCCESS) return AMDSMI_STATUS_NOT_SUPPORTED;
return drm_.amdgpu_query_hw_ip(fd, info_id, hw_ip_type, size, value);
}
amdsmi_status_t AMDSmiGPUDevice::amdgpu_query_fw(unsigned info_id,
unsigned fw_type, unsigned size, void *value) const {
amdsmi_status_t ret;
uint32_t fd = 0;
ret = drm_.get_drm_fd_by_index(gpu_id_, &fd);
if (ret != AMDSMI_STATUS_SUCCESS) return AMDSMI_STATUS_NOT_SUPPORTED;
return drm_.amdgpu_query_fw(fd, info_id, fw_type, size, value);
}
amdsmi_status_t AMDSmiGPUDevice::amdgpu_query_vbios(void *info) const {
amdsmi_status_t ret;
uint32_t fd = 0;
ret = drm_.get_drm_fd_by_index(gpu_id_, &fd);
if (ret != AMDSMI_STATUS_SUCCESS) return AMDSMI_STATUS_NOT_SUPPORTED;
return drm_.amdgpu_query_vbios(fd, info);
}
int32_t AMDSmiGPUDevice::get_compute_process_list_impl(GPUComputeProcessList_t& compute_process_list,
ComputeProcessListType_t list_type)
src/amd_smi/amd_smi_system.cc
+2 -4
Wyświetl plik
@@ -23,15 +23,14 @@
#include <sstream>
#include <iomanip>
#include <fstream>
#include <cerrno>
#include <cstring>
#include "amd_smi/impl/amd_smi_system.h"
#include "amd_smi/impl/amd_smi_gpu_device.h"
#include "amd_smi/impl/amd_smi_common.h"
#include "amd_smi/impl/amd_smi_utils.h"
#include "rocm_smi/rocm_smi.h"
#include "rocm_smi/rocm_smi_main.h"
#include <fstream>
#include <cerrno>
#include <cstring>
namespace amd {
namespace smi {
@@ -304,7 +303,6 @@ amdsmi_status_t AMDSmiSystem::cleanup() {
if (!processors_.empty()) {processors_.clear();}
if (!sockets_.empty()) {sockets_.clear();}
init_flag_ &= ~AMDSMI_INIT_AMD_GPUS;
amd::smi::AMDSmiSystem::getInstance().clean_up_drm();
rsmi_status_t ret = rsmi_shut_down();
if (ret != RSMI_STATUS_SUCCESS) {
return amd::smi::rsmi_to_amdsmi_status(ret);
src/amd_smi/amd_smi_utils.cc
+85 -12
Wyświetl plik
@@ -23,6 +23,7 @@
#include <limits.h>
#include <sys/ioctl.h>
#include <libdrm/amdgpu.h>
#include <libdrm/drm.h>
#include <errno.h>
#include <fcntl.h>
#include <stdint.h>
@@ -32,8 +33,6 @@
#include <sys/mman.h>
#include <time.h>
#include <unistd.h>
#include <xf86drm.h>
#include <xf86drmMode.h>
#include <dirent.h>
#include <sys/types.h>
@@ -582,21 +581,13 @@ amdsmi_status_t smi_amdgpu_get_pcie_speed_from_pcie_type(uint16_t pcie_type, uin
return AMDSMI_STATUS_SUCCESS;
}
amdsmi_status_t smi_amdgpu_get_market_name_from_dev_id(amd::smi::AMDSmiGPUDevice* device, char *market_name) {
amdsmi_status_t smi_amdgpu_get_market_name_from_dev_id(amd::smi::AMDSmiGPUDevice* device,
char *market_name) {
if (market_name == nullptr || device == nullptr) {
return AMDSMI_STATUS_ARG_PTR_NULL;
}
std::ostringstream ss;
// requires libdrm being active
if (!device->check_if_drm_is_supported()) {
ss << __PRETTY_FUNCTION__ << " | DRM is not supported";
LOG_ERROR(ss);
return AMDSMI_STATUS_NOT_SUPPORTED;
}
uint32_t major_version, minor_version;
amdgpu_device_handle device_handle = nullptr;
std::string render_name = device->get_gpu_path();
int fd = -1;
std::string path = "/dev/dri/" + render_name;
@@ -612,7 +603,60 @@ amdsmi_status_t smi_amdgpu_get_market_name_from_dev_id(amd::smi::AMDSmiGPUDevice
<< render_name << "; path: " << path << "; fd: " << fd;
LOG_DEBUG(ss);
amd::smi::AMDSmiLibraryLoader libdrm_amdgpu_;
amdsmi_status_t status = libdrm_amdgpu_.load("libdrm_amdgpu.so");
if (status != AMDSMI_STATUS_SUCCESS) {
close(fd);
libdrm_amdgpu_.AMDSmiLibraryLoader::unload();
return status;
}
// Function pointer typedefs
typedef int (*amdgpu_device_initialize_t)(int fd, uint32_t *major_version,
uint32_t *minor_version,
amdgpu_device_handle *device_handle);
typedef int (*amdgpu_device_deinitialize_t)(amdgpu_device_handle device_handle);
typedef const char* (*amdgpu_get_marketing_name_t)(amdgpu_device_handle device_handle);
amdgpu_device_initialize_t amdgpu_device_initialize = nullptr;
amdgpu_device_deinitialize_t amdgpu_device_deinitialize = nullptr;
amdgpu_get_marketing_name_t amdgpu_get_marketing_name = nullptr;
status = libdrm_amdgpu_.load_symbol(
reinterpret_cast<amdgpu_device_initialize_t *>(&amdgpu_device_initialize),
"amdgpu_device_initialize");
if (status != AMDSMI_STATUS_SUCCESS) {
close(fd);
libdrm_amdgpu_.AMDSmiLibraryLoader::unload();
return status;
}
amdgpu_device_handle device_handle = nullptr;
uint32_t major_version, minor_version;
int ret = amdgpu_device_initialize(fd, &major_version, &minor_version, &device_handle);
if (ret != 0) {
close(fd);
libdrm_amdgpu_.AMDSmiLibraryLoader::unload();
return AMDSMI_STATUS_DRM_ERROR;
}
status = libdrm_amdgpu_.load_symbol(
reinterpret_cast<amdgpu_get_marketing_name_t *>(
&amdgpu_get_marketing_name), "amdgpu_get_marketing_name");
if (status != AMDSMI_STATUS_SUCCESS) {
close(fd);
libdrm_amdgpu_.AMDSmiLibraryLoader::unload();
return status;
}
status = libdrm_amdgpu_.load_symbol(reinterpret_cast<amdgpu_device_deinitialize_t *>(
&amdgpu_device_deinitialize), "amdgpu_device_deinitialize");
if (status != AMDSMI_STATUS_SUCCESS) {
close(fd);
libdrm_amdgpu_.AMDSmiLibraryLoader::unload();
return status;
}
ret = amdgpu_device_initialize(fd, &major_version, &minor_version, &device_handle);
if (ret != 0) {
std::string empty = "";
std::strncpy(market_name, empty.c_str(), AMDSMI_256_LENGTH - 1);
@@ -628,11 +672,25 @@ amdsmi_status_t smi_amdgpu_get_market_name_from_dev_id(amd::smi::AMDSmiGPUDevice
market_name[AMDSMI_256_LENGTH - 1] = '\0';
amdgpu_device_deinitialize(device_handle);
close(fd);
libdrm_amdgpu_.AMDSmiLibraryLoader::unload();
ss << __PRETTY_FUNCTION__ << " | path: " << path << "\n"
<< " | fd: "<< std::dec << fd << "\n"
<< " | Marketing Name: " << market_name << "\n"
<< " | Returning: "
<< smi_amdgpu_get_status_string(AMDSMI_STATUS_SUCCESS, false) << "\n";
LOG_INFO(ss);
return AMDSMI_STATUS_SUCCESS;
}
amdgpu_device_deinitialize(device_handle);
close(fd);
libdrm_amdgpu_.AMDSmiLibraryLoader::unload();
ss << __PRETTY_FUNCTION__ << " | path: " << path << "\n"
<< " | fd: "<< std::dec << fd << "\n"
<< " | Marketing Name: " << market_name << "\n"
<< " | Returning: "
<< smi_amdgpu_get_status_string(AMDSMI_STATUS_DRM_ERROR, false) << "\n";
LOG_INFO(ss);
return AMDSMI_STATUS_DRM_ERROR;
}
@@ -1109,3 +1167,18 @@ amdsmi_status_t amdsmi_get_gpu_cper_entries_by_path(
return AMDSMI_STATUS_SUCCESS;
}
void amdsmi_wait_for_user_input(void) {
for (;;) {
std::cout << "\n\t**Press any key to continue**" << std::endl;
int input = std::cin.get();
if (input == EOF) {
std::cout << "EOF detected. Exiting." << std::endl;
return;
}
char input_char = static_cast<char>(input);
std::cout << "User entered: " << input_char << std::endl;
if (input_char == '\n') {
return;
}
}
}
tests/amd_smi_test/CMakeLists.txt
+1
Wyświetl plik
@@ -1,3 +1,4 @@
set(CMAKE_VERBOSE_MAKEFILE on)
# Required Defines first:
option(INSTALL_GTEST "Install GTest (only useful if GTest is not already installed)" OFF)
tests/amd_smi_test/functional/id_info_read.cc
+5 -3
Wyświetl plik
@@ -139,8 +139,9 @@ void TestIdInfoRead::Run(void) {
IF_VERB(STANDARD) {
std::cout << "\t**Device Vram type id: "
<< vram_info.vram_type << std::endl;
std::cout << "\t**Device Vram vendor id: "
<< vram_info.vram_vendor << std::endl;
std::cout << "\t**Device Vram vendor id: 0x"
<< std::hex << std::setw(4) << std::setfill('0') << vram_info.vram_vendor
<< " (" << std::dec << vram_info.vram_vendor << ")" << std::endl;
std::cout << "\t**Device Vram size: 0x"
<< std::hex << vram_info.vram_size
<< " (" << std::dec << vram_info.vram_size << ")"
@@ -242,7 +243,8 @@ void TestIdInfoRead::Run(void) {
ASSERT_EQ(err, AMDSMI_STATUS_INVAL);
amdsmi_virtualization_mode_t vmode;
err = amdsmi_get_gpu_virtualization_mode(processor_handles_[i], &vmode);
ASSERT_EQ(err, AMDSMI_STATUS_SUCCESS);
ASSERT_TRUE(err == AMDSMI_STATUS_SUCCESS ||
err == AMDSMI_STATUS_NOT_SUPPORTED);
IF_VERB(STANDARD) {
auto it = virtualization_mode_map.find(vmode);
if (it != virtualization_mode_map.end()) {